JPS54109783A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54109783A
JPS54109783A JP1715278A JP1715278A JPS54109783A JP S54109783 A JPS54109783 A JP S54109783A JP 1715278 A JP1715278 A JP 1715278A JP 1715278 A JP1715278 A JP 1715278A JP S54109783 A JPS54109783 A JP S54109783A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
sio
si
film
poly
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1715278A
Inventor
Hiroshi Koshimizu
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To ensure the independent adjustment of the film thicknes with no lowering of the dielectric strength of SiO2 by providing previously the SiO2 of the necessary thickness on the poly Si and then covering the SiO2 with the Si3N4 to suppress the growth of the SiO2.
CONSTITUTION: SiO210∼12, P-type channel stopper 9 and B-ion injection layer 13 are provided on P-type Si substrate 8, and then covered with poly Si14 with SiO215 formed on the surface. Then Si3N416 is coated to etch off 16∼14 in sequence by means of resist mask 17. After removal of the mask, film 11 is removed to form SiO218 newly, and then film 16 is removed. Then poly Si19 of the 2nd layer is coated. Film 19 is then photo-etched to form phosphorus diffusion layer 20 and 21 using film 10 as the mask. In this method, the adjustment is possible for the thickness of each oxide film, and the SiO2 exists under the Si3N4 film along with the poly Si functioning as the stopper of the photo etching. As a result, all procedures can be performed by the wet etching method by just forming the SiO2 on the Si3N4.
COPYRIGHT: (C)1979,JPO&Japio
JP1715278A 1978-02-16 1978-02-16 Manufacture of semiconductor device Pending JPS54109783A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1715278A JPS54109783A (en) 1978-02-16 1978-02-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1715278A JPS54109783A (en) 1978-02-16 1978-02-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54109783A true true JPS54109783A (en) 1979-08-28

Family

ID=11936003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1715278A Pending JPS54109783A (en) 1978-02-16 1978-02-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54109783A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161874A (en) * 1983-02-23 1984-09-12 Texas Instruments Inc Floating gate memory and method of producing same
JPS6273774A (en) * 1985-09-27 1987-04-04 Toshiba Corp Manufacture of semiconductor memory
JPS63186478A (en) * 1987-01-29 1988-08-02 Fujitsu Ltd Eprom cell
USRE34535E (en) * 1983-02-23 1994-02-08 Texas Instruments Incorporated Floating gate memory with improved dielectric

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161874A (en) * 1983-02-23 1984-09-12 Texas Instruments Inc Floating gate memory and method of producing same
USRE34535E (en) * 1983-02-23 1994-02-08 Texas Instruments Incorporated Floating gate memory with improved dielectric
JPS6273774A (en) * 1985-09-27 1987-04-04 Toshiba Corp Manufacture of semiconductor memory
JPS63186478A (en) * 1987-01-29 1988-08-02 Fujitsu Ltd Eprom cell

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