JPS57170548A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS57170548A
JPS57170548A JP5610281A JP5610281A JPS57170548A JP S57170548 A JPS57170548 A JP S57170548A JP 5610281 A JP5610281 A JP 5610281A JP 5610281 A JP5610281 A JP 5610281A JP S57170548 A JPS57170548 A JP S57170548A
Authority
JP
Japan
Prior art keywords
holes
sio2
si3n4
etching
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5610281A
Other languages
Japanese (ja)
Other versions
JPS6217866B2 (en
Inventor
Hiroyuki Sakai
Tsutomu Fujita
Toyoki Takemoto
Kenji Kawakita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5610281A priority Critical patent/JPS57170548A/en
Publication of JPS57170548A publication Critical patent/JPS57170548A/en
Publication of JPS6217866B2 publication Critical patent/JPS6217866B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape

Abstract

PURPOSE:To finely isolate insulators by isotropically etching an Si substrate with two-layer mask of SiO2 and Si3N4, then anisotropically etching the substrate further deeply to open holes, laminating SiO2, Si3N4 in the holes, then anisotropically etching it, and then burying the holes with a CVD SiO2. CONSTITUTION:An SiO2 film 24 and an Si3N4 film 25 are laminated on an n type Si 23, a resist mask 26 is covered, and holes 23a are opened. When the n type layer 23 is then chemically etched, the etching is isotropically progressed, and overhangs of insulating films are formed. Then, a reactive sputter etching is performed to open vertical holes 23C. The resist 26 is removed, the holes are selectively covered with an SiO2 27, and Si3N4 is superposed. A reactive sputter etching is then performed to remove only the Si3N4 on the lower surface, which is allowed to remain on the side surface by a self-alignment. Thereafter, it is oxidized under high pressure to bury the SiO2 29 in the holes for a short time. According to this structure, an element isolation layer can be completed without bird head, the stress applied to the substrate at the oxidizing time can be alleviated, and crystalline defect can be reduced.
JP5610281A 1981-04-13 1981-04-13 Semiconductor device and manufacture thereof Granted JPS57170548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5610281A JPS57170548A (en) 1981-04-13 1981-04-13 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5610281A JPS57170548A (en) 1981-04-13 1981-04-13 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS57170548A true JPS57170548A (en) 1982-10-20
JPS6217866B2 JPS6217866B2 (en) 1987-04-20

Family

ID=13017734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5610281A Granted JPS57170548A (en) 1981-04-13 1981-04-13 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS57170548A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6115344A (en) * 1984-06-29 1986-01-23 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of forming semiconductor structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0231460U (en) * 1988-08-22 1990-02-27

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54128298A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Selective oxidizing method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54128298A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Selective oxidizing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6115344A (en) * 1984-06-29 1986-01-23 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of forming semiconductor structure
JPH0526337B2 (en) * 1984-06-29 1993-04-15 Intaanashonaru Bijinesu Mashiinzu Corp

Also Published As

Publication number Publication date
JPS6217866B2 (en) 1987-04-20

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