JPS5780735A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5780735A
JPS5780735A JP15672680A JP15672680A JPS5780735A JP S5780735 A JPS5780735 A JP S5780735A JP 15672680 A JP15672680 A JP 15672680A JP 15672680 A JP15672680 A JP 15672680A JP S5780735 A JPS5780735 A JP S5780735A
Authority
JP
Japan
Prior art keywords
layer
substrate
mask
film
thinner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15672680A
Other languages
Japanese (ja)
Inventor
Junichi Matsunaga
Hiroshi Nozawa
Hisahiro Matsukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15672680A priority Critical patent/JPS5780735A/en
Publication of JPS5780735A publication Critical patent/JPS5780735A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To obtain a semiconductor device having preferable characteristics by forming a layer having faster oxidation speed than a semiconductor substrate on the substrate and forming a mask thinner than the layer, thereby selectively oxidizing. CONSTITUTION:An SiO2 2 and P-adding Si 3 are superposed on a P type Si substrate 1, and Si3N4 mask 4 is formed thinner than the sum of the layers 2 and 3. A P<+> type channel stopper 5 is formed by B ion injection, is selectively oxidized, and a thick oxidized film 6 is superposed thereon. When the mask 4 is removed, the layer 3 is etched by reactive sputter ion etching, and is vertically opened, a layer 3'' remains at the overhang of the film 6. The film 2 is removed to form a gate oxidized film 7, and an MOSFET is completed thereafter as the ordinary method. According to this structure, the selective oxidation time can be remarkably shortened, and the Si3N4 mask is thinner than the sum of the layers 2 and 3. Accordingly, no stress deformation occurs in the substrate at the oxidizing time, thereby obtaining an MOS device having preferable characteristics.
JP15672680A 1980-11-07 1980-11-07 Manufacture of semiconductor device Pending JPS5780735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15672680A JPS5780735A (en) 1980-11-07 1980-11-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15672680A JPS5780735A (en) 1980-11-07 1980-11-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5780735A true JPS5780735A (en) 1982-05-20

Family

ID=15633982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15672680A Pending JPS5780735A (en) 1980-11-07 1980-11-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5780735A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045039A (en) * 1983-08-23 1985-03-11 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045039A (en) * 1983-08-23 1985-03-11 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device

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