JPS5779642A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5779642A
JPS5779642A JP15614580A JP15614580A JPS5779642A JP S5779642 A JPS5779642 A JP S5779642A JP 15614580 A JP15614580 A JP 15614580A JP 15614580 A JP15614580 A JP 15614580A JP S5779642 A JPS5779642 A JP S5779642A
Authority
JP
Japan
Prior art keywords
polycrystalline
layer
oxide film
mask
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15614580A
Other languages
Japanese (ja)
Inventor
Hisahiro Matsukawa
Hiroshi Nozawa
Junichi Matsunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15614580A priority Critical patent/JPS5779642A/en
Publication of JPS5779642A publication Critical patent/JPS5779642A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals

Abstract

PURPOSE:To enable to obtain a semiconductor substrate having few generation of defect improving the element isolation technique by a method wherein a polycrystalline Si layer provided on the semiconductor substrate is oxidized selectively, and after a mask is removed, doping in the polycrystalline Si layer is performed, and after a surface oxide film is formed, the oxide film thereof and a part of the remaining polycrystalline Si layer are removed. CONSTITUTION:The polycrystalline Si layer 13 is provided on the Si substrate 11 interposing an oxide film 12 between them, and after selective etching is performed making the Si3N4 film as a mask to form thick oxide films 16, the Si3N4 mask is removed, then after an impurity is doped in the polycrystalline Si layer to enhance oxidation speed, the thin theral oxide film is formed on the surface, and after then the thermal oxide film is removed and at the same time, oxynitride films 17 are removed, a part of the remained polycrystalline Si layer 13' is removed, and the remained polycrystalline Si layer is oxidized. Accordingly thermal isolation films can be formed reducing generation of defect, and moreover accuracy variation in size cn be reduced.
JP15614580A 1980-11-06 1980-11-06 Manufacture of semiconductor device Pending JPS5779642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15614580A JPS5779642A (en) 1980-11-06 1980-11-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15614580A JPS5779642A (en) 1980-11-06 1980-11-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5779642A true JPS5779642A (en) 1982-05-18

Family

ID=15621307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15614580A Pending JPS5779642A (en) 1980-11-06 1980-11-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5779642A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6464325A (en) * 1987-09-04 1989-03-10 Denki Kagaku Kogyo Kk Electrode for plasma etching
US4818235A (en) * 1987-02-10 1989-04-04 Industry Technology Research Institute Isolation structures for integrated circuits
US5795814A (en) * 1995-03-04 1998-08-18 Nec Corporation Method for manufacturing semiconductor device having groove-type isolation area
US6127242A (en) * 1994-02-10 2000-10-03 Micron Technology, Inc. Method for semiconductor device isolation using oxygen and nitrogen ion implantations to reduce lateral encroachment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4818235A (en) * 1987-02-10 1989-04-04 Industry Technology Research Institute Isolation structures for integrated circuits
JPS6464325A (en) * 1987-09-04 1989-03-10 Denki Kagaku Kogyo Kk Electrode for plasma etching
US6127242A (en) * 1994-02-10 2000-10-03 Micron Technology, Inc. Method for semiconductor device isolation using oxygen and nitrogen ion implantations to reduce lateral encroachment
US5795814A (en) * 1995-03-04 1998-08-18 Nec Corporation Method for manufacturing semiconductor device having groove-type isolation area

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