JPS56148841A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS56148841A JPS56148841A JP5205580A JP5205580A JPS56148841A JP S56148841 A JPS56148841 A JP S56148841A JP 5205580 A JP5205580 A JP 5205580A JP 5205580 A JP5205580 A JP 5205580A JP S56148841 A JPS56148841 A JP S56148841A
- Authority
- JP
- Japan
- Prior art keywords
- film
- si3n4
- patterned
- built
- polycrystal silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To decrease defective patterning and improve yield by a method wherein a mask necessary for introducing impurities is patterned before selective oxidation, and subsequent processes are self-aligned. CONSTITUTION:An N<-> type layer 21 is formed on an N<+> type substrate 20, a thermal oxide film 22 for decreasing strain is made up and an active base layer 36 is built up. An Si3N4 23 and a thin polycrystal silicon film 24 are formed as the first oxidation preventing films, and patterned by using an oversized mask. An Si3N4 film 25 as the second oxidatipn preventing film is made up, and patterned leaving base-emitter window sections. A field oxide film 26 is built up. Accurate patterning can be conducted by forming windows by utilizing difference between the etching characteristics of the polycrystal silicon 24 and the Si3N4 film 25.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5205580A JPS56148841A (en) | 1980-04-18 | 1980-04-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5205580A JPS56148841A (en) | 1980-04-18 | 1980-04-18 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56148841A true JPS56148841A (en) | 1981-11-18 |
Family
ID=12904115
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5205580A Pending JPS56148841A (en) | 1980-04-18 | 1980-04-18 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56148841A (en) |
-
1980
- 1980-04-18 JP JP5205580A patent/JPS56148841A/en active Pending
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