JPS5660015A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5660015A
JPS5660015A JP13627279A JP13627279A JPS5660015A JP S5660015 A JPS5660015 A JP S5660015A JP 13627279 A JP13627279 A JP 13627279A JP 13627279 A JP13627279 A JP 13627279A JP S5660015 A JPS5660015 A JP S5660015A
Authority
JP
Japan
Prior art keywords
layer
mask
film
oxide
ions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13627279A
Other languages
Japanese (ja)
Inventor
Kazuya Shibazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP13627279A priority Critical patent/JPS5660015A/en
Publication of JPS5660015A publication Critical patent/JPS5660015A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To form each region of a semiconductor device by self-alignment by a method wherein a step is provided between a film and an oxidized layer of thin film being provided on a semiconductor substrate, ions are inplanted using the oxide as a mask and then doping is performed using the film as a mask. CONSTITUTION:A monocrystalline Si 102 is made to grow on a sapphire substrate 101, and after an oxide film 103 is formed, etching is performed to make it to be a prescribed form. A polycrystalline Si 105', and a nitride film are formed in order, and a desired part of the polycrystalline Si is oxidized according to a photoechting process to form an oxide layer 108. P ions are implanted to form an n type layer 109 using this oxide as a mask, the layer 108 is removed and B ions are implanted to form a p type layer using the layer 105' as a mask. By this way, each region is made to be formed by self-alignment, the process of photoetching is reduced and the discrepancy of pattern positioning and the contamination to be given to the substrate can be suppressed.
JP13627279A 1979-10-22 1979-10-22 Manufacture of semiconductor device Pending JPS5660015A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13627279A JPS5660015A (en) 1979-10-22 1979-10-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13627279A JPS5660015A (en) 1979-10-22 1979-10-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5660015A true JPS5660015A (en) 1981-05-23

Family

ID=15171308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13627279A Pending JPS5660015A (en) 1979-10-22 1979-10-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5660015A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5678157A (en) * 1979-11-29 1981-06-26 Toshiba Corp Semiconductor device
JPS58123721A (en) * 1982-01-19 1983-07-23 Sumitomo Electric Ind Ltd Impurity doping method onto semiconductor crystal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5678157A (en) * 1979-11-29 1981-06-26 Toshiba Corp Semiconductor device
JPS6331106B2 (en) * 1979-11-29 1988-06-22 Tokyo Shibaura Electric Co
JPS58123721A (en) * 1982-01-19 1983-07-23 Sumitomo Electric Ind Ltd Impurity doping method onto semiconductor crystal

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