JPS6331106B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device constructed using a semiconductor layer on an insulating substrate, and in which semiconductor regions of different conductivity types are directly coupled.

An example of a semiconductor device in which semiconductor regions of different conductivity types are coupled via metal wiring is a complementary MOS inverter. This is a p-channel with a common drain, as shown in Figure 1.
A MOSFET and an n-channel MOSFET are arranged in parallel in multiple stages, and the first stage is a p-channel MOSFET1.
The connection point between the drain of MOSFET a and the drain of n-channel MOSFET 1b is connected to the second-stage p-channel MOSFET.
MOSFET2a and n-channel MOSFET2b
The third stage, fourth stage, and so on are connected in the same way. Conventionally, in such a semiconductor device, p-channel MOSFETs 1a, 2a...
drain (p layer) and n-channel MOSFET1
Connections to the drains (n layer) of the transistors b, 2b, . . . were made using Al wires. For this reason, an extra area was required for arranging the Al wires, which caused problems in improving the degree of integration.

It was thought that if semiconductor regions of different conductivity were directly bonded without using Al wires, an electrical barrier would be formed at the bonding area, causing problems in operation.

On the other hand, it has been found that ohmic contact can be realized without forming the barrier by including impurities of 10 ¹⁸ /cm ³ or more in each semiconductor region in order to eliminate the barrier that occurs at the bonding portion. (Special application 1974-74178).

The present inventors have discovered that in the case of SOS (Silicon on Sapphire), there are many defects, so even if the barrier exists, there is a sufficient leakage current of the barrier (p-n junction barrier). Even when the impurity concentration of the semiconductor region is 10 ¹⁸ /cm ³ or more, good electrical conduction can be obtained by direct coupling, and complementary MOS
We discovered that it can be used as an inverter.

This invention was made in view of the above points.
In a semiconductor device in which semiconductor layers of different conductivity types are bonded using a semiconductor layer provided on an insulating substrate such as SOS, conductivity types with an impurity concentration of 10 ¹⁸ /cm ³ or less can be obtained without using Al wire etc. An object of the present invention is to provide a semiconductor device in which semiconductor layers of different types are directly connected to each other to improve the degree of integration.

The details of this invention will be described below with reference to examples.

For example, as shown in FIGS. 2a to 2d, a highly impurity-concentrated n ⁺ layer 13 and a p ⁺ layer 14 are formed in an n ^- type silicon layer 12 provided on a sapphire substrate 11 so that their respective parts overlap. Alternatively, the n ⁺ layer 13 and the p ⁺ layer 14 are formed so that an electrical leakage current exists by diffusing them so that they are in contact with each other. In the case of SOS, as mentioned above, there are many crystal defects (10 ¹⁸ - 10 ¹¹ /cm ³ ) in the silicon film, and these form deep levels, which increases the generated current and makes it easy to reach the desired leakage current. can get. For this reason, there is no particular need to make the impurity concentration of the aforementioned semiconductor regions of different conductivity types higher than 10 ¹⁸ /cm ³ .

Furthermore, if it is desired to particularly increase the leakage current of this barrier (junction) in terms of circuit design, a structure as shown in FIGS. 2e to 2g may be used. That is, in e, n ⁺ layer 13
A p ^- layer (or n ^- layer, ideally an i layer) 15 is formed between the p ⁺ layer 14 and the p + layer 14, and the volume of the depletion layer is increased to effectively control the current generated in this region. It's getting bigger. In f, an impurity layer 16 (preferably a heavy metal such as Au, Ag, Cu or other impurity forming a deep level) that increases leakage current is formed near the boundary (junction) between the n ⁺ layer 13 and the p ⁺ layer 14. This layer is formed by ^ion implantation to form a deep level ⁱⁿ this region and further increase the leakage current. The leakage current is electrically increased between the ^p can.

Next, the present invention will be explained using the complementary MOS shown in FIG.
An embodiment applied to an inverter will be described with reference to FIG.

In the figure, 20 is a sapphire substrate, on the upper surface of which a field oxide film 21, a low impurity concentration n-type silicon layer 22, and a p-type silicon layer 23 are provided. Predetermined portions of these silicon layers 22 and 23, that is, the portions that will become the source and drain of the FET, have a very high impurity concentration (for example, 10 ²⁰ /cm ³ ).
A p ⁺⁺ layer 24, an n ⁺⁺ layer 27, a p ⁺ layer 25 with a high impurity concentration (for example, 10 ¹⁷ /cm ³ ), and an n ⁺ layer 26 are formed by adding impurities. and p ⁺ layer 25 and n ⁺
It is in contact with layer 26.

On the other hand, the p ⁺⁺ layer 24 and the p ⁺ layer 25, which become the channel region
on the n-type silicon layer 22 and the n ⁺ layer 26 between;
Polycrystalline silicon films 30 and 31 serving as gates are provided on the p-type silicon layer 23 between the n ⁺⁺ layers 27 via gate oxide films 28 and 29, respectively. An insulating protective film 32 is provided on the upper surface of these semiconductor layers, and at predetermined locations,
A hole is made for taking out the electrode, and the Al film 33,3
4 is provided.

In this way, a p channel is formed on the Saffire substrate 20.
A complementary MOS inverter is constructed in which the drain p ⁺ layer 25 and n ⁺ layer 26 of each MOSFET and n-channel MOSFET are directly connected. In other words, the p ⁺ layer 25 and the n ⁺ layer 26 form a barrier connection with a large leakage current.

With this configuration, there is no need for Al wiring for electrically connecting the p ⁺ layer 25, which not only simplifies the manufacturing process but also eliminates the need for the area of Al wiring for interconnection. , the degree of integration can be increased. Especially this kind of structure, i.e. SOS
In the case of structured integrated circuits, since the sapphire substrate is extremely expensive, it has been desired to increase the degree of integration of the elements as much as possible. Therefore, as in this example, connecting drains of different conductivity types directly to each other with a large leakage current without using Al wiring is extremely beneficial from the perspective of reducing product costs. be. Furthermore, since the load capacity is reduced, the switching speed is improved, and the high frequency characteristics, which are an advantage of this type of semiconductor device, can be further improved.

Next, the leakage current between the p ⁺ layer 25 and the n ⁺ layer 26 in this example will be estimated and looked at. In Figure 4,
Q ₁ is a drive n-channel FET, Q ₂ is a load p-channel FET, D is a diode formed between the aforementioned p ⁺ layer 25 and n ⁺ layer 26, and C ₁ is the load capacitance of the inverter. Now, the W/L of the drive transistor and load transistor is 8 μm/2 μm, respectively.
Assuming 4μm/2μm (β _R = 1/2), the load capacity per inverter stage is 0.02PF. Considering the case where the output is taken out from the upper side of the diode as shown in Figure 4, when the input is 0V, charging the load capacitance from the power supply side is done regardless of the diode.
The output will be V _DD =5V. When the input reaches 5V, _Q1 conducts and the charge is discharged from the load through diode D. At this time, if the diffusion potential of diode D is 0.4V, the output potential will rapidly decrease until it reaches 0.4V, but once it reaches 0.4V, discharge will occur through the leakage current of diode D. Now, if the load capacitance C ₁ is 0.02PF, 0.4V is
Roughly calculating the time t until it reaches 0V, assuming the diode leakage current I is 10 ^-6 A, t = 0.02 (PF) x 0.4 (V) / 10 ^-6 (A) = 8 (ns), i.e. , the output potential will drop to 0V in 8ns. This time is not a very large amount of time and is often not a problem. Furthermore, if this time is an issue, the system of the present invention can be fully used in digital circuits if the circuit is designed with the possibility that the low level of the output will float by 0.4V. In this example, it is also possible to reduce the diffusion potential of diode D. Furthermore, when using an inverter with such a structure according to the present invention in a semiconductor memory cell, the leakage current of the diode D must be made larger than the leakage current of the load transistor _Q2 , otherwise the consumption during standby of the semiconductor memory will be reduced. The power will be fixed by the diode D, which is inconvenient.

Furthermore, a method of taking the output from the lower side of the diode as shown in FIG. 5 is also conceivable. Regarding the effect of the leakage current of the diode D, the above explanation regarding FIG. 4 applies similarly, so the explanation will be omitted. However, in this case, the low level drops completely to 0V, so depending on the usage, it may be easier to use than the case shown in FIG. 4, and in some cases it is often desirable.

The magnitude of the leakage current between the semiconductor layers of different conductivity types is determined according to the desired characteristics of the complementary MOS inverter, and various values are used for design purposes. Also, if there is no barrier and the leakage current in this region is about the same, a resistive layer may be used.

Although the embodiment described above is applied to a complementary MOS inverter, the present invention is not limited thereto, and various modifications are possible. For example, MISFET using Si ₃ N ₄ , Al ₂ O ₃ , etc. as an insulating film,
It can be applied to other semiconductor devices using Ge, compound semiconductors, etc. as semiconductor layers. It can also be used for MES type FETs or MES type ICs using metal shot key barrier type gate structures.
Further, the substrate is not limited to sapphire, and various insulating substrates such as spinel, ruby, crystal, silicon carbide, etc. can be used.

As described above, according to the present invention, in a semiconductor device such as an SOS, a p-type layer and an n-type layer with an impurity concentration of 10 ¹⁸ /cm ³ or less are electrically connected by sharing or contacting a part with each other. By providing this, it is possible to provide an excellent semiconductor device with an improved degree of integration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a generally known complementary MOS inverter, FIGS. 2 a to g are diagrams for explaining the basic configuration of the present invention, and FIG. 3 is an embodiment of the present invention. Figures 4 and 5 showing the configuration of a certain MOS inverter are diagrams for explaining the effects of the embodiment of the present invention. 11...Sapphire substrate, 12...n ^- silicon layer, 13...n ⁺ layer, 14...p ⁺ layer, 20...
Saffire substrate, 21...Field oxide film, 2
2...n-type silicon layer, 23...p-type silicon layer, 24...p ⁺⁺ layer (source), 25...p ⁺ layer (drain), 26...n ⁺ layer (drain), 27...
...n ⁺⁺ layer (source), 28, 29...gate oxide film, 30, 31...polycrystalline silicon film, 32...
Protective film, 33, 34...Al film.

Claims (1)

[Claims] 1 A p-channel with an impurity concentration of 10 ¹⁸ /cm ³ or less in a semiconductor layer provided on an insulating substrate
MOSFET p-type drain layer and n-channel
The n-type drain layers of MOSFETs are partially shared or in contact with each other so as to be electrically conductive.
A semiconductor device characterized by forming a CMOS circuit.