JPS592363A - Complementary insulated gate field effect device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to complementary insulated field effect devices and, more particularly, to an arrangement that simplifies the interconnection of gate regions of such complementary devices.

DESCRIPTION OF THE PRIOR ART The prior art of the present invention can be better understood by reference to the drawings of FIGS. 1 and 2. FIG. Figure 2 shows
1 is a schematic diagram of a simple 0MO8FET (complementary metal oxide semiconductor field effect transistor) inverter; FIG. The inverter receives input through line 10. line 10
is connected to p, +1 of the P channel device 11 and r- of the N channel device 12, and generates an output on the line 13.

The manufacturing process of the CMOS converter shown in FIG. 2 is shown in FIG. This is illustrated at a manufacturing stage prior to forming the holes for the electrodes and patterning the metal. FIG. 1 includes an N-channel device in which a drain region 1 and a source region 6 are shown on either side of a doped polysilicon layer 12. The second device is a source 1 located on either side of the doped polysilicon gate 5.
and a P-channel device located in an N-type potential well 8 with a drain 4 . It must be noted that the )f-z polysilicon 2 and the doped polysilicon r-)5 are interconnected. Both transistors are located on a substrate 8 with P-type doping. If the two r-t regions are made with appropriate doping to create a channel on the surface, the N-channel region has r-t 2 with N-type doping, and the P-channel region has r-t 2 with N-type doping. ,
It has a P+ doped gate 5 (not shown) which is interconnected with the above r-). however,
If these layers are interconnected in this way,
p,% of polysilicon with N-type doping
A diode is formed at the junction between the t region and the r-t region of polysilicon doped with P type. One way to overcome this diode problem is to form a metal layer on top of the r-) region of the polysilicon. However, forming a jumper with a metal layer using this method requires more area and has the problem of hindering the ability to back the device densely over a small effective area on the surface of the semiconductor device. be.

A second solution, currently in use, is to connect a singly doped polysilicon root region to both the N-channel and P-channel devices.

This configuration is the same as the configuration shown in FIG. 1, and the cross-sectional views are shown in FIGS. 6a and 6b. A- in Figure 1
In FIG. 3, which shows a cross-sectional view along line A, the polysilicon interconnect strips are illustrated as regions 2 and 5 located over a substrate 8 with P-type doping. There is also an N-type potential well region 3 in the substrate for creating a P-channel device. At this time, since the polysilicon tate region 5 is an N-type doped polysilicon layer, a P-type channel must be formed at the location shown as the channel 9 by implantation. Date oxide layers 32 and 31 are located below gates 2 and 5.

Field oxide layers 17, 18, 19 are formed for insulation. A cross-sectional view along BB is shown in Figure 3b. FIG. 3b shows that an N-type doping is performed which is located in the soil of the date oxide layer 31 above the P-channel region 9 which is sandwiched between the source 7 and drain regions in the N-type potential well 3. A P-channel device with a polysilicon region 5 is illustrated. The N-type doped polysilicon r-HaM2 (connected to the gate region 5) is
Situated over a gate oxide layer 32 over an N-channel device having source region 1 and drain region 6 . 6th
Figure b also shows field oxide layers 18, 21 and 2 on substrate 8.
2 is illustrated. Although this configuration solves the problem with gated diodes, it requires an extra step in the P-channel device to create a P-type channel 9 between the source 1 and drain D, resulting in a P-channel device with less optimal buried channel behavior. - Channels are formed. As OMO8 devices become smaller and therefore more densely integrated, this type of configuration (ie, where the gate region is N+ polysilicon) becomes less advantageous.

It is an object of the present invention to provide a simple interconnect between P+ doped polysilicon gates and N+ doped polysilicon gates.

SUMMARY OF THE INVENTION In accordance with the present invention, a first device having a first pole of doped polysilicon (1) ft-region and a second pole of doped polysilicon are provided. A complementary insulated gate field effect device is disclosed having a second device with two gate regions. A capability is provided to enable an interconnection connecting r-) of the first device and the gate of the second device. This interconnect capability further includes a metal silicide overlying the polysilicon regions of these gates and subsequently disposed over the field oxide layer or gate oxide layer.

In the first embodiment, a first transistor has a first date region of polysilicon that has been doped with n+, and a second transistor has a second region of polysilicon that has been doped with p+. A complementary insulated field-effect circuit is provided having two transistors interconnected by creating a doped polysilicon layer interconnecting them over a field oxide layer. It has first and second gates.

The metal silicide layer is formed by disposing the metal silicide on the surface of the r-t region consisting of two doped polysilicon layers and doped polysilicon layer.
It is used to counteract the effects of diodes that form at +-doped polysilicon junctions.

DESCRIPTION OF PREFERRED EMBODIMENTS A detailed description of the invention will now be described with reference to specific embodiments with reference to the drawings.

FIG. 4 shows a C! The plan view of the MOS inverter, FIG. 4, is similar to the converter shown in FIG. 1, except for the P+ doped polysilicon layer 15' and the metal silicide layer 25.29.26. The metal silicide layers 25, 29, 26 are shown as thin strips to illustrate the doped polysilicon gate regions 2 and 5'. In a preferred embodiment,
A metal silicide layer overlies the doped polysilicon gate layer.

The present invention provides a simple configuration for interconnecting P-channel r-to and N-channel dates in complementary insulated gate field effect transistor devices.

This configuration is shown in Figures 5a and 5b. These drawings are cross-sectional views of FIG. 4. This configuration, shown in FIG. 4, has two gate areas, M 1 "'
This is an N+ doped polysilicon region coupled to a + doped polysilicon gate 5'. This junction region 19 is shown overlying field oxide layer 18 in FIG. 5a. The P-channel gate 5' is positioned over the N-type potential well 3 described above. N-channel gate 2 is located directly on substrate 8 . The structure includes a metal silicide layer covering the N+ doped polysilicon region 26, the N+ doped polysilicon layer 5', and the P+ doped polysilicon layer. Illustrated.

This layer 25 and 26 is a continuous layer that electrically interconnects the two date regions and shunts the diode barrier that occurs in region 29.

The P-channel device consists of a P-channel implanted layer (6th layer) formed on the previously required N-type potential well 3
(not shown in the figure) and is operating as an optimal surface channel device.

Figure 5b shows a cross-sectional view of the area along BB of Figure 4 in which the invention was implemented. Note that the silicide layers 25, 26 are positioned over the corresponding P+ and N"4"-) regions.

For the time being, those of ordinary skill in the art will be familiar with the process for a complementary insulated gate field effect device consisting of an N-channel device constructed in a P-type well and a P-channel device constructed on an N-type substrate. can be modified to be optimal with the silicon compound strap formation techniques disclosed herein.

In a preferred embodiment, the metal silicon compound is a platinum silicon compound (PtBl) or a molybdenum silicon compound (Mo81z, ) together with a refractory metal silicon compound such as a tungsten silicon compound (wet) or a titanium silicon compound ('I'181). This includes all precious metals such as By using the present invention, the complementary insulating (r-) field effect transistor device is optimally formed and the 01 and N+ region are connected by preventing the influence of diodes formed at their junction surfaces. We were able to provide a simple configuration.

Although specific embodiments have been described herein, this is not meant to be limiting. It is believed that those skilled in the art will understand that the present invention includes changes and modifications within the scope of the gist of the present invention as defined in the claims.

4. Brief Description of the Drawings Figure 1 is a plan view of a CMOS converter manufactured on a semiconductor substrate. Figure 2 is a schematic diagram of a CMOS converter.

FIG. 6a is a sectional view taken along line AA of FIG. M1 showing an embodiment of the prior art.

FIG. 6b is a sectional view taken along line BB in FIG. 1, showing an embodiment of the prior art.

FIG. 4 is a plan view of a CMOS converter embodying the present invention.

FIG. 5a shows a second version of the configuration of FIG. 4 illustrating the present invention. It is a sectional view along AA.

FIG. 5b is a cross-sectional view along line BB of the configuration of FIG. 4 illustrating the present invention.

Agent Akira Asamura Rg, Ja

Claims (5)

[Claims] (1) A first device having a first date region of polysilicon with a first pole doping, and a second device having a second date region of polysilicon with a second pole doping. The first doped polysilicon layer of the first pole extends from the first doped polysilicon layer.
a metal silicon compound layer covering a second doped polysilicon layer of the second electrode extending from the first and second doped polysilicon layers; and interconnect means for connecting said first gate to said second gate, located over a field oxide layer between said first and second gates. Electric boost effect circuit. (2) The complementary insulated gate field effect circuit of claim 1, wherein the metal silicon compound comprises a tungsten silicon compound. (3) The complementary insulated gate field effect circuit of claim 1, wherein the metal silicon compound comprises a titanium silicon compound. (4) The complementary insulated date field effect circuit according to claim 1, wherein the metal silicon compound comprises a platinum silicon compound. (5) N+ doped polysilicon located between the N+ doped source and drain formed in the P-type doped substrate over the silicon dioxide layer; a first having a gate region;
a gate region of N+ doped polysilicon located over a silicon dioxide layer located between a source and a y''=1 region, the source and date regions respectively being connected to the substrate; a second device having an N-type doped region; and a second device extending from the first N+ doped polysilicon layer extending from the second r-t. a gate of said first device with a metal silicide area positioned over a P+ doped polysilicon layer and over a field oxide layer between the two gates; and an interconnect means for connecting to a complementary insulated date field effect circuit.