KR0147776B1 - Wiring method of cmos inverter - Google Patents

Abstract

The present invention provides a method of forming a metal wiring on a substrate having a PMOS transistor and an NMOS transistor structure constituting a conventional CMOS inverter; Contacting and patterning a first conductive layer on a source region of each of the PMOS transistor and the NMOS transistor; Forming a first insulating film on the entire structure; Contacting and patterning a second conductive layer on a drain region and a first conductive layer of each of the PMOS transistor and the NMOS transistor; A method for forming an inverter metal wiring, comprising contacting and patterning a third conductive film on the second conductive film, wherein the source of the PMOS and the source of the NMOS are double metal wires when the inverter of the peripheral circuit is formed. After using the laminated metal or silicide rather than using the first metal used for the first metal, the first metal passes over it, so that the freedom of layout of the first metal is increased, so it is easy to design, and as the degree of freedom increases, There is an effect of reducing the area occupied by the circuit.

Description

How to connect CMOS inverter

1 is a conventional CMOS inverter circuit diagram.

2a to 2c is a wiring process diagram of a CMOS inverter according to an embodiment of the present invention.

3a and 3c are process diagrams of the connection of the CMOS inverter according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

201: N-well 202: P-well

203: field oxide film 204: gate oxide film

205 gate electrode 206 insulating film

207: spacer insulating film 208, 209: drain

208 ', 209': source 210: silicide film

211: interlayer insulating film 212: metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method of connecting a complementary metal-oxide-semiconductor (CMOS) inverter formed in a peripheral circuit region when a semiconductor device is manufactured.

In general, a double layer metallization (DLM) process using a lower metal interconnection and an upper metal interconnection is used for connection between devices forming a peripheral circuit.

Accordingly, a source of a PMOS transistor (P-type Metal-Oxide-Semiconductor transistor, hereinafter referred to as PMOS) and an NMOS transistor (N-type Metal-Oxide-Semiconductor) of an inverter, which is one of the elements constituting a peripheral circuit, are conventionally known. Although the interconnection of the source of a transistor (hereinafter referred to as NMOS) was made during the lower metal wiring process of the cell region, the complexity of the peripheral circuit region increased as the semiconductor device became more integrated, so that the lower metal wiring of other peripheral circuit elements including the inverter was increased. When forming, the process margin (degree of freedom) is reduced, which leads to difficulty in designing the layout, and the chip size increases as the area occupied by the peripheral circuits increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for connecting a CMOS inverter to secure a process margin of a lower metal wiring process of a double layer metal wiring in a peripheral circuit area while preventing chip area increase.

A characteristic method of connecting a CMOS inverter provided from the present invention is a method of connecting a CMOS inverter formed on a wafer, wherein each of the wafers on which the PMOS transistors and the NMOS transistors on which the gate electrode and its sidewalls are insulated is formed is formed. Forming a conductive film on the entire structure; Selectively etching the conductive film to form a conductive film pattern to interconnect the source region of the PMOS transistor and the NMOS transistor; Forming an interlayer insulating film on the entire structure; And a fourth step of forming a metal wiring penetrating the interlayer insulating film and connected to the conductive film pattern, the PMOS transistor, and the drain of the NMOS transistor.

A method of connecting a characteristic CMOS inverter provided from the present invention is also a method of connecting a CMOS inverter formed on a wafer, wherein the first interlayer insulating film is formed on the entire structure of the wafer on which the PMOS transistor and the NMOS transistor are formed. Forming a first step; Forming a conductive film pattern through the first interlayer insulating film to interconnect the source region of the PMOS transistor and the NMOS transistor; A third step of forming a second interlayer insulating film on the entire structure after performing the second step; And a metal wire penetrating the second interlayer insulating film to be connected to the conductive film pattern and penetrating the second interlayer insulating film and the first interlayer insulating film to be connected to a drain of the PMOS transistor and the NMOS transistor. It comprises a fourth step.

That is, the present invention does not connect the PMOS source and the NMOS source of the CMOS inverter in the peripheral circuit region by using the lower metal wiring in the two-layer metal wiring process, and the silicide film or other laminated metal in forming the bit line. After using the connection, the lower metal wiring and the upper metal wiring process to proceed to secure the process margin during the lower metal wiring process.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

First, FIG. 1 shows a conventional CMOS inverter circuit, in which an inverter is formed around the cell region of the wafer, that is, in the peripheral circuit region.

As shown in the figure, a CMOS inverter has a source of PMOS and NMOS interconnected between a supply power supply (Vcc) line and a ground power supply (Vss) line, and an output (VOUT) line is connected in common, and the gates of the transistors are mutually connected. Connected to the input (VIN) line in common.

2A through 2C illustrate a process of connecting a CMOS inverter according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, a conventional process is performed to form an N-well 201 and a P-well 202 on a wafer, and the field oxide film 203 and the gate oxide film 204 are sequentially formed. In this state, the source / drain regions 208, 208 ′, 209, and 209 ′ of the gate electrode 205 and the lightly doped drain (LDD) structure are formed. At this time, the top and sidewalls of the gate electrode 205 are covered with the insulating film 206 and the spacer insulating film 207, respectively.

Next, as shown in FIG. 2B, a silicide layer 210 is deposited on the entire wafer structure and patterned to form a source 208 ′ and a P-well 202 of the PMOS formed in the N-well 201. The source 209 'of the formed NMOS is connected. In this case, a conventional silicide bit line forming process is performed in the cell region. That is, although the interlayer insulating film is formed in the peripheral circuit region shown, it is not shown because it is removed during the photolithography and etching process for forming the contact hole in the cell region.

Subsequently, as shown in FIG. 2C, an interlayer insulating film 211 is formed over the entire structure and selectively etched to form a region of the drain 208 of the PMOS and the drain 209 of the NMOS and a predetermined portion of the silicide film 210. After forming a metal wiring contact hole exposing the metal film, a metal film is deposited on the entire structure and patterned to form a metal wiring 212. At this time, the lower metal wiring of the two-layer metal wiring is formed in the cell region, thereby completing the wiring process of the CMOS inverter.

Thereafter, the subsequent process is performed.

3A through 3C illustrate a wiring process of a CMOS inverter according to another exemplary embodiment of the present invention.

First, as shown in FIG. 3A, the N-well 301 and the P-well 302 are formed by performing a conventional process, and the field oxide film 303 and the gate oxide film 304 are sequentially formed. The gate electrode 305 is formed in FIG. Subsequently, a spacer insulating film 307 is formed on the sidewall of the gate electrode 305, and an interlayer insulating film 310 is formed on the entire structure. Reference numerals 308, 308 ', 309, and 309' denote source / drain regions of the LDD structure.

Next, as shown in FIG. 3B, the interlayer insulating film 310 is selectively etched to form contact holes for exposing the source 308 'of the PMOS and the source 309' of the NMOS, and forming Ti / over the entire structure. After the TiN / W laminated metal 311 is deposited and patterned, an interlayer insulating layer 312 is formed on the entire structure again.

Subsequently, as shown in FIG. 3C, the interlayer insulating layer 312 is selectively etched to form regions of the drain 308 of the PMOS and the drain 309 of the NMOS, and a predetermined portion of the patterned Ti / TiN / W stacked metal 311. After forming a contact hole for exposing the light, and then depositing a metal film on the entire structure and patterning it to form a metal wiring 313, and then to form an interlayer insulating film 314 and another contacted to the metal wiring 313 Metal wiring 315 is formed. At this time, a two-layer metallization process is performed in the cell region. That is, the metal wire 313 corresponds to the lower metal wire, and the metal wire 315 corresponds to the upper metal wire.

Thereafter, the subsequent process is performed.

In the above-described embodiments of the present invention, the conductive film for interconnecting the PMOS and the NMOS source is limited to a silicide film or a Ti / TiN / W laminated metal. However, the present invention is not intended to limit the present invention. Any conductive film that conforms to the technical idea of is not limited to its kind.

As described above, according to the present invention, the PMOS source and the NMOS source are connected to each other by using a separate conductive film before the lower metal wiring process instead of the bottom metal wiring during the double layer metal wiring process when forming the CMOS inverter of the peripheral circuit. In addition, when forming the lower metal wiring, there is an effect of increasing the process margin in the peripheral circuit area, thereby contributing to the high integration of the semiconductor device can be expected.

Claims (5)

A method for connecting a CMOS inverter formed on a wafer, comprising: a first step of forming a conductive film on an entire structure of a wafer on which a PMOS transistor and an NMOS transistor insulated from an upper side of each gate electrode and sidewalls thereof; Selectively etching the conductive film to form a conductive film pattern to interconnect the source region of the PMOS transistor and the NMOS transistor; Forming an interlayer insulating film on the entire structure; And forming a metal wiring connected to the conductive film pattern, the drain of the PMOS transistor, and the NMOS transistor through the interlayer insulating film. The method of claim 1, wherein in the second step, a bit line is formed in a cell region on the wafer. The method for wiring a CMOS inverter according to claim 1 or 2, wherein the conductive film is a silicide film. A method of connecting a CMOS inverter formed on a wafer, comprising: a first step of forming a first interlayer insulating film on an entire structure of the wafer on which a PMOS transistor and an NMOS transistor are formed; Forming a conductive film pattern through the first interlayer insulating film to interconnect the source region of the PMOS transistor and the NMOS transistor; A third step of forming a second interlayer insulating film on the entire structure after performing the second step; And a metal wire penetrating the second interlayer insulating film to be connected to the conductive film pattern and penetrating the second interlayer insulating film and the first interlayer insulating film to be connected to a drain of the PMOS transistor and the NMOS transistor. Wiring method of the CMOS inverter comprising a fourth step. The method according to claim 4, wherein the conductive film pattern is made of a titanium film, a titanium nitride film, and a tungsten film, which are sequentially stacked.