KR0131741B1 - Semiconductor memory device and manufacturing method thereof - Google Patents
Semiconductor memory device and manufacturing method thereofInfo
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- KR0131741B1 KR0131741B1 KR1019930031837A KR930031837A KR0131741B1 KR 0131741 B1 KR0131741 B1 KR 0131741B1 KR 1019930031837 A KR1019930031837 A KR 1019930031837A KR 930031837 A KR930031837 A KR 930031837A KR 0131741 B1 KR0131741 B1 KR 0131741B1
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- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title description 5
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 125000006850 spacer group Chemical group 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims 3
- 239000012212 insulator Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
제1도는 일반적인 반도체 장치의 집적회로에서 가장 널리 사용되는 인버터(inverter)의 회로도.1 is a circuit diagram of an inverter most widely used in an integrated circuit of a general semiconductor device.
제2도는 종래기술에 따른 제1도의 회로를 종래 방법에 의해 반도체 기판에 형성한 단면도.2 is a cross-sectional view of the circuit of FIG. 1 according to the prior art formed on a semiconductor substrate by a conventional method.
제3a도 내지 제3d도는 본 발명에 따른 제1도의 회로를 본 발명의 반도체 기판에 형성한 단면도.3A to 3D are sectional views in which the circuit of FIG. 1 according to the present invention is formed on a semiconductor substrate of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 소자분리 절연막1 semiconductor substrate 2 device isolation insulating film
3 : 게이트 산화막 4 : 게이트전극3: gate oxide film 4: gate electrode
6 : 층간절연막 10 : N-웰6 interlayer insulating film 10 N-well
15A : P+소오스전극 15B : P+그레인전극15A: P + source electrode 15B: P + grain electrode
15C : N+기판전극 20 : P- 웰15C: N + substrate electrode 20: P-well
25A : N+소오스전극 25B : N+드레인전극25A: N + source electrode 25B: N + drain electrode
25C : P+기판전극 30A : LDD용 스페이서25C: P + substrate electrode 30A: LDD spacer
30B : 기판전극 형성용 스페이서 31 : 제1감광막패턴30B: spacer for forming substrate electrode 31: first photosensitive film pattern
32 : 제2 감광막패턴 35A, 35B, 35C : 연결선32: second photosensitive film pattern 35A, 35B, 35C: connection line
본 발명은 반도체 기억장치 및 그 제조방법에 관한 것으로, 특히 모스펫 소자의소오스전극과 기판전극을 접속시키는 부분의 면적을 감소시키기 위하여 소오스전극이 형성되는 동일한 활성영역(active region)게이트전극 측벽의 스페이서에 의한 자기정렬방식을 이용하여 소오스전극과 기판전극을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to spacers of sidewalls of the same active region gate electrode on which source electrodes are formed in order to reduce the area of a portion connecting the source electrode and the substrate electrode of the MOSFET device. It relates to a method of forming a source electrode and a substrate electrode by using a self-aligned method.
일반적으로 반도체 장치의 고집적화에 따라 반도체 장치를 구성하는 각각의 소자들의 크기가 감소되어야 한다. 반도체 장치의 집적회로를 구성하는 소자중 가장 많은 부분을 차지하는 모스펫 구조는 집적회로내에서 소오스 전극과 기판전극이 서로 연결된 형태로 이루어지고 있다.In general, as the integration of semiconductor devices increases, the size of each element constituting the semiconductor device should be reduced. The MOSFET structure, which occupies the most part of the devices constituting the integrated circuit of the semiconductor device, is formed in such a manner that the source electrode and the substrate electrode are connected to each other in the integrated circuit.
제1도는 일반적인 반도체 장치의 집적회로에서 가장 널리 사용되는 인버트(inverter)의 회로도이다.1 is a circuit diagram of an inverter which is most widely used in an integrated circuit of a general semiconductor device.
제1도에 도시된 바와같이, VDD가 PMOS의 소오스전극에 연결되고, PMOS의 드레인전극이 NMOS의 드레인전극에 연결되어 있다.As shown in FIG. 1, VDD is connected to the source electrode of the PMOS, and the drain electrode of the PMOS is connected to the drain electrode of the NMOS.
또한, NMOS의 소오스전극이 VSS에 연결되고, PMOS의 소오스전극은 PMOS의 기판전극과 연결되어 있다. 그리고, NMOS의 소오스전극은 NMOS의 기판전극에 연결되고, 상기 PMOS와 NMOS의 게이트전극이 서로 연결된 부분이 입력단자가 되며, PMOS의 드레인전극과 NMOS의 드레인전극이 서로 연결된 부분이 출력단자가 되어 입력단자와 출력단자가 서로 반전된다.In addition, the source electrode of the NMOS is connected to the VSS, and the source electrode of the PMOS is connected to the substrate electrode of the PMOS. The source electrode of the NMOS is connected to the substrate electrode of the NMOS, and the portion where the PMOS and the gate electrode of the NMOS are connected to each other is an input terminal, and the portion where the drain electrode of the PMOS is connected to the drain electrode of the NMOS is an output terminal. The terminals and output terminals are inverted each other.
이와 관련하여, 종래 기술에 따른 종래의 방법에 의해 형성된 모스펫 소자를 제2도를 참조하여 설명하면 다음과 같다. 제2도는 종래 기술에 따른 제1도의 반도체소자의 회로를 종래의 방법에 적용하여 형성된 모스펫 소자의 단면도이다. 제2도에 도시된 바와 같이, 공지의 기술에 의해 반도체 기판(1) 상부에 N-웰(well)(10) 및 P-웰(well)(20)을 각각 형성한다.In this regard, the MOSFET device formed by the conventional method according to the prior art will be described with reference to FIG. 2 is a cross-sectional view of a MOSFET device formed by applying the circuit of the semiconductor device of FIG. 1 according to the prior art to a conventional method. As shown in FIG. 2, N-wells 10 and P-wells 20 are formed on the semiconductor substrate 1 by known techniques, respectively.
이어서, 소자분리 절연막(2), 게이트전극(4), 소오스/드레인전극(15A)(15B)(25A)(25B)을 순차적으로 형성한다음, 층간절연막(6)과 연결선 (35A)(35B)(35C)을 형성한다.Subsequently, the device isolation insulating film 2, the gate electrode 4, and the source / drain electrodes 15A, 15B, 25A, and 25B are sequentially formed, and the interlayer insulating film 6 and the connection line 35A and 35B are sequentially formed. (35C).
그 다음, 모스펫 소자의 소오스전극(15A)(25A)과 기판전극(15C)(25C)을 연결하기 위하여 소오스전극(15A)(25A)이 형성되는 활성영역과 이웃한 별도의 활성영역에 기판과 동일한 타입(type)의 불순물을 이온주입하여 기판전극(15C)(25C)을 형성하므로써 소오스전극(15A)(25A)과 연결시킨다.Subsequently, the substrate is connected to a separate active region adjacent to an active region where the source electrodes 15A and 25A are formed to connect the source electrodes 15A and 25A and the substrate electrodes 15C and 25C of the MOSFET device. The same type of impurities are implanted into the ions to form the substrate electrodes 15C and 25C so as to be connected to the source electrodes 15A and 25A.
상기한 바와같이, 상기 종래 방법에 있어서는 소오스전극 형성용 마스크와 기판전극 형성용 마스크, 그리고 게이트전극 마스크사이의 레티클 레지스트레이션(reticle registration) 및 마스크 작업시의 오정렬, CD변화 등을 고려하면 소오스전극이 형성되는 활성영역의 크기를 줄일 수 없는 문제점이 발생한다.As described above, in the conventional method, in consideration of reticle registration between the source electrode forming mask, the substrate electrode forming mask, and the gate electrode mask, misalignment during mask operation, CD change, and the like, There is a problem that can not reduce the size of the active region formed.
이에, 본 발명은 모스펫 소자의 소오스전극이 형성되는 동일한 활성영역에 자기정렬방식을 이용하여 소오스전극과 기판전극을 형성함으로써 소오스전극이 형성되는 활성영역의 크기를 최소화할 수 있는 반도체기억장치 및 그 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a semiconductor memory device capable of minimizing the size of the active region in which the source electrode is formed by forming the source electrode and the substrate electrode in the same active region in which the source electrode of the MOSFET is formed by using a self-aligning method. The purpose is to provide a manufacturing method.
상기 목적을 달성하기 위한 본 발명에 따른 반도체기억장치는, 반도체 기판의 한 영역에 형성된 소자분리절연막과 활성영역 및 상기 활성영역상에 형성된 게이트영역과, 상기 활성영역의 일부분을 차단시키도록 상기 게이트영역의 측벽에 형성된 절연막 스페이서와, 상기 반도체기판의 노출된 활성영역의 표면상에 형성된 소오스 및 드레인 영역과, 상기 절연막스페이서와 게이트영역 및 드레인영역을 제외한 상기 소오스영역의 노출된 영역내에 형성되고 상기 소오스영역과 접속되는 기판전극을 포함하여 구성됨을 그 특징으로한다.In accordance with another aspect of the present invention, a semiconductor memory device includes a device isolation insulating film and an active region formed in one region of a semiconductor substrate, a gate region formed on the active region, and a portion of the gate to block a portion of the active region. An insulating film spacer formed on a sidewall of the region, a source and drain region formed on a surface of an exposed active region of the semiconductor substrate, and formed in an exposed region of the source region except for the insulating layer spacer, a gate region and a drain region; And a substrate electrode connected to the source region.
또한, 본 발명에 따른 반도체기억장치는, 반도체 기판의 한 영역에 형성된 소자분리절연막과 활성영역 및 게이트영역과, 상기 게이트영역의 측벽에 형성된 제1절연막 스페이서와, 상기 제1절연막스페이서상에 형성된 제2절연막스페이서와, 상기 활성영역의 노출된 표면상에 형성된 소오스 및 드레인영역과, 상기 제2 절연막스페이서와 소자분리절연막사이에 있는 상기 소오스영역의 노출된 영역내에 형성되고 상기 소오스영역과 접속되는 기판전극을 포함하여 구성됨을 그 특징으로 한다.In addition, the semiconductor memory device according to the present invention includes a device isolation insulating film, an active region and a gate region formed in one region of a semiconductor substrate, a first insulating layer spacer formed on sidewalls of the gate region, and a first insulating layer spacer formed on the first insulating layer spacer. A second insulating film spacer, a source and a drain region formed on an exposed surface of the active region, and formed in an exposed region of the source region between the second insulating film spacer and the device isolation insulating film and connected to the source region. It is characterized by including a substrate electrode.
그리고, 본 발명에 따른 반도체기억장치의 제조방법은 반도체 기판의 한 영역에 소자분리절연막과 활성영역 및 게이트영역을 형성하는 공정과, 상기 게이트영역의 측벽에 제1절연막 스페이서를 형성하는 공정과, 상기 제1절연막스페이서상에 제2절연막스페이서를 형성하는 공정과, 상기 활성영역의 노출된 표면상에 소오스 및 드레인 영역을 형성하는 공정과, 상기 드레인영역을 포함한 게이트영역의 일측면에 있는 노출된 구조상에 감광막패턴을 형성하는 공정과, 상기 제2절연막스페이서와 소자분리절연막 및 감광막패턴을 마스크로한 자기정렬방식에 의해 상기 소오스영역의 노출된 영역내에 상기 소오스영역의 도전성타입과 반대되는 타입의 불순물을 이온주입하여 기판전극을 형성하는 공정을 포하하여 이루어짐을 그 특징으로 한다.The method of manufacturing a semiconductor memory device according to the present invention comprises the steps of forming a device isolation insulating film, an active region and a gate region in one region of the semiconductor substrate, forming a first insulating layer spacer on the sidewall of the gate region; Forming a second insulating film spacer on the first insulating film spacer, forming a source and a drain region on an exposed surface of the active region, and exposing at one side of the gate region including the drain region. A process of forming a photoresist pattern on the structure and a self-aligning method using the second insulating film spacer, the device isolation insulating film, and the photoresist pattern as a mask, in a type opposite to the conductivity type of the source region in the exposed region of the source region. It is characterized by comprising a step of forming a substrate electrode by implanting impurities into the ion.
이하, 본 발명에 따른 반도체소자의 기억장치 및 그 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a memory device and a manufacturing method thereof of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제3a도 내지 제3d도는 제1도의 회로를 본 발명에 의해 반도체 기판에 형성한 단면도이다.3A to 3D are sectional views in which the circuit of FIG. 1 is formed on a semiconductor substrate according to the present invention.
제3a도에 도시된 바와같이, N-웰(10)과 P-웰(20)내의 일정부분에 소자분리 절연막(2)을 형성하고, 게이트전극(4)과 LDD용 스페이서(30A), 그리고 N-웰(10)에 P+소오스/드레인전극(15A)(15B), P-웰(20)에 N+소오스/드레인전극(25A)(25B)을 형성한다.As shown in FIG. 3A, a device isolation insulating film 2 is formed in a portion of the N-well 10 and the P-well 20, the gate electrode 4, the LDD spacer 30A, and P + source / drain electrodes 15A and 15B are formed in the N-well 10 and N + source / drain electrodes 25A and 25B are formed in the P-well 20.
이어서, 상기 LDD용 스페이서(30A)는 목적에 따라 형성하거나, 형성하지 않을 수도 있다. 그다음, 제3b도에 도시된 바와같이, 게이트전극(4) 측벽에 폭이 큰 기판전극형성용 스페이서(30B)를 형성한다. 이어서, 상기 전체구조의 노출된 표면상에 제1감광막을 도포하고, 상기 제1감광막을 PMOS 트랜지스터의 상기 소오스전극의 일부분만이 노출되도록 선택적으로 제거하여 N+기판전극 마스크용 제1 감광막패턴(31)을 형성한다.Subsequently, the LDD spacer 30A may or may not be formed depending on the purpose. Then, as shown in FIG. 3B, a wide substrate electrode formation spacer 30B is formed on the sidewall of the gate electrode 4. Subsequently, a first photoresist film is coated on the exposed surface of the entire structure, and the first photoresist film is selectively removed so that only a part of the source electrode of the PMOS transistor is exposed to thereby expose the first photoresist pattern for N + substrate electrode mask. 31).
그다음, 상기 N+기판전극 마스크용 제1감광막패턴(31)을 마스크로하여 상기 P+소오스전극(15A)의 노출된 일부분에 N형 불순물을 이온주입하여 N+기판전극(15C) 형성한다. 이때, 상기 제1감광막패턴(31)은 상기 PMOS의 소오스전극(15A)의 예정된 위치에 형성되지 않고 게이트전극(4) 에 겹쳐지도록 형성되지만, 상기 N형 불순물들은 폭이 큰 상기 기판전극형성용 스페이서(30B) 때문에 상기 소오스전극(15A)의 전체면적안으로 이온주입되는 것이 방지된다.Then, to form N + substrate electrode (15C) by implanting N-type impurity in the exposed portion of the N + substrate electrode a first photoresist pattern 31 is the P + source electrode (15A) as a mask to for the mask. In this case, the first photoresist layer pattern 31 is formed to overlap the gate electrode 4 without being formed at a predetermined position of the source electrode 15A of the PMOS, but the N-type impurities are formed for the substrate electrode having a large width. Because of the spacer 30B, ion implantation is prevented into the entire area of the source electrode 15A.
즉,상기 이온주입되는 불순물들은 상기 게이트전극(4)과 상기 기판 전극형성용 스페이서(30B)에 자기정렬되어 N+기판전극(15C)을 형성한다.That is, the impurities are ion-aligned to the gate electrode 4 and the substrate electrode forming spacer 30B to form N + substrate electrode 15C.
이어서, 제3c도에 도시된 바와같이, 상기 제1감광막패턴(31)을 제거하고, 상기 전체구조의 노출된 표면상에 제2감광막을 도포하고, 상기 제2감광막을 NMOS 트랜지스터의 상기 소오스전극의 일부분만이 노출되도록 선택적으로 제거하여 P+기판전극 마스크용 제2 감광막패턴(32)를 형성한다.Subsequently, as shown in FIG. 3C, the first photoresist layer pattern 31 is removed, a second photoresist layer is applied on the exposed surface of the entire structure, and the second photoresist layer is formed on the source electrode of the NMOS transistor. The second photoresist pattern 32 for the P + substrate electrode mask is selectively formed to selectively expose only a portion of the portion of the P + substrate electrode mask.
그다음, 상기 P+기판전극 마스크용 제2감광막패턴(32)을 마스크로하여 상기 N+ 소오스전극(25 A)의 노출된 일부분에 P형 불순물을 이온주입하여 P+기판전극(25C)을 형성한다.Then, to form an ion implanted P + substrate electrode (25C), the P-type impurity in the exposed portion of the P + substrate electrode, the second photoresist pattern 32 to the N + source electrode (25 A) as a mask for mask .
이때, 상기 제2감광막패턴(32)은 상기 NMOS의 소오스전극(25A)의 예정된 위치에 형성되지 않고 게이트전극(4)상에 겹쳐지도록 형성되지만, 상기 P형 불순물들은 폭이 큰 상기 기판전극형성용 스페이서(30B) 때문에 상기 소오스전극(25A)의 전체면적안으로 이온주입되는 것이 방지된다.In this case, the second photoresist layer pattern 32 is formed to overlap the gate electrode 4 without being formed at a predetermined position of the source electrode 25A of the NMOS, but the P-type impurities are formed in the substrate electrode having a large width. Due to the spacer 30B, ion implantation is prevented into the entire area of the source electrode 25A.
즉, 상기 이용주입되는 P형 불순물들은 상기 게이트전극(4)과 상기 기판전극형성용 스페이서(30B)에 자기정렬되어 P+기판전극(15C)을 형성한다.That is, the P-type impurities to be used are self-aligned to the gate electrode 4 and the substrate electrode forming spacer 30B to form the P + substrate electrode 15C.
이어서, 제3d도에 도시된 바와같이, 상기 전체구조상에 층간절연막(6)을 형성하고 상기 층간절연막을 선택적으로 제거하여 상기 소오스/드레인전극(15A)(25A)(15B)(25B)과 기판전극(15C)(25C) 상부를 노출시키는 콘택(미도시)을 형성한다. 이때, 상기 콘택형성시에 소오스전극(15A)(25A)과 기판전극(15C)(25C)이 동시에 노출되도록 한다.Subsequently, as shown in FIG. 3D, an interlayer insulating film 6 is formed on the entire structure, and the interlayer insulating film is selectively removed so that the source / drain electrodes 15A, 25A, 15B, 25B and the substrate are removed. A contact (not shown) for exposing the upper portions of the electrodes 15C and 25C is formed. At this time, the source electrodes 15A and 25A and the substrate electrodes 15C and 25C are simultaneously exposed when forming the contact.
그 다음, 상기 콘택을 통해 상기 노출된 층간절연막(6)상에 도전층을 형성하고 이를 선택적으로 패터닝하여 상호 연결선(35A)(35B)(35C)을 형성한다.Next, a conductive layer is formed on the exposed interlayer insulating film 6 through the contact and then selectively patterned to form interconnect lines 35A, 35B, and 35C.
상기한 바와 같이, 본 발명에 의하면 모스펫 소자의 소오스전극이 형성되는 동일한 활성영역에 게이트 전극측벽의 스페이서에 의한 자기정렬방식을 이용하여 소오스전극과 기판전극을 형성함으로써 소오스전극이 형성되는 활성영역의 크기를 최소화할 수 있다.As described above, according to the present invention, the source electrode and the substrate electrode are formed in the same active region where the source electrode of the MOSFET is formed by using a self-aligning method by spacers on the side wall of the gate electrode. The size can be minimized.
Claims (5)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930031837A KR0131741B1 (en) | 1993-12-31 | 1993-12-31 | Semiconductor memory device and manufacturing method thereof |
| DE4447255A DE4447255C2 (en) | 1993-12-31 | 1994-12-30 | Method for manufacturing a field effect semiconductor device with a substrate electrode |
| JP7000038A JPH07211785A (en) | 1993-12-31 | 1995-01-04 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930031837A KR0131741B1 (en) | 1993-12-31 | 1993-12-31 | Semiconductor memory device and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| KR950021499A KR950021499A (en) | 1995-07-26 |
| KR0131741B1 true KR0131741B1 (en) | 1998-04-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930031837A KR0131741B1 (en) | 1993-12-31 | 1993-12-31 | Semiconductor memory device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JPH07211785A (en) |
| KR (1) | KR0131741B1 (en) |
| DE (1) | DE4447255C2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3821781A (en) * | 1972-11-01 | 1974-06-28 | Ibm | Complementary field effect transistors having p doped silicon gates |
| JPS6235666A (en) * | 1985-08-09 | 1987-02-16 | Nissan Motor Co Ltd | Mos transistor |
| JPS63133564A (en) * | 1986-11-25 | 1988-06-06 | Nec Corp | Manufacture of semiconductor integrated circuit |
| JPH0521736A (en) * | 1991-07-12 | 1993-01-29 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
-
1993
- 1993-12-31 KR KR1019930031837A patent/KR0131741B1/en not_active IP Right Cessation
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1994
- 1994-12-30 DE DE4447255A patent/DE4447255C2/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| DE4447255C2 (en) | 1997-09-11 |
| DE4447255A1 (en) | 1995-07-06 |
| JPH07211785A (en) | 1995-08-11 |
| KR950021499A (en) | 1995-07-26 |
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