KR100252855B1 - Dram and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A DRAM and a fabrication method thereof are provided to improve reliability, yield and the degree of integration by forming a capacitor on the transistor vertically. CONSTITUTION: The DRAM includes a plurality of thin film transistors formed on a semiconductor substrate(31), each transistor having the first and second impurity regions(33,39). The first insulating layer(41) is formed over entire surfaces and has the first contact holes each exposing the first impurity region(33) between the transistors. A plurality of bit lines(42) are formed in the first contact holes and electrically connected to the first impurity regions(33). The second insulating layer(43) is formed over the first insulating layer(41) and has the second contact holes each exposing the second impurity region(39). A plurality of capacitors, each having a storage node electrode(44), a dielectric layer(45) and a plate electrode(46), are formed in the second contact holes and over the second insulating layer(43), and electrically connected to the second impurity regions(39).

Description

DRAM and its manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM and a method of manufacturing the same, and more particularly, to a DRAM and a method of manufacturing the same, which improve the reliability, yield, and integration of a device.

In general, a DRAM cell includes one bit line, one word line, one access transistor, and one storage capacitor. The structure of the DRAM cell includes a gate of the access transistor. The drain of the access transistor is connected to one word line and has a so-called horizontal structure connected to the bit line.

In order to increase the integration of DRAM devices, many types of cell arrays and structures thereof have been proposed.

In the DRAM manufacturing method according to the related art, as shown in FIG. 1A, the field oxide film 12 is formed by a general LOCOS process on the semiconductor substrate 11 in the isolation region.

Then, a gate oxide film 13, a first polycrystalline silicon, a first oxide film, and a first photosensitive film are sequentially formed on the semiconductor substrate 11, and then the first photosensitive film is selectively exposed so that only a portion where a gate electrode is to be formed remains. And develop.

Subsequently, the first oxide film, the first polycrystalline silicon, and the gate oxide film 13 are selectively etched using the selectively exposed and developed first photoresist film as a mask to form a plurality of gate electrodes 14 and a cap gate oxide film 15. Are formed and the first photoresist film is removed.

In addition, the low concentration n-type impurity ions are implanted into the semiconductor substrate 11 using the cap gate oxide layers 15 as a mask, and then drive-in diffusion to drive both sides of the gate electrode 14. Lightly Doped Drain (LDD) regions 16 are formed in the surface of the semiconductor substrate 11.

As shown in FIG. 1B, a second oxide film is formed on the entire surface including the gate electrode 14 and the cap gate oxide film 15, and is etched back to form the second gate electrode 14 and the cap gate oxide film 15. The second oxide film sidewalls 17 are formed on both sides of the.

The high concentration n-type impurity ions are implanted into the semiconductor substrate 11 using the cap gate oxide film 15 and the second oxide film sidewall 17 as a mask, and then drive-in diffusion to form the second oxide film sidewall ( The source / drain impurity region 18 is formed in the surface of the semiconductor substrate 11 on both sides of the gate electrode 14 including 17.

As shown in FIG. 1C, after the third oxide film 19 and the second photoresist film are sequentially formed on the entire surface, the second photoresist film is selectively exposed and developed so as to be removed only at the portion where the storage node contact is to be formed.

The third oxide film 19 is selectively etched using the selectively exposed and developed second photosensitive film as a mask to form a first contact hole, and the second photosensitive film is removed.

As shown in FIG. 1D, a second polycrystalline silicon and a third photoresist film are sequentially formed on the third oxide film 19 including the first contact hole, and then the third photoresist film is selectively left so as to remain only at a portion where the storage node electrode is to be formed. Exposure and development.

The second polycrystalline silicon is selectively etched using the selectively exposed and developed third photoresist layer to form a storage node electrode 20, and then the third photoresist layer is removed.

Subsequently, a dielectric film 21 is formed on the surface of the storage node electrode 20, and a third polycrystalline silicon and a fourth photoresist film are sequentially formed on the entire surface including the dielectric film 21.

The fourth photosensitive film is selectively exposed and developed so that only the portion where the plate electrode is to be formed remains.

Subsequently, the third polycrystalline silicon is selectively etched using the selectively exposed and developed fourth photoresist film to form a plate electrode 22, and then the fourth photoresist film is removed.

Here, a capacitor is formed of the storage node 20, the dielectric layer 21, and the plate electrode 22.

As shown in FIG. 1E, the fourth oxide film 23 and the fifth photoresist film are sequentially formed on the third oxide film 19 including the capacitor, and then the fifth photoresist film is selectively removed so that only the portion where the bit line contact is to be formed is removed. Exposure and development.

The fourth oxide film 23 and the third oxide film 19 are selectively etched using the fifth exposed and developed photosensitive film as a mask to form a second contact hole, and the fifth photosensitive film is removed.

As shown in FIG. 1F, the bit line metal layer 24 is formed on the fourth oxide layer 23 including the second contact hole.

However, the conventional DRAM and its manufacturing method had the following problems.

First, since the storage node electrode of the capacitor is in contact with the semiconductor substrate, a leakage current is generated in the semiconductor substrate to reduce the reliability of the device.

Second, because of the horizontal structure, the integration of the device is lowered and the active area is reduced by the field oxide film formed by the LOCOS process, so that there is no etching margin such as contact, so the yield is lowered.

Disclosure of Invention The present invention has been made to solve the above problems, and therefore has a vertical structure by forming a capacitor on a thin film transistor, and therefore has an object to provide a DRAM and a method of manufacturing the same, which improves the reliability, yield and integration of the device.

1A to 1F are cross-sectional views illustrating a method of manufacturing a DRAM according to the prior art.

2 is a structural cross-sectional view showing a DRAM according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a thin film transistor of a DRAM according to an embodiment of the present invention.

4A to 4I are cross-sectional views illustrating a method of manufacturing a DRAM according to an embodiment of the present invention.

Explanation of symbols for main parts of the drawings

31 semiconductor substrate 32 first oxide film

33: first polycrystalline silicon 34: gate oxide film

35 gate electrode 36 cap gate oxide film

37: third oxide film sidewall 38: second photosensitive film

39: third polycrystalline silicon 40: third photosensitive film

41: fourth oxide film 42: bit line

43: fifth oxide film 44: storage node electrode

45 dielectric film 46 plate electrode

The DRAM of the present invention includes an insulating substrate, a plurality of thin film transistors having first and second impurity regions formed on the insulating substrate, and a first contact hole on the first impurity region of each thin film transistor. A first insulating film to be formed, a plurality of bit lines formed in the first contact hole and electrically connected to the first impurity region of each thin film transistor, and a second contact hole on the second impurity region of each thin film transistor A plurality of capacitors having a second insulating film formed on the first insulating film including the bit lines, and a second insulating film formed on the second insulating film including the second contact hole and electrically connected to the second impurity regions of the thin film transistors. Characterized in that it comprises a.

In addition, the method of manufacturing a DRAM of the present invention may include forming a plurality of thin film transistors having first and second impurity regions on an insulating substrate, and forming a first insulating film on an insulating substrate including the plurality of thin film transistors. Etching the first insulating layer to form a first contact hole on the first impurity region of each of the thin film transistors, and forming a plurality of bit lines electrically connected to the first impurity region of each of the thin film transistors. Forming in the contact hole, forming a second insulating film on the first insulating film including the bit lines, and forming the second contact hole on the second impurity region of each thin film transistor. And etching a plurality of capacitors electrically connected to the second impurity regions of the thin film transistors. And forming on the second insulating film including the second contact hole.

When described in detail with reference to the accompanying drawings, a preferred embodiment of the DRAM and its manufacturing method according to the present invention as follows.

2 is a cross-sectional view showing a DRAM according to an embodiment of the present invention, Figure 3 is a cross-sectional view showing a thin film transistor of the DRAM according to an embodiment of the present invention, Figures 4a to 4i according to an embodiment of the present invention It is process sectional drawing which shows the manufacturing method of a DRAM.

As shown in FIG. 2, a DRAM according to an embodiment of the present invention includes a plurality of first oxide films 32 formed on a semiconductor substrate 31 and a plurality of source / drain impurity regions formed on the first oxide films 32. Thin film transistors, a fourth oxide film 41 having a first contact hole on the drain region of each thin film transistor, and formed on the front surface thereof, and formed in the first contact hole to be electrically connected to the drain region of each thin film transistor. A plurality of bit lines 42, a fifth oxide layer 43 having a second contact hole on the source region of each thin film transistor and formed on the fourth oxide layer 41 including the bit lines 42. And a plurality of storage node electrodes 44, dielectric layers 45, and plate electrodes 46 formed on the fifth oxide layer 43 including the second contact hole, and electrically connected to the source regions of the respective thin film transistors. Dog It is composed of L-seater.

As shown in FIG. 3, a thin film transistor of a DRAM according to an exemplary embodiment of the present invention includes a p-type channel region and an offset set region and an n-type source / drain impurity region, that is, a gate electrode and a first electrode of the gate electrode. And a drain region formed under the side and a source region formed over the gate electrode and the second side.

In the method of manufacturing a DRAM according to an exemplary embodiment of the present invention, as shown in FIG. 4A, the first oxide film 32 and the first polycrystalline silicon 33 are sequentially formed on the semiconductor substrate 31.

Then, p-type impurity ions are implanted into the first polycrystalline silicon 33.

As shown in FIG. 4B, the gate oxide layer 34 is grown on the first polycrystalline silicon 33 by a thermal oxidation process.

A second polycrystalline silicon, a second oxide film, and a first photosensitive film are sequentially formed on the gate oxide film 34, and the first photosensitive film is selectively exposed and developed so that only the portion where the gate electrode is to be formed remains.

Subsequently, the second oxide film, the second polycrystalline silicon, and the gate oxide film 34 are selectively etched using the selectively exposed and developed first photoresist film as a mask to form a plurality of gate electrodes 35 and a cap gate oxide film 36. After forming the film, the first photosensitive film is removed.

A third oxide film is formed over the entire surface, and the third oxide film is etched back to form a third oxide film sidewall 37 on the semiconductor substrate 31 on both sides of the gate electrode 35 and the cap gate oxide film 36. Form.

As shown in FIG. 4C, a second photosensitive film 38 is coated on the entire surface including the third oxide film sidewall 37, and the second photosensitive film 38 is selectively exposed and developed so that only the portion where the drain region is to be formed remains. do.

Then, the first polycrystalline silicon 33 is selectively etched using the selectively exposed and developed second photosensitive film 38 as a mask.

Here, the drain region is formed by the selective etching of the first polycrystalline silicon 33 and is isolated between the transistors.

As shown in FIG. 4D, the second photosensitive film 38 is removed, a third polycrystalline silicon 39 is formed on the entire surface, and then n-type impurity ions are implanted.

Here, the drain region is changed from the p-type impurity region to the n-type impurity region because the n-type impurity ions are implanted into the third polycrystalline silicon 39.

As shown in FIG. 4E, a third photosensitive film 40 is coated on the third polycrystalline silicon 39, and the third photosensitive film 40 is selectively exposed and developed so as to remain only at a portion where a source region is to be formed.

The third polycrystalline silicon 39 is selectively etched using the selectively exposed and developed third photosensitive film 40 as a mask.

Here, a plurality of thin film transistors including a p-type channel region, an offset region, and an n-type source / drain impurity region are formed by selective etching of the third polycrystalline silicon 39.

As shown in FIG. 4F, the third photoresist film 40 is removed, and a fourth oxide film 41 and a fourth photoresist film are sequentially formed on the entire surface including the thin film transistors.

After selectively exposing and developing the fourth photoresist layer so as to be removed only at a portion where a bit line contact is to be formed, the fourth oxide layer 41 is selectively etched using the selectively exposed and developed fourth photoresist layer as a mask. A first contact hole is formed and the fourth photoresist film is removed.

Subsequently, after forming a metal layer on the fourth oxide layer 41 including the first contact hole, the metal layer is etched back to form a bit line 42 in the first contact hole.

As shown in FIG. 4G, a fifth oxide layer 43 and a fifth photoresist layer are sequentially formed on the fourth oxide layer 41 including the bit line 42, and then the fifth photoresist layer is formed at the storage node contact. Selectively exposed and developed so as to be removed only.

The fifth oxide film 43 and the fourth oxide film 41 are selectively etched using the fifth exposed and developed photosensitive film as a mask to form a second contact hole, and the fifth photosensitive film is removed.

As shown in FIG. 4H, a fourth polycrystalline silicon and a sixth photoresist layer are sequentially formed on the fifth oxide layer 43 including the second contact hole, and the sixth photoresist layer is selectively left so as to remain only at a portion where the storage node electrode is to be formed. Exposure and development.

The fourth polycrystalline silicon is selectively etched using the selectively exposed and developed sixth photoresist layer to form a plurality of storage node electrodes 44 on the fifth oxide layer 43 including the second contact hole. Then, the sixth photosensitive film is removed.

As shown in FIG. 4I, a dielectric film 45 is formed on a surface of the storage node electrodes 44, and then a fifth polycrystal for plate electrode 46 is formed on a fifth oxide film 43 including the dielectric film 45. To form silicon.

The DRAM of the present invention and a method of manufacturing the same have a vertical structure by forming a thin film transistor as an access transistor and forming a capacitor on the thin film transistor, thereby preventing the occurrence of leakage current by the junction of the storage node electrode and the semiconductor substrate of the capacitor. There is an effect of improving the reliability, yield and integration of the device by not performing a LOCOS process for preventing and forming a field oxide film.

Claims (4)

Insulating substrate; A plurality of thin film transistors having first and second impurity regions formed on the insulating substrate; A first insulating film having a first contact hole on the first impurity region of each of the thin film transistors and formed on an entire surface thereof; A plurality of bit lines formed in the first contact hole and electrically connected to first impurity regions of the thin film transistors; A second insulating film having a second contact hole on the second impurity region of each thin film transistor and formed on the first insulating film including the bit lines; And a plurality of capacitors formed on a second insulating film including the second contact hole and electrically connected to second impurity regions of the thin film transistors. The method of claim 1, And the thin film transistor includes a gate electrode, a first impurity region formed below the first side of the gate electrode, and a second impurity region formed above and second to the gate electrode. Forming a plurality of thin film transistors having first and second impurity regions on an insulating substrate; Forming a first insulating film on an insulating substrate including the plurality of thin film transistors; Etching the first insulating layer to form a first contact hole on the first impurity region of each of the thin film transistors; Forming a plurality of bit lines in the first contact hole, the plurality of bit lines electrically connected to first impurity regions of the thin film transistors; Forming a second insulating film on the first insulating film including the bit lines; Etching the first and second insulating layers to form second contact holes on second impurity regions of each of the thin film transistors; And forming a plurality of capacitors electrically connected to the second impurity regions of each of the thin film transistors on the second insulating film including the second contact hole. The method of claim 3, wherein Forming a first conductor on the insulating substrate and implanting first conductivity type impurity ions in the process of forming the thin film transistor; Forming a plurality of gate electrodes on the first conductor; Selectively etching the first conductor so that only the region where the drain region is to be formed remains; Forming a second conductor on the entire surface including the drain region and the gate electrodes and implanting second conductivity type impurity ions; And selectively etching the second conductor so as to remain only at a portion where a source region is to be formed.

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