JP3376284B2 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a DRAM portion including a memory cell array and peripheral circuits and a logic portion such as a CPU and a conversion circuit are mounted together, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a large capacity DRAM section and a CP
Since the manufacturing process is individually established for the U and the logic part such as the conversion circuit, it is often manufactured as separate chips and systemized by using a plurality of chips after manufacturing. However, in recent years, in order to improve performance and reduce cost, DRA, which has conventionally manufactured chips separately,
There has been an increasing demand for systematization by combining the M section and the logic section on a single chip.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
If the M section and the logic section are mixed as they are, there are many steps that are incompatible with each other because they have their own specific processes. For example, the conventional general-purpose DRAM does not use the step of siliciding the polysilicon layer, but there is a difference that it is common to use the silicidation step recently in the logic portion. Therefore, it is necessary to perform efficient and efficient design by forming a circuit by utilizing both the steps used for the logic section and the DRAM section.

An object of the present invention is to provide a semiconductor integrated circuit device in which a DRAM part and a logic part are mounted together and a manufacturing method thereof, which can simplify the manufacturing process and improve the design efficiency.

[0005]

A semiconductor integrated circuit device according to claim 1 is a semiconductor integrated circuit device in which a DRAM portion having a memory cell array and peripheral circuits and a logic portion are formed on the same semiconductor substrate. , The conductive layer forming the plate electrode of the memory cell of the DRAM part is
It is characterized in that it is arranged also in a predetermined region of the peripheral circuit and logic part of the portion, and the conductive layer arranged in this predetermined region is silicified and used as a wiring.

According to this structure, the same conductive layer as the plate electrode of the memory cell of the DRAM section is arranged in a predetermined region of the peripheral circuit and the logic section of the DRAM section and is silicidized to be used as the wiring. Since the same conductive layer as that of the plate electrode is used for, the process can be simplified and the design efficiency can be improved. In addition, the number of wiring layers increases, the degree of freedom in design increases, and the circuit area can be reduced.

A semiconductor integrated circuit device according to a second aspect of the present invention is a semiconductor integrated circuit device in which a DRAM portion having a memory cell array and peripheral circuits and a logic portion are formed on the same semiconductor substrate. The conductive layer forming the plate electrode is also arranged in a predetermined region of the peripheral circuit and the logic portion of the DRAM part, and the conductive layer arranged in the predetermined region is used as a resistance element.

According to this structure, the same conductive layer as that of the plate electrode of the memory cell of the DRAM section is arranged in a predetermined region of the peripheral circuit and the logic section of the DRAM section and used as a resistance element. Resistive elements can be formed at the same time, the process can be simplified, and the design efficiency can be improved. The semiconductor integrated circuit device according to claim 3 is a semiconductor integrated circuit device in which a DRAM section having a memory cell array and peripheral circuits and a logic section are formed on the same semiconductor substrate, wherein the plate electrode of the memory cell of the DRAM section. The conductive layer forming the conductive layer is also arranged in the first and second predetermined regions of the peripheral circuit and the logic portion of the DRAM part, and the conductive layer arranged in the first predetermined region is silicidized and used as a wiring. In addition, the conductive layer arranged in the second predetermined region is used as a resistance element.

According to this structure, the effects of both claim 1 and claim 2 can be obtained. The semiconductor integrated circuit device according to claim 4, wherein, in the semiconductor integrated circuit device according to claim 2 or 3, wherein the resistance element formed of a conductive layer is a resistive element luer analog in the circuit put in the logic portion <br/> It is characterized by

As a result, in the same process as the plate electrode of the memory cell of the DRAM section, the DA conversion circuit of the logic section,
A resistance element in an analog circuit such as an AD conversion circuit or a PLL circuit can be formed. A semiconductor integrated circuit device according to a fifth aspect is the semiconductor integrated circuit device according to the second or third aspect, wherein the resistance element formed of a conductive layer is a resistance element in a circuit having a self-refresh function of a peripheral circuit of the DRAM section. It is characterized by

As a result, the resistance element in the circuit having the self-refresh function of the peripheral circuit of the DRAM section can be formed in the same process as the plate electrode of the memory cell of the DRAM section. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the semiconductor integrated circuit device has a DRAM section having a memory cell array and peripheral circuits and a logic section formed on the same semiconductor substrate. By forming a conductive layer on the conductive layer and patterning it, a plate electrode of the memory cell of the DRAM section which is a pattern of a part of the conductive layer is formed, and at the same time, a predetermined area of the peripheral circuit and logic section of the DRAM section Of forming a conductive layer pattern on the substrate, and peripheral circuits and logic of the DRAM part
Part of the conductive layer pattern formed in a predetermined area of the part
Or a step of silicidizing the entire structure
And According to this manufacturing method, since the conductive layer pattern made of the same conductive layer as the plate electrode of the memory cell in the DRAM section is formed in a predetermined region of the peripheral circuit of the DRAM section and the logic section, the conductive layer pattern is formed into a resistor. It can be used as an element, a plate electrode and a resistance element can be simultaneously formed, and the process can be simplified and the design efficiency can be improved.

Then, a part or all of the conductive layer pattern can be silicidized to be used as a wiring. That is, depending on the difference in sheet resistance between the silicided portion and the non-silicided portion of the conductive layer pattern, the wiring and the resistance element can be used separately. Since the same conductive layer as the plate electrode is used for wiring and resistance elements,
The process can be simplified and the design efficiency can be improved.
In addition, the number of types of wiring layers has increased, increasing the freedom of design,
The circuit area can be reduced.

A method of manufacturing a semiconductor integrated circuit device according to a seventh aspect is the method of manufacturing a semiconductor integrated circuit device according to the sixth aspect , wherein when a part or all of the conductive layer pattern is silicidized, the periphery of the DRAM part is formed. It is characterized in that at least one of the gate electrode and the surface of the source / drain region of the MOS transistor formed in the circuit and the logic portion is simultaneously silicidized.

As described above, the silicidation of the conductive layer pattern is performed simultaneously with the silicidation of the surface of the gate electrode or the source / drain region of the MOS transistor,
Further, the process can be simplified.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.
1 shows a semiconductor integrated circuit device of a mixed type including a DRAM section including a memory cell array and peripheral circuits and a logic section. In FIG. 1, 11 is a semiconductor integrated circuit device of the present invention, 12 is a DRAM section, 13 is a logic section, and 14 is a DR.
An oscillation circuit for a self-refresh function inside the AM unit 12, 15 is a pad, 16 is a DA (digital / analog) conversion circuit, 17 is an AD (analog / digital) conversion circuit, and 18 is a PLL circuit.

FIG. 2 is a circuit diagram of a main part of the oscillator circuit 14 shown in FIG. In FIG. 2, D1 and D2 are diodes,
P1, P2, P3 are PMOS transistors, N1, N2
Is an NMOS transistor, R1 and R2 are resistive elements, and C1
Is a capacitor element, 21 is a NAND circuit, IN is an input terminal, and OUT is an output terminal. Diode D1,
D2 is connected in series between the power supply and ground at node S1. The PMOS transistor P3 has a source connected to the power supply, a gate connected to the input terminal IN, and a drain connected to the node S1. PMOS transistor P1 and NMOS
The transistor N1 constitutes the CMOS inverter 200, the input of the inverter 200 is connected to the node S1, and the output is connected to the node S2. The PMOS transistor P2 and the NMOS transistor N2 form a CMOS inverter 201, and the input of the inverter 201 is the node S.
2, the output is connected to node S3. The NAND circuit 21 receives the input terminal IN and the node S3 as its inputs, and its output is connected to the output terminal OUT. A resistance element R1 is connected between the nodes S1 and S4, a resistance element R2 is connected between the nodes S4 and the output terminal OUT, and a capacitor element C1 is connected between the nodes S3 and S4. .

In the configuration of FIG. 2, when the voltage applied to the input terminal IN is changed from "L (low)" to "H (high)", the capacitor element C1 may cause oscillation in the waveform at the output terminal OUT. The pulse width of the oscillation can be controlled by the sizes of the resistance elements R1 and R2 and the capacitor element C1. In order to use the pulse at the output terminal OUT for the self-refresh function or the like, the resistance element R
It is necessary that R1 and R2 have a large resistance value.

FIG. 3 is a plan view of a memory cell portion of the DRAM portion 12 of the semiconductor integrated circuit device 11 of FIG. 1 and a representative portion of the oscillator circuit 14 (a partial area A1 in the circuit diagram of FIG. 2). Is. 4 is a plan view of FIG.
It is sectional drawing in a line. In FIGS. 3 and 4, 400
2 is a DRAM cell area (memory cell area of the DRAM section 12), 404 is a partial area A1 in FIG.
NMOS transistor region where the NMOS transistor N1 is formed, 402 is a polysilicon wiring region, 403 is a resistance element region where the resistance element R1 of FIG. 2 is formed, 50 is a contact, 51 is a substrate, 52 is a deep N well, and 53 is shallow. N well, 54 P well, 55 field oxide film, 56 and 63 source regions, 57 and 64 drain regions, 58 a gate electrode made of a first polysilicon layer, 6
2 is a gate electrode made of a silicided first polysilicon layer, 59 is a storage electrode made of a second polysilicon layer, 60 is a plate electrode made of a third polysilicon layer (conductive layer), and 67 is a silicided Wiring made of a third polysilicon layer, 70 is a resistance element made of the third polysilicon layer (corresponding to the resistance element R1 in FIG. 2), 61, 6
5, 66, 68, 69, 71 and 72 are first wiring layers.

The DRAM cells in the DRAM cell region 400 are formed on the P well 54 on the deep N well 52, and the gate electrode 58 made of the first polysilicon layer,
Source region 56 and drain region 57 formed of a diffusion layer
And a storage electrode 59 made of the second polysilicon layer.
And a plate electrode 60 made of a third polysilicon layer. Although not clearly shown in FIG. 4, a dielectric film is formed between the storage electrode 59 and the plate electrode 60. The gate electrode 58 forms a word line, and the first wiring layer 61 is connected to the drain region 57 via a contact to form a bit line.

NMO of NMOS transistor region 401
The S-transistor is formed on the P-well 54 on the substrate 51, and has a gate electrode 62 made of a silicided first polysilicon layer, and a source region 63 and a drain region made of a diffusion layer having a silicided surface. 64, the gate electrode 62 is connected to the first wiring layer 71 via a contact (FIG. 3), the source region 63 is connected to the first wiring layer 65 via a contact, and the drain region 6 is provided.
4 is connected to the first wiring layer 66 via a contact.

In the polysilicon wiring region 402, a wiring 67 is formed by the silicided third polysilicon layer on the field oxide film 55, and the wiring 67 is 2
It is connected to the first wiring layers 68 and 65 via contacts at some points. The resistance element region 403 is formed above the field oxide film 55 by the third polysilicon layer.
Is formed, and the resistance element 70 is connected to the first wiring layers 71 and 72 via contacts at two locations. That is, the resistance element 70 is formed by utilizing the electric resistance of the third polysilicon layer between the two contacts connected to the first wiring layer 71 and the first wiring layer 72. Resistance element 7
0 is the gate electrode 62 of the NMOS transistor and the first
They are connected by the wiring layer 71. The resistance element 70
Are actually arranged in a meandering manner as shown in FIG. 3, but are not shown in an accurate cross section in FIG. 4 and are shown in a simplified manner.

Generally, the plate electrode of the DRAM does not consume current, and it is sufficient to always apply a predetermined voltage (for example, a voltage of about ½ of the power supply voltage). Therefore, the first polysilicon layer and the second polysilicon layer are required. Plate electrode 60 compared to layers
The third polysilicon layer forming the is thinly formed. Therefore, the sheet resistance value becomes higher than that of the first polysilicon layer or the second polysilicon layer, and it becomes effective to use it as a resistance element.

The wiring 67 is silicidized by further depositing a TiSi ₂ layer on the polysilicon layer formed in the same step as the third polysilicon layer forming the plate electrode 60 of the DRAM cell. It was done. The silicided polysilicon layer has a sheet resistance value of about 1/10 of that before the silicidation. Therefore, it can be used as wiring.

A method of manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention configured as described above will be described with reference to FIG. 5A, 5B, and 5C are process cross-sectional views showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. Here, the manufacturing process corresponding to the cross-sectional view of FIG. 4 will be described. To do. It should be noted that the formation of the interlayer insulating film, the opening thereof, and the like are formed by a known method, and a detailed description thereof will be omitted. Hereinafter, formation of a main portion will be described in detail. Also in FIG. 5, the resistance element 70 is not shown in an accurate cross section but is simplified in the same manner as in FIG. 4.

First, as shown in FIG. 5A, the substrate 51
A deep N well 52 to be used on the DRAM cell side is formed on the upper side, and a P well 54 on the deep N well 52 and a P well 54 on the substrate 1 are formed.
And a shallow N well 53 on the deep N well 52 is formed. Next, after forming a field oxide film 55, a gate oxide film is formed, and then a first polysilicon layer is deposited and etched in a predetermined pattern to form a gate electrode 58 of the DRAM cell and a gate electrode 62 of the NMOS transistor. To form. Diffusion layers are formed using the gate electrodes 58 and 62 as masks to form source regions 56 and 63 and drain regions 57,
64.

Next, after forming an interlayer insulating film, etc., FIG.
As shown in, a second polysilicon layer is deposited and etched into a predetermined pattern to form a storage electrode 59 of the DRAM cell. After forming a dielectric film (not shown) on the storage electrode 59, a third polysilicon layer is deposited and etched into a predetermined pattern to form a plate electrode 60 of the DRAM cell and, at the same time, a field oxide film 55.
A wiring polysilicon layer 67 'and a resistance element 70 are provided on the upper portion.
To form.

Next, as shown in FIG. 5C, after an oxide film 73 is formed on the entire surface by TEOS growth, a photoresist mask A2 is formed on the third polysilicon layer not used for wiring.
(In FIG. 5, the mask region is shown as A2), the oxide film 73 is removed, a TiSi ₂ layer is deposited, and the wiring polysilicon layer 67 ′ is silicided to form the wiring 67. The gate electrode 62, the source region 63 and the drain region 64 of the NMOS transistor are silicidized.

After that, after forming an interlayer insulating film, contacts, etc., the first wiring layers 61, 65, 66, 68, 69, 71,
Forming 72 results in the cross-sectional view shown in FIG. As described above, according to the present embodiment, on the substrate 51, the DRAM cell, the NMOS transistor, and the wiring 67 formed by silicidizing the third polysilicon layer also used for the plate electrode 60 of the DRAM cell, The resistance element 70 made of the third polysilicon layer is formed. Since the wiring 67 and the resistance element 70 are formed by using the third polysilicon layer that forms the plate electrode 60, the process peculiar to the DRAM can be effectively utilized, the process can be simplified, and the design efficiency can be improved. Can be realized.

Further, since the wiring polysilicon layer 67 'which becomes the wiring 67 is silicidized at the same time as the silicidation of the gate electrode 62, the source region 63 and the drain region 64 of the NMOS transistor, the existing process is effectively utilized. And contributes to simplification of the process. That is, the process of siliciding the polysilicon layer is performed by the conventional general-purpose DRA.
It is generally not used in M but used in the logic section. In the present embodiment, the third polysilicon layer also used for the plate electrode 60 of the DRAM cell is used as a peripheral circuit of the DRAM section 12 (oscillation circuit). 14) and form mask A2
And the oxide film 73 is used to divide into a region where silicidation is performed and a region where silicidation is not performed, and by performing silicidation which is originally a process of the logic portion, the wiring 67 and the resistance element 70 using the third polysilicon layer By forming a circuit by using both the original logic part process and the process peculiar to DRAM in this way, a wasteless and efficient design can be achieved and the process can be simplified. Is something that can be done.

Further, in the above-described embodiment, an example in which the wiring 67 and the resistance element 70 using the same third polysilicon layer as the plate electrode 60 are used in the oscillation circuit 14 in the DRAM section 12 is shown. Other peripheral circuits in 12 and analog circuits such as the DA conversion circuit 16, the AD conversion circuit 17, and the PLL circuit 18 in the logic unit 13 can be used in the same manner.

Further, in the above-described embodiment, an example is shown in which the same third polysilicon layer as the plate electrode 60 is used for the wiring 67 and the resistance element 70, but it may be used only for the wiring or only for the resistance element. Needless to say. In the above embodiment, silicidation is described using TiSi ₂ , but the present invention is not limited to this.

Further, since the wiring 67 is formed by using the same third polysilicon layer as the plate electrode 60, the number of types of wiring layers increases, the degree of freedom in design increases, and the circuit area can be reduced. This will be further described with reference to FIG. FIG. 6 is a plan view of another region (for example, a wiring dense region of the logic unit 13) in the semiconductor integrated circuit device of the above embodiment. In FIG. 6, 81, 82,
Reference numeral 83 is a first wiring layer which is the same layer as the first wiring layer 61 and the like, 84 is a second wiring layer formed above the first wiring layers 81, 82 and 83 via an insulating film, and 85, 86 and 87 are Second wiring layer 8
A third wiring layer formed on the upper part of 4 through an insulating film, 8
Reference numeral 8 is a wiring made of a first polysilicon layer in the same layer as the gate electrode 58, 89 is a wiring made of a silicided third polysilicon layer similarly to the wiring 67, and 90 is a contact.

In the area shown in FIG. 6, the first wiring layer 8 is formed.
A second wiring layer 84 is arranged on the upper portions of the second wiring layer 83 and the second wiring layer 83 in parallel therewith, and the first wiring layers 82 and 83 and the second wiring layer 8 are arranged.
The third wiring layer 85 is formed on the upper part of 4 so as to intersect them.
86 and 87 are arranged. Further, there is a first wiring layer 82 between the first wiring layer 83 and the first wiring layer 81, and the first wiring layer 83 and the first wiring layer 8 are avoided while avoiding the first wiring layer 82.
1 and the contact 90 and the silicided third
They are connected by a wiring 89 made of a polysilicon layer.

As described above, in FIG. 6, in order to avoid the first wiring layer 82 and connect the first wiring layer 83 and the first wiring layer 81, the same third electrode as the plate electrode 60 (FIGS. 3 to 5) is used. By using the wiring 89 made of the polysilicon layer, the degree of freedom in performing the placement and wiring is expanded, and the area can be reduced.

[0035]

As described above, according to the present invention, the DRAM
Same conductive layer as the plate electrode of the memory cell
It can be used as a resistance element by forming it in the peripheral circuit or logic section of the M section. Further, the same conductive layer as the plate electrode formed in the peripheral circuit of the DRAM part or the logic part can be silicidized and used as a wiring. Thus, using the same conductive layer as the plate electrode, D
Since the resistance element and the wiring can be formed in the peripheral circuit of the RAM section and the logic section, the process can be simplified and the design efficiency can be improved. In addition, since the wiring is formed using the same conductive layer as the plate electrode, the number of types of wiring layers increases, the degree of freedom in design increases, and the circuit area can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a main part of the oscillator circuit in FIG.

3 is a memory cell portion of a DRAM portion in FIG.
It is a top view of a typical portion of an oscillation circuit.

FIG. 4 is a cross-sectional view taken along the line II ′ in FIG.

FIG. 5 is a process cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device in the embodiment of the present invention.

FIG. 6 is a plan view of another region of the semiconductor integrated circuit device according to the embodiment of the present invention.

[Explanation of symbols]

11 semiconductor integrated circuit device 12 DRAM part 13 logic part 14 oscillator circuit 15 pads D1, D2 diodes P1, P2, P3 PMOS transistors N1, N2 NMOS transistors S1, S2, S3, S4 nodes R1, R2 resistance element C1 capacitor element IN input Terminal OUT Output terminal 21 NAND circuit 400 DRAM cell region 401 NMOS transistor region 402 Polysilicon wiring region 403 Resistance element region 50 Contact 51 Substrate 52 Deep N well 53 Shallow N well 54 P well 55 Field oxide film 56, 63 Source region 57, 64 drain region 58, 62 gate electrode 59 storage electrode 60 plate electrode 67 wiring 67 'wiring polysilicon layer 70 resistance element 61, 65, 66, 68, 69, 71, 72 first wiring layer 81, 2,83 first wiring layer 84 second wiring layer 85, 86 and 87 the third wiring layer 88 wiring 89 wiring 90 contact

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-283647 (JP, A) JP-A-9-129844 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 21/3205 H01L 21/822 H01L 27/04 H01L 27/108

Claims (7)

(57) [Claims] 1. A semiconductor integrated circuit device in which a DRAM section having a memory cell array and peripheral circuits and a logic section are formed on the same semiconductor substrate, the conductive layer forming a plate electrode of a memory cell of the DRAM section. Is also arranged in a predetermined region of the peripheral circuit of the DRAM part and the logic part, and the conductive layer arranged in the predetermined region is silicidized and used as a wiring. . 2. A semiconductor integrated circuit device in which a DRAM section having a memory cell array and peripheral circuits and a logic section are formed on the same semiconductor substrate, the conductive layer forming a plate electrode of a memory cell of the DRAM section. Is also arranged in a predetermined region of the peripheral circuit of the DRAM part and the logic part, and the conductive layer arranged in the predetermined region is used as a resistance element. 3. A semiconductor integrated circuit device in which a DRAM section having a memory cell array and peripheral circuits and a logic section are formed on the same semiconductor substrate, the conductive layer forming a plate electrode of a memory cell of the DRAM section. Is also arranged in the peripheral circuit of the DRAM section and the first and second predetermined regions of the logic section,
A semiconductor integrated circuit device, wherein the conductive layer arranged in the first predetermined region is silicidized and used as a wiring, and the conductive layer arranged in the second predetermined region is used as a resistance element. . 4. A resistive element comprising a conductive layer, a semiconductor integrated circuit device according to claim 2 or 3, wherein it is a resistive element luer analog in the circuit put in the logic unit. 5. The semiconductor integrated circuit device according to claim 2, wherein the resistance element formed of the conductive layer is a resistance element in a circuit having a self-refresh function of a peripheral circuit of the DRAM section. 6. A method of manufacturing a semiconductor integrated circuit device, wherein a DRAM section having a memory cell array and peripheral circuits and a logic section are formed on the same semiconductor substrate, wherein a conductive layer is formed on the semiconductor substrate. By patterning, the D consisting of a part of the pattern of the conductive layer is formed.
Forming the plate electrode of the memory cell of the RAM section and simultaneously forming the conductive layer pattern in a predetermined region of the peripheral circuit of the DRAM section and the logic section.
When, in the peripheral circuit and the logic portion of the DRAM portion
Part of the conductive layer pattern formed in a predetermined area of
And a step of silicidizing all of them, the method of manufacturing a semiconductor integrated circuit device. 7. When siliciding a part or all of the conductive layer pattern, at least one of the gate electrode and the source / drain region surface of the MOS transistor formed in the peripheral circuit of the DRAM part and the logic part should be silicidized at the same time. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6 .