KR950010066A - Semiconductor device having thin film wiring and manufacturing method thereof - Google Patents

Semiconductor device having thin film wiring and manufacturing method thereof Download PDF

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KR950010066A
KR950010066A KR1019940022836A KR19940022836A KR950010066A KR 950010066 A KR950010066 A KR 950010066A KR 1019940022836 A KR1019940022836 A KR 1019940022836A KR 19940022836 A KR19940022836 A KR 19940022836A KR 950010066 A KR950010066 A KR 950010066A
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type polysilicon
electrodes
thin film
wirings
insulating layers
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히로시 시미즈
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세끼자와 다다시
후지쓰 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

기판(3, 43), 기판(3, 43)을 덮는 절연층(32, 83)및 절연층(32, 83)상에 형성된 배선(17, 62, 66)을 구비한 반도체 장치는 기판(3, 43), 절연층(32, 83) 사이에 형성된 n형 폴리실리콘 전극(28, 79, 80) 및 p형 폴리실리콘 전극(14, 59, 63)및 n형 폴리실리콘 전극(28, 79, 80) 과 p형 폴리실리콘 전극(14, 59, 63)을 접속하기 위하여 절연층(32, 83)과 기판(3, 43)사이에 형성되는 박막배선(15, 60, 64)을 포함하며, 상기 박막 배선(15, 60, 64)은 절연층(32, 83)을 뚫어 형성된 단일 콘텍트 홀(16, 61, 65)을 통하여 배선(17, 62, 66)에 접속된다.A semiconductor device having a substrate 3, 43, insulating layers 32, 83 covering the substrates 3, 43, and wirings 17, 62, 66 formed on the insulating layers 32, 83 includes a substrate 3. 43, n-type polysilicon electrodes 28, 79, 80 and p-type polysilicon electrodes 14, 59, 63 and n-type polysilicon electrodes 28, 79, formed between insulating layers 32, 83, 80 and thin film wirings 15, 60 and 64 formed between the insulating layers 32 and 83 and the substrates 3 and 43 for connecting the p-type polysilicon electrodes 14, 59 and 63, The thin film wirings 15, 60, and 64 are connected to the wirings 17, 62, and 66 through single contact holes 16, 61, and 65 formed through the insulating layers 32 and 83.

Description

박막배선을 갖는 반도체장치와 그의 제조방법Semiconductor device having thin film wiring and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제8도는 본 발명의 다른 실시예로 NAND게이트로 작용하는 이중게이트 구조로 함께 접속된 p채널 트랜지스터들과 n채널 트랜지스터들을 갖는 CMOS회로의 평면도.8 is a plan view of a CMOS circuit having p-channel transistors and n-channel transistors connected together in a double gate structure serving as a NAND gate in another embodiment of the present invention.

제9도는 제8도의 CMOS회로의 단면도.9 is a cross-sectional view of the CMOS circuit of FIG.

제10도는 제8도의 CMOS회로의 다른 단면도.FIG. 10 is another cross-sectional view of the CMOS circuit of FIG. 8. FIG.

제11도는 제8도의 CMOS회로의 등가회로도.FIG. 11 is an equivalent circuit diagram of the CMOS circuit of FIG. 8. FIG.

Claims (9)

기판(3, 43), 상기 기판을 덮는 절연층(32, 83)및 상기 절연층(32, 83)상에 형성된 배선(17, 62, 66)을 갖는 반도체 장치에 있어서, 상기 기판(3, 43)과 절연층(32, 83)사이에 형성된 n형 폴리실리콘 전극(28, 79, 80)과, 상기 기판(3, 43)과 상기 절연층(32, 83)사이에 형성된 p형 폴리실리콘 전극(14, 59, 63)과, n형 상기 폴리실리콘 전극(28, 79, 80) 및 상기 p형 폴리실리콘 전극(14, 59, 63)을 접속하기 위하여 상기 절연층(32, 83)과 상기 기판(3, 43)사이에 형성되는 상기 박막배선(15, 60, 64)으로 구성되며, 상기 박막배선(15, 60, 64)은 절연층(32, 83)을 뚫고 형성된 단일 콘텍트 홀(16, 61, 65)을 통하여 배선(17, 62, 66)에 접속되는 것을 특징으로 하는 반도체 장치.In a semiconductor device having a substrate (3, 43), an insulating layer (32, 83) covering the substrate and wirings (17, 62, 66) formed on the insulating layer (32, 83), the substrate (3, N-type polysilicon electrodes 28, 79 and 80 formed between 43 and insulating layers 32 and 83, and p-type polysilicon formed between substrates 3 and 43 and insulating layers 32 and 83 The insulating layers 32 and 83 to connect the electrodes 14, 59, 63, the n-type polysilicon electrodes 28, 79, 80, and the p-type polysilicon electrodes 14, 59, 63. The thin film wirings 15, 60, and 64 are formed between the substrates 3 and 43, and the thin film wirings 15, 60, and 64 are formed of a single contact hole formed through the insulating layers 32 and 83. A semiconductor device, characterized in that connected to a wiring (17, 62, 66) via 16, 61, 65. 제1항에 있어서, 상기 n형 폴리실리콘 전극(28, 79, 80)은 n채널 MOSFET(Q2, Q13, Q14)(금속 산화물 반도체 전계 효과 트랜지스터)의 n형 폴리실리콘 게이트 전극으로, 상기 p형 폴리실리콘 전극(14, 59, 63)은 p채널 MOSFET(Q1, Q11, Q12)의 p형 폴리실리콘 게이트 전극으로 구성됨을 특징으로 하는 반도체 장치.The n-type polysilicon electrodes 28, 79, and 80 are n-type polysilicon gate electrodes of n-channel MOSFETs Q 2 , Q 13 , and Q 14 (metal oxide semiconductor field effect transistors). Wherein said p-type polysilicon electrode (14, 59, 63) is comprised of a p-type polysilicon gate electrode of a p-channel MOSFET (Q 1 , Q 11 , Q 12 ). 제1항에 있어서, 상기 기판(3, 43)과 상기 절연층(32, 83)사이에 로컬 인터커넥터들을 더 구비하며, 또 상기 박막 배선(15, 60, 64)이 상기 로컬 인터커넥터의 물질과 같을 물질로 형성되고 또한 상기 로컬 인터커넥터를 형성하는 공정과 같은 공정으로 형성될 수 있는 것을 특징으로 하는 반도체 장치.Further comprising local interconnects between the substrates (3, 43) and the insulating layers (32, 83), wherein the thin film interconnects (15, 60, 64) are made of the material of the local interconnector. A semiconductor device, characterized in that formed of a material such as, and can be formed by the same process as the step of forming the local interconnector. 제2항에 있어서, 상기 기판(3, 43)과 상기 절연층(32, 83)사이에 로컬 인터커넥터들을 더 구비하며, 또 상기 박막 배선(15, 60, 64)이 상기 로컬 인터커넥터의 물질과 같을 물질로 형성되고 또한 상기 로컬 인터커넥터를 형성하는 공정과 같은 공정으로 형성될 수 있는 것을 특징으로 하는 반도체 장치.3. The device of claim 2, further comprising local interconnects between the substrates (3, 43) and the insulating layers (32, 83), wherein the thin film interconnects (15, 60, 64) are made of the material of the local interconnector. A semiconductor device, characterized in that formed of a material such as, and can be formed by the same process as the step of forming the local interconnector. 제2항에 있어서, 상기 박막 배선(15, 60, 64)이 또한 상기 p채널 MOSFET(Q1, Q11, Q12)의 드레인과 상기 n채널 MOSFET(Q2, Q13, Q14)의 드레인에 접속됨을 특징으로 하는 반도체 장치.3. The thin film wirings (15, 60, 64) of claim 2 are also used for draining the p-channel MOSFETs (Q 1 , Q 11 , Q 12 ) and the n-channel MOSFETs (Q 2 , Q 13 , Q 14 ). And a drain connected to the drain. 기판(3, 43), 상기 기판(3, 43)을 덮는 절연층(32, 84)및 상기 절연층(32, 83)밑에 형성되는 n형 폴리실리콘 적극(28, 79, 80)과 p형 폴리실리콘 전극(14, 59, 63)에 전기적으로 접속되는 상기 절연층(32, 83)상의 배선(17, 62, 66)을 구비하는 반도체 장치의 제조 방법에 있어서, 상기 n형 폴리실리콘 전극(28, 79, 80)및 p형 폴리실리콘 전극(14, 59, 63)을 덮는 상기 박막층을 상기 기판(3, 43)의 최상단에 형성되는 단계, 상기 n형 폴리실리콘 전극(28, 79, 80) 및 상기 p형 폴리실리콘 전극(14, 59, 63)사이의 상기 박막층을 덮는 포토레지스트를 패턴화하는 단계, 상기 n형 폴리실리콘 전극(28, 79, 80)과 p형 폴리실리콘 전극(14, 59, 63)을 접속하는 박막배선(15, 60, 64)을 형성하기 위하여 상기 박막 층을 에칭하는 단계, 상기 박막배선(15, 60, 64)의 부분에 단일 콘텍트 홀(16, 61, 65)을 갖는 상기 절연층(32, 83)을 형성하는 단계, 상기 배선(17, 62, 66)이 상기 단일 콘텍트 홀(16, 61, 65)을 통하여 상기 박막 배선(15, 60, 64)에 접속되도록 상기 절연층(32, 83)상에 상기 배선(17, 62, 66)을 형성하는 단계의 순서로 반도체 장치를 제조하는 것을 특징으로 하는 반도체 장치의 제조 방법.N-type polysilicon actives 28, 79, 80 and p-type formed under the substrates 3 and 43, the insulating layers 32 and 84 covering the substrates 3 and 43, and the insulating layers 32 and 83 In the method of manufacturing a semiconductor device having the wirings 17, 62, 66 on the insulating layers 32, 83 electrically connected to the polysilicon electrodes 14, 59, 63, the n-type polysilicon electrode ( 28, 79, 80 and the thin film layer covering the p-type polysilicon electrodes 14, 59, 63 are formed at the top of the substrate (3, 43), the n-type polysilicon electrodes (28, 79, 80) And patterning a photoresist covering the thin film layer between the p-type polysilicon electrodes 14, 59, and 63, the n-type polysilicon electrodes 28, 79, and 80 and the p-type polysilicon electrode 14. Etching the thin film layer to form the thin film wirings 15, 60 and 64 connecting the plurality of thin film wirings 59, 63, and the single contact hole 16, 61, 65) with insulation Forming layers 32, 83, such that the wirings 17, 62, 66 are connected to the thin film wirings 15, 60, 64 through the single contact holes 16, 61, 65; A semiconductor device manufacturing method, characterized in that the semiconductor device is manufactured in the order of forming the wirings (17, 62, 66) on (32, 83). 제6항에 있어서, 상기 n형 폴리실리콘 전극(28, 79, 80)은 n채널 MOSFET(Q2, Q13, Q14)의 n형 폴리실리콘 게이트 전극으로, 상기 p형 폴리실리콘 전극(14, 59, 63)은 p채널 MOSFET(Q1, Q11, Q12)의 p형 폴리실리콘 게이트 전극으로 구성하여 반도체 장치를 제조하는 것을 특징으로 하는 반도체 장치의 제조방법.The n-type polysilicon electrodes 28, 79, and 80 are n-type polysilicon gate electrodes of n-channel MOSFETs Q 2 , Q 13 , and Q 14 , and the p-type polysilicon electrodes 14 are formed. And 59, 63 are composed of p-type polysilicon gate electrodes of p-channel MOSFETs (Q 1 , Q 11 , Q 12 ) to manufacture a semiconductor device. 기판(3, 43), 상기 기판(3, 43)을 덮는 절연층(32, 83)및 상기 절연층(32, 83)밑에 형성되는 n형 폴리실리콘 전극(28, 79, 80)과 p형 폴리실리콘 전극(14, 59, 63)에 전기적으로 접속되는 상기 절연층(32, 83)상의 배선(17, 62, 66)을 구비하는 반도체 장치의 제조 방법에 있어서, 상기 n형 폴리실리콘 전극(28, 79, 80)및 상기 p형 폴리실리콘 전극(14, 59, 63)을 덮는 상기 박막층을 상기 기판(3, 43)의 최상단에 형성되는 단계, 상기 박막층의 최상단에 인실리콘층을 형성하는 단계, 상기 n형 폴리실리콘 전극(28, 79, 80) 및 상기 p형 폴리실리콘 전극(14, 59, 63)사이에 상기 인 실리콘 층을 덮는 포토레지스트를 패턴화하는 단계, 상기 n형 폴리실리콘 전극(28, 79, 80)과 상기 p형 폴리실리콘 전극(14, 59, 63)사이에 인 실리콘 배선(15, 60, 64)을 형성하기 위하여 상기 인 실리콘 층을 에칭하는 단계, 상기 인 실리콘 배선(15, 60, 64)내에 실리사이드를 만들기 위하여, 상기 n형 폴리실리콘 전극(28, 79, 80) 및 상기 p형 폴리실리콘 전극(14, 59, 63) 실리사이드 형성 반응을 실시하고, 실리사이드가 형성되지 않은 박막층을 제거하는 단계, 상기 인 실리콘 배선(15, 60, 64)의 부분에 단일 콘텍트 홀(16, 61, 65)을 갖는 절연층(32, 83)을 형성하는 단계, 상기 배선(17, 62, 66)이 상기 단일 콘텍트 홀(16, 61, 65)을 통하여 상기 인 실리콘 배선(15, 60, 64)에 접속되도록 상기 절연층(32, 83)상에 상기 배선(17, 62, 66)을 제조하는 단계의 순서로 반도체 장치를 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.N-type polysilicon electrodes 28, 79, 80 and p-type formed under the substrates 3 and 43, the insulating layers 32 and 83 covering the substrates 3 and 43, and the insulating layers 32 and 83 In the method of manufacturing a semiconductor device having the wirings 17, 62, 66 on the insulating layers 32, 83 electrically connected to the polysilicon electrodes 14, 59, 63, the n-type polysilicon electrode ( 28, 79, 80) and the thin film layer covering the p-type polysilicon electrodes 14, 59, 63 are formed on the top of the substrate (3, 43), to form an in-silicon layer on the top of the thin film layer Patterning a photoresist covering the phosphorus silicon layer between the n-type polysilicon electrodes 28, 79, and 80 and the p-type polysilicon electrodes 14, 59, and 63, wherein the n-type polysilicon Etching the phosphorus silicon layer to form phosphorus silicon interconnects 15, 60, 64 between electrodes 28, 79, 80 and the p-type polysilicon electrodes 14, 59, 63, In order to make silicide in the phosphorus silicon wirings 15, 60 and 64, a silicide formation reaction of the n-type polysilicon electrodes 28, 79 and 80 and the p-type polysilicon electrodes 14, 59 and 63 is performed. Removing the thin film layer in which silicide is not formed, forming the insulating layers 32 and 83 having single contact holes 16, 61, and 65 in portions of the phosphorus silicon wires 15, 60, and 64. The wiring on the insulating layers 32 and 83 such that the wirings 17, 62 and 66 are connected to the phosphorus silicon wirings 15, 60 and 64 through the single contact holes 16, 61 and 65. 17, 62, 66) A method for manufacturing a semiconductor device, characterized in that to form a semiconductor device in the order of manufacturing step. 제8항에 있어서, 상기 n형 폴리실리콘 전극(28, 79, 80)은 n채널 MOSFET(Q2, Q13, Q14)의 n형 폴리실리콘 게이트 전극으로, 상기 p형 폴리실리콘 전극(14, 59, 63)은 p채널 MOSFET(Q1, Q11, Q12)의 p형 폴리실리콘 게이트 전극으로 구성하여 반도체 장치를 제조하는 것을 특징으로 하는 반도체 장치의 제조방법.The n-type polysilicon electrodes 28, 79, and 80 are n-type polysilicon gate electrodes of n-channel MOSFETs Q 2 , Q 13 , and Q 14 , and the p-type polysilicon electrodes 14 are formed. And 59, 63 are composed of p-type polysilicon gate electrodes of p-channel MOSFETs (Q 1 , Q 11 , Q 12 ) to manufacture a semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940022836A 1993-09-10 1994-09-10 Semiconductor device having thin film wiring and manufacturing method thereof KR950010066A (en)

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