KR100511090B1 - Metal wiring formation method of MOS PET transistor - Google Patents

Metal wiring formation method of MOS PET transistor Download PDF

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KR100511090B1
KR100511090B1 KR1019970077353A KR19970077353A KR100511090B1 KR 100511090 B1 KR100511090 B1 KR 100511090B1 KR 1019970077353 A KR1019970077353 A KR 1019970077353A KR 19970077353 A KR19970077353 A KR 19970077353A KR 100511090 B1 KR100511090 B1 KR 100511090B1
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gate electrode
film
nitride
active region
metal wiring
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KR19990057303A (en
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서을규
백성학
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides

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Abstract

본 발명은 모스형페트트랜지스터의 금속배선에 관한 것으로서, 특히, 반도체기판의 필드산화막과 게이트전극 상에 패드산화막과 폴리실리콘막을 순차적으로 증착하고서 블랭킹 식각을 통하여 게이트전극 외측에 스페이서를 형성하는 단계와; 상기 단계 후에 상부면에 나이트라이드막을 증착하고, 이 나이트라이드막상에서 비활성영역에 감광막을 증착하여, 식각으로 통하여 활성영역의 나이트라이드막을 식각하고 감광막을 제거하는 단계와; 상기 단계 후에 블랭킹 식각을 통하여 활성영역의 게이트전극의 스페이서 외측에 나이트라이드 스페이서를 형성하는 단계와; 상기 단계 후에 나이트라이드 스페이서를 제외한 게이트전극과 활성영역에 금속배선라인을 형성하는 단계로 이루어진 모스페트트랜지스터의 금속배선 형성방법인 바, 게이트전극과 활성 영역을 티타늄실리사이드화시킨 금속배선라인을 형성하므로 신호의 전송선로를 줄여주어 밀도 높은 회로의 설계를 가능하도록 하는 매우 유용하고 효과적인 발명이다.The present invention relates to a metal wiring of a MOS-type transistor, in particular, the step of depositing a pad oxide film and a polysilicon film sequentially on the field oxide film and the gate electrode of the semiconductor substrate to form a spacer outside the gate electrode through the blanking etching and ; Depositing a nitride film on the upper surface after the step, and depositing a photoresist film on the inactive region on the nitride film to etch the nitride film of the active region by etching and to remove the photoresist film; Forming a nitride spacer outside the spacer of the gate electrode of the active region through blanking etching after the step; After forming the metal wiring line of the MOSFET transistor, the metal wiring line is formed on the gate electrode and the active region except for the nitride spacer, and thus the metal wiring line is formed by titanium silicided the gate electrode and the active region. It is a very useful and effective invention that enables the design of dense circuits by reducing signal transmission lines.

Description

모스페트트랜지스터의 금속배선 형성방법 Metal wiring formation method of MOS PET transistor

본 발명은 모스페트트랜지스터의 금속배선에 관한 것으로, 특히, 비활성영역에 있는 스페이서의 외측에 나이트라이드막을 증착하여서 게이트전극과 활성 영역을 티타늄실리사이드화시킨 금속배선라인을 형성하므로 신호의 전송선로를 줄여주어 밀도 높은 회로의 설계를 가능하도록 하는 모스페트트랜지스터의 금속배선 형성방법에 관한 것이다.The present invention relates to a metal wiring of a MOS PET transistor, and in particular, by depositing a nitride film on the outside of the spacer in the inactive region to form a metal wiring line of titanium silicide of the gate electrode and the active region, thereby reducing the signal transmission line The present invention relates to a method for forming a metal wiring of a MOS transistor transistor to enable the design of a high density circuit.

일반적으로, 반도체장치의 종류에는 여러 가지가 있으며, 이 반도체장치 내에 형성되는 트랜지스터 및 커패시터등을 구성시키는 방법에는 다양한 제조기술이 사용되고 있으며, 최근에는 반도체기판 상에 산화막을 입혀 전계효과를 내도록 하는 모스형 전계효과 트랜지스터(MOSFET; metal oxide semiconductor field effect transistor)(이하, 모스페트트랜지스터라 칭함)를 점차적으로 많이 사용하고 있는 실정에 있다.In general, there are many kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors, capacitors, etc. formed in the semiconductor device, and in recent years, MOS is formed to apply an oxide film on a semiconductor substrate to produce an electric field effect. Metal oxide semiconductor field effect transistors (MOSFETs, hereinafter referred to as MOSFET transistors) are increasingly used.

상기한 모스페트트랜지스터는 반도체 기판상에 형성된 게이트가 반도체층에서 얇은 산화 실리콘막에 의해 격리되어 있는 전계효과 트랜지스터로서 접합형 트랜지스터와 같이 임피던스가 저하되는 일이 없으며, 확산 공정이 1회로 간단하고, 소자간의 분리가 필요 없는 장점을 지니고 있어서, 고밀도 집적화에 적합한 특성을 지니고 있는 반도체 장치이다.The MOSFET transistor is a field effect transistor in which a gate formed on a semiconductor substrate is isolated by a thin silicon oxide film in a semiconductor layer, so that impedance is not lowered like a junction transistor, and the diffusion process is simple in one time. The semiconductor device has an advantage of not requiring separation between devices, and has characteristics suitable for high density integration.

종래의 모스페트트랜지스터에는 배선으로 사용되는 금속배선층을 형성하기 위하여 반도체기판 상의 절연막을 일정한 간격과 깊이로 식각하여 콘택홀(Contact hole)을 형성하고, 이 콘택홀내에 소오스/드레인으로 전기적으로 연결되는 금속배선층을 증착하여 상부금속라인을 활성영역과 전기적으로 연결하게 되는 것이다. In conventional MOSFET transistors, an insulating film on a semiconductor substrate is etched at regular intervals and depths to form a metal wiring layer to be used as a wiring to form contact holes, and the contact holes are electrically connected to sources / drains in the contact holes. By depositing a metal wiring layer, the upper metal line is electrically connected to the active region.

도 1은 종래의 일반적인 금속배선 연결구조에 대하여 개략적으로 보인 도면으로서, 반도체기판(1)에 필드산화막(2)과 게이트전극(5)을 형성하고서, 이 양자의 상부면에 절연막(3)을 두껍게 증착한 후에 게이트전극(5)과 반도체기판의 활성영역(Active Drain)에 식각을 통하여 콘택을 형성하도록 한다.FIG. 1 is a view schematically showing a conventional metal wiring connection structure, in which a field oxide film 2 and a gate electrode 5 are formed on a semiconductor substrate 1, and an insulating film 3 is formed on the upper surface of both. After the deposition is made thick, a contact is formed by etching the gate electrode 5 and the active region of the semiconductor substrate.

그리고, 이 콘택을 통하여 텅스텐과 같은 금속재질을 주입하고, 그 위에 상부배선라인(7)을 증착하여 식각하므로 도 1에 도시된 바와 같이, 게이트전극(5)과 반도체기판(1)의 활성영역 사이에 금속라인이 연결되어져서 전기적으로 도전되는 금속배선(Inter Connection)상태로 있게 되는 것이다. Then, a metal material such as tungsten is injected through the contact, and the upper wiring line 7 is deposited and etched thereon, so that the active region of the gate electrode 5 and the semiconductor substrate 1 is shown in FIG. The metal lines are connected to each other so that the metal wires are electrically connected to each other.

그런데, 상기한 바와 같이, 게이트전극(5)의 상부면을 콘택으로 연결하고, 이 콘택을 상부배선라인을 통하여 다른 콘택으로 통하여 반도체기판(1)의 활성영역에 연결하는 방식은 콘택이 형성되기 위한 넓은 면적이 게이트전극과 활성영역에 필요하게 되며, 이로 인하여 전반적인 회로가 복잡하게 되고, 트랜지스터의 집적도를 제약하게 되는 요인으로 작용하게 될 뿐만아니라 신호의 전송라인이 복잡하고 길어지며, 층상에 있는 커패시턴스 성분으로 인하여 신호의 전송시간이 길어지는 등의 문제점을 지니고 있었다. However, as described above, a method of connecting a top surface of the gate electrode 5 to a contact and connecting the contact to another active contact through the upper wiring line to the active region of the semiconductor substrate 1 is to form a contact. A large area is required for the gate electrode and the active region, which not only complicates the overall circuit and restricts the integration of the transistor, but also complicated and lengthens the transmission line of the signal. Due to the capacitance component, the transmission time of the signal was long.

본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판에서 두 개의 필드산화막과 이 필드산화막 사이에 형성되는 게이트전극 상에 나이트라이드막을 증착하고, 감광막을 이용하여 나이트라이드막을 식각하여서 활성영역에는 나이트라이드막을 모두 식각하여 스페이서를 노출하고, 비 활성영역에 있는 스페이서의 외측에는 나이트라이드막을 증착하여서 게이트전극과 활성 영역을 티타늄실리사이드화시킨 금속배선라인을 형성하므로 신호의 전송선로를 줄여주어 밀도 높은 회로의 설계를 가능하도록 하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and a nitride film is deposited on two field oxide films and a gate electrode formed between the field oxide films on a semiconductor substrate, and the nitride film is etched using a photoresist film, thereby forming a nitride in the active region. Etch all of the ride films to expose the spacers, and deposit a nitride film on the outside of the spacers in the non-active region to form a metal wiring line in which the gate electrode and the active region are titanium silicided, thereby reducing the signal transmission line and thus providing a high density circuit. The purpose is to enable the design of.

이러한 목적은 반도체기판의 필드산화막과 게이트전극 상에 패드산화막과 폴리실리콘막을 순차적으로 증착하고서 블랭킹 식각을 통하여 게이트전극 외측에 스페이서를 형성하는 단계와; 상기 단계 후에 상부면에 나이트라이드막을 증착하고, 이 나이트라이드막 상에서 비활성영역에 감광막을 증착하여, 활성영역의 나이트라이드막을 식각하고 감광막을 제거하는 단계와; 상기 단계 후에 블랭킹 식각을 통하여 활성영역의 게이트전극의 스페이서 외측에 나이트라이드 스페이서를 형성하는 단계와; 상기 단계 후에 나이트라이드 스페이서를 제외한 게이트전극과 활성영역에 금속배선라인을 형성하는 단계로 이루어진 모스페트트랜지스터의 금속배선 형성방법을 제공함으로써 달성된다. The object of the present invention is to sequentially deposit a pad oxide film and a polysilicon film on a field oxide film and a gate electrode of a semiconductor substrate and form a spacer outside the gate electrode through blanking etching; Depositing a nitride film on the upper surface after the step, and depositing a photosensitive film on the inactive region on the nitride film to etch the nitride film of the active region and remove the photosensitive film; Forming a nitride spacer outside the spacer of the gate electrode of the active region through blanking etching after the step; After the step is achieved by providing a method for forming a metal wiring of the MOSFET transistor consisting of forming a metal wiring line in the gate electrode and the active region excluding the nitride spacer.

그리고, 상기 패드산화막 상에 증착되는 폴리실리콘막은 도핑되지 않은 폴리실리콘막을 사용하는 것이 바람직하고, 상기 나이트라이드막은 습식식각(Wetch Etch)에 의하여 형성되어진다.The polysilicon layer deposited on the pad oxide layer is preferably a non-doped polysilicon layer, and the nitride layer is formed by wet etching.

또한, 상기 인터케넥션라인은 티타늄(Ti)을 증착하여 티타늄실리사이드화시킨 Ti- Si2 막으로 이루어지게 된다.In addition, the interconnection line is made of a Ti-Si 2 film formed by depositing titanium (Ti) and titanium silicide.

이하, 첨부한 도면에 의거하여 본 발명에 따른 모스페트트랜지스터의 금속배선 형성방법에 대하여 상세히 설명한다.Hereinafter, a method of forming metal wirings of a MOSFET transistor according to the present invention will be described in detail with reference to the accompanying drawings.

도 2 및 도 3에 도시된 바와 같이, 반도체기판(10)의 필드산화막(20)과 게이트전극(40) 상에 패드산화막(30)과 폴리실리콘막(50)을 순차적으로 증착하고서 블랭킹 식각(Blancking Etch)을 통하여 게이트전극(40) 외측에 스페이서(60)를 형성하는 상태를 보이고 있다.As shown in FIGS. 2 and 3, the pad oxide layer 30 and the polysilicon layer 50 are sequentially deposited on the field oxide layer 20 and the gate electrode 40 of the semiconductor substrate 10, thereby blanking etching ( The spacer 60 is formed outside the gate electrode 40 through the Blancing Etch.

이때, 상기 패드산화막(30) 상에 증착되는 폴리실리콘막(50)은 도핑되지 않은(Undopped) 폴리실리콘막이고, 상기 나이트라이드막(70)은 습식식각에 의하여 형성된다.In this case, the polysilicon layer 50 deposited on the pad oxide layer 30 is an undoped polysilicon layer, and the nitride layer 70 is formed by wet etching.

그리고, 도 4 및 도 5는 상기 단계 후에 상부면에 나이트라이드막(70)을 증착하고, 이 나이트라이드막(70)상에서 비활성영역에 감광막(80)을 증착하여, 식각으로 통하여 활성영역의 나이트라이드막(70)을 식각하고 감광막(80)을 제거하는 상태를 보이고 잇다.4 and 5, after the step, the nitride film 70 is deposited on the upper surface, and the photoresist film 80 is deposited on the inactive area on the nitride film 70, and the nitride of the active area is etched through etching. The ride film 70 is etched and the photoresist film 80 is removed.

또한, 도 6은 상기 단계 후에 블랭킹 식각을 통하여 활성영역의 게이트전극(40)의 스페이서(60) 외측에 나이트라이드스페이서(75)를 형성하는 상태를 보이고 있다.6 shows a state in which the nitride spacer 75 is formed outside the spacer 60 of the gate electrode 40 of the active region through blanking etching after the step.

그리고, 도 7은 상기 단계 후에 나이트라이드 스페이서(75)를 제외한 게이트전극(40)과 활성영역에 티타늄층을 증착하여 실리콘과 반응하여 Ti- Si2 막으로 된 금속배선라인(90)을 형성하여 게이트전극(40)과 반도체기판(10)의 활성영역과 연결되는 배선으로 사용하는 상태를 보이고 있다.In FIG. 7, a titanium layer is deposited on the gate electrode 40 and the active region except for the nitride spacer 75 to react with silicon to form a metal wiring line 90 made of a Ti—Si 2 film. A state in which the gate electrode 40 and the semiconductor substrate 10 are connected to the active region is shown.

따라서, 상기한 바와 같이 본 발명에 따른 모스페트트랜지스터의 금속배선 형성방법을 이용하게 되면, 반도체기판에서 두 개의 필드산화막과 이 필드산화막 사이에 형성되는 게이트전극 상에 나이트라이드막을 증착하고, 감광막을 이용하여 나이트라이드막을 식각하여서 활성영역에는 나이트라이드막을 모두 식각하여 스페이서를 노출하고, 비 활성영역에 있는 스페이서의 외측에는 나이트라이드막을 증착하여서 게이트전극과 활성 영역을 티타늄실리사이드화시킨 금속배선라인을 형성하므로 신호의 전송선로를 줄여주어 밀도 높은 회로의 설계를 가능하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the method for forming the metal wiring of the MOSFET transistor according to the present invention is used, a nitride film is deposited on two field oxide films and a gate electrode formed between the field oxide films on a semiconductor substrate, and the photoresist film is formed. The nitride layer is etched using the nitride layer to etch all of the nitride layer in the active region to expose the spacers, and a nitride layer is deposited on the outer side of the spacer in the non-active region to form a metal wiring line in which the gate electrode and the active region are titanium silicided. Therefore, it is a very useful and effective invention that reduces the transmission line of the signal and enables the design of the dense circuit.

도 1은 종래의 일반적인 금속배선 연결구조에 대하여 개략적으로 보인 도면. 1 is a view schematically showing a conventional general metal wiring connection structure.

도 2 내지 도 7은 본 발명에 따른 금속배선 형성방법을 순차적으로 보인 도면.2 to 7 are views sequentially showing a metal wiring forming method according to the present invention.

-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing

10 : 반도체기판 20 : 필드산화막10: semiconductor substrate 20: field oxide film

30 : 패드산화막 40 : 게이트전극30: pad oxide film 40: gate electrode

50 : 폴리실리콘막 60 : 스페이서50 polysilicon film 60 spacer

70 : 나이트라이드막 75 : 니이트라이드 스페이서70: nitride film 75: nitride nitride spacer

80 : 감광막 90 : 금속배선라인80: photosensitive film 90: metal wiring line

Claims (2)

필드산화막과 게이트전극이 형성된 반도체기판 상에 패드산화막과 도핑되지 않은 폴리실리콘막을 순차적으로 증착한 후 블랭킹 식각을 통하여 게이트전극 양측벽에 스페이서를 형성하는 단계;Sequentially depositing a pad oxide film and an undoped polysilicon film on the semiconductor substrate on which the field oxide film and the gate electrode are formed, and forming spacers on both sidewalls of the gate electrode through blanking etching; 상기 단계 후에 상부면에 나이트라이드막을 형성하고, 이 나이트라이드막 상의 비활성영역에 감광막을 증착하여, 식각을 통하여 활성영역의 나이트라이드막을 식각하고 감광막을 제거하는 단계;Forming a nitride film on the upper surface after the step, and depositing a photoresist film on the inactive region on the nitride film to etch the nitride film of the active region by etching and to remove the photoresist film; 상기 단계 후에 블랭킹 식각을 통하여 활성영역의 게이트전극의 스페이서 외측에 나이트라이드 스페이서를 형성하는 단계;Forming a nitride spacer outside the spacer of the gate electrode of the active region through blanking etching after the step; 상기 단계 후에 나이트라이드 스페이서를 제외한 게이트 전극과 활성영역에 Ti층을 증착하여 티타늄실리사이드층을 형성하는 단계로 이루어진 것을 특징으로 하는 모스페트 트랜지스터의 금속 배선 형성 방법.And forming a titanium silicide layer by depositing a Ti layer on the gate electrode and the active region excluding the nitride spacer after the step of forming a titanium silicide layer. 제 1 항에 있어서, The method of claim 1, 상기 나이트라이드막은 습식식각에 의하여 형성되는 것을 특징으로 하는 모스페트 트랜지스터의 금속 배선 형성 방법.And the nitride layer is formed by wet etching.
KR1019970077353A 1997-12-29 1997-12-29 Metal wiring formation method of MOS PET transistor KR100511090B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05304108A (en) * 1992-04-24 1993-11-16 Sony Corp Semiconductor device and fabrication thereof
JPH07106570A (en) * 1993-10-05 1995-04-21 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH09293865A (en) * 1996-04-26 1997-11-11 Ricoh Co Ltd Semiconductor device and manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05304108A (en) * 1992-04-24 1993-11-16 Sony Corp Semiconductor device and fabrication thereof
JPH07106570A (en) * 1993-10-05 1995-04-21 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH09293865A (en) * 1996-04-26 1997-11-11 Ricoh Co Ltd Semiconductor device and manufacture thereof

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