KR100230731B1 - Contact structure of semiconductor device and process for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact structure of a semiconductor device for simultaneously contacting a gate electrode and any one of a source or a drain region, and a manufacturing method thereof.

A method of manufacturing a contact structure of a semiconductor device according to the present invention comprises the steps of: providing a semiconductor substrate of a first conductivity type with a field oxide film; Forming a gate electrode on the field oxide layer; Forming first and second junction regions of a second conductivity type on both sides of the gate electrode; Forming an interlayer insulating film on the semiconductor substrate; Etching the interlayer insulating layer to form a first contact hole through which the gate electrode and the first junction region are simultaneously exposed, and a second contact hole through which the second junction region is exposed; Forming a first plug in contact with the gate electrode and the first junction region in the first and second contact holes, and a second plug in contact with the second junction region; And forming a metal wire to be connected to the first plug.

Description

A contact structure of a semiconductor device and a method of manufacturing the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact structure of a semiconductor device and a method of manufacturing the same, and more particularly, to a contact structure of a semiconductor device and a method of manufacturing the same, which simultaneously contact any one of a source electrode and a drain region.

In general, in forming a specific circuit using a plurality of MOS transistors, a MOS transistor used in a device such as a field transistor used in a specific transistor, for example, an antistatic circuit, has a gate electrode, a source region or a drain region. At the same time, a contact structure is required.

Here, a semiconductor device having a structure in which a conventional gate electrode and a source region or a drain region are contacted at the same time, as shown in FIG. 1, may be applied to a known LOCOS oxidation method in a predetermined portion of the semiconductor substrate 1. Thus, the field oxide film 2 is formed. At this time, the field oxide film 2A serves to separate the device from the device, and the field oxide film 2B serves as a gate insulating film of the field transistor. Thereafter, the gate oxide film 3 and the polysilicon film are sequentially stacked on the resultant, and then patterned to exist on the field oxide film 2B, thereby forming the gate electrode 4.

Subsequently, impurities opposite to the substrate are ion-implanted into the semiconductor substrates on both sides of the gate electrode 4 to form source / drain regions 5A and 5B. Then, an interlayer insulating film 6 is deposited on the resultant to a predetermined thickness and etched to expose the gate electrode 4, the source region 5A and the drain region 5B. At this time, the gate electrode 4 and the source region 5A are simultaneously exposed.

Then, metal wires 7A, 7B, and 7C are formed to contact each exposed portion.

However, as described above, the metal wiring structure in which the gate electrode and the source region are in contact at the same time, as the semiconductor device becomes highly integrated, the pitch of the wiring increases, which causes the wiring density to increase.

For this reason, the problem that the metal wiring reliability of a semiconductor element falls is produced.

Accordingly, an object of the present invention is to provide a contact structure of a semiconductor device with improved wiring density applicable to a highly integrated semiconductor device.

Moreover, it aims at providing the manufacturing method of the contact structure of a semiconductor device as mentioned above.

1 is a cross-sectional view showing a contact structure of a conventional semiconductor device.

2A and 2B are cross-sectional views illustrating a contact structure of a semiconductor device and a method of manufacturing the same according to the present invention.

* Explanation of symbols for main parts of the drawings

11: semiconductor substrate 12A, 12B: field oxide film

13 gate oxide film 14 gate electrode

15A: source region 15B: drain region

16: interlayer insulating film 17A, 17B: plug

18: metal wiring

In order to achieve the above object of the present invention, the semiconductor contact structure of the present invention, the field oxide film formed on a predetermined portion on the semiconductor substrate of the first conductivity type; A gate electrode formed on the field oxide film; First and second junction regions of a second conductivity type formed in the semiconductor substrate on both sides of the gate electrode; An interlayer insulating film having a first contact hole exposing the gate and the first junction region to an illustration and a second contact hole exposing the second junction region; A first plug connected to the gate and the first junction region and formed in a first contact hole; A second plug connected to the second junction region and formed in a second contact hole; And a metal wire in contact with the second plug.

In addition, a method of manufacturing a contact structure of a semiconductor device according to the present invention comprises the steps of: providing a semiconductor substrate of a first conductivity type with a field oxide film; Forming a gate electrode on the field oxide layer; Forming first and second junction regions of a second conductivity type on both sides of the gate electrode; Forming an interlayer insulating film on the semiconductor substrate; Etching the interlayer insulating layer to form a first contact hole through which the gate electrode and the first junction region are simultaneously exposed, and a second contact hole through which the second junction region is exposed; Forming a first plug in contact with the gate electrode and the first junction region in the first and second contact holes, and a second plug in contact with the second junction region; And forming a metal wire to be connected to the second plug.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are cross-sectional views illustrating a contact structure of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention, wherein reference numeral 11 denotes a semiconductor substrate, 12A and 12B denote a field oxide film, and a 13 gate oxide film Indicates. In addition, 14 represents a gate electrode, 15A represents a source region, 15B represents a drain region, 16 represents an interlayer insulating film, 17 represents a plug, and 18 represents a metal wiring.

First, referring to FIG. 2A, field oxide films 12A and 12B by a known LOCOS oxidation method are applied to a predetermined portion of a semiconductor substrate 11, for example, a silicon substrate in which impurities of a first conductivity type are ion-implanted. Is formed. At this time, the field oxide film 12A serves to separate the device from the device, and the field oxide film 12B serves as a gate insulating film of the field transistor. Thereafter, the gate oxide film 13 and the polysilicon film are sequentially stacked on the resultant, and then patterned to exist on the field oxide film 12B, thereby forming the gate electrode 14. Here, the gate electrode 14 is formed to partially extend to the source region.

Next, the second conductivity type impurities are ion-implanted into the semiconductor substrate 11 on both sides of the gate electrode 14 to form source / drain regions 15A and 15B, and source / drain regions 15A and 15B. An interlayer insulating film 16 is formed on the formed semiconductor substrate 11. In this case, as the interlayer insulating film 16, a BPSG film or a PSG film having excellent interlayer planarization characteristics may be used, and an insulating film known as an interlayer insulating film may be deposited, and a separate planarization process may be performed by a chemical mechanical polishing method. have.

Then, a contact hole (not shown) is formed by etching the interlayer insulating film 16 so that the gate electrode 14, the source region 15A, and the drain region 15B are exposed. At this time, since the gate electrode 14 and the source region are commonly connected to 15A, they are etched to be simultaneously exposed.

Thereafter, tungsten plugs 17A and 17B are formed in each contact hole to have the same height as the interlayer insulating film 16. At this time, the tungsten plugs 17A and 17B may be formed by a known selective deposition method of a tungsten film or a tungsten film deposition, followed by an etch back process using an interlayer insulating film as an etch stop.

For example, referring to FIG. 2B, a metal wiring film is deposited on the semiconductor substrate 11 on which the tungsten plugs 17A and 17B are formed, and a tungsten plug simultaneously connected to the gate electrode 14 and the source region 15A is formed. Patterned so as to be in contact with the other plug region except for the above, metal wirings 18A and 18B are formed. At this time, the metal wiring film is made of aluminum or barrier metal, for example, an aluminum metal film provided with a Ti film or a laminated film of Ti / TiN.

Here, not forming a metal wiring on the tungsten plug 17A simultaneously connected to the gate electrode 14 and the source region 15A is tungsten simultaneously connected to the gate electrode 14 and the source region 15A. As the plug 17A alone serves as a metal wiring sufficiently and does not form a metal wiring thereon, the pitch between the wirings is reduced and the metal wiring density is reduced.

The present invention is not limited to the above embodiment.

For example, in the present embodiment, for example, the gate electrode and the source region are described as being commonly connected, but the same applies to the common connection between the gate electrode and the drain electrode.

In addition, although the tungsten plug was used in this invention, it is also included in this invention also using the other conductive material which is excellent in other conductive characteristics and the embedding characteristic.

As described in detail above, in the metal wiring process of the MOS transistor in which the gate electrode and the source region are simultaneously contacted, a tungsten plug is formed in a portion where the gate electrode and the source region are commonly connected, thereby minimizing the pitch between the metal wirings, Reduce the wiring density of the semiconductor device.

Therefore, the present invention can be applied to highly integrated semiconductor devices.

Claims (21)

A field oxide film formed on a predetermined portion on the semiconductor substrate of the first conductivity type; A gate electrode formed on the field oxide film; First and second junction regions of a second conductivity type formed in the semiconductor substrate on both sides of the gate electrode; An interlayer insulating film having a first contact hole exposing the gate electrode and the first junction region at the same time and a second contact hole exposing the second junction region; A first plug connected to the gate electrode and the first junction region and formed in a first contact hole; A second plug connected to the second junction region and formed in a second contact hole; And a metal wire in contact with the second plug. The contact structure of claim 1, wherein the first and second plugs are tungsten plugs. The contact structure of a semiconductor device according to claim 1 or 2, wherein the first plug serves as a metal wiring. The contact structure of claim 1, wherein the field oxide film serves as a gate insulating film. 2. The contact structure of claim 1, wherein the first junction region is a source region and the second junction region is a drain region. The contact structure of claim 1, wherein the first junction region is a drain region and the second junction region is a source region. The contact structure of claim 1, wherein the first conductivity type is P type and the second conductivity type is N type. The contact structure of claim 1, wherein the first conductivity type is N type and the second conductivity type is P type. The contact structure of a semiconductor device according to claim 1, wherein said interlayer insulating film is a planarizing insulating film. Providing a semiconductor substrate of a first conductivity type with a field oxide film; Forming a gate electrode on the field oxide layer; Forming first and second junction regions of a second conductivity type on both sides of the gate electrode; Forming an interlayer insulating film on the semiconductor substrate; Etching the interlayer insulating layer to form a first contact hole through which the gate electrode and the first junction region are simultaneously exposed, and a second contact hole through which the second junction region is exposed; Forming a first plug in contact with the gate electrode and the first junction region in the first and second contact holes, and a second plug in contact with the second junction region; And forming a metal wiring so as to be connected with the second plug. The method of manufacturing a contact structure of a semiconductor device according to claim 10, wherein the interlayer insulating film is formed of a BPSG film and one film selected from a PSG film. The method of claim 10, wherein forming the interlayer insulating film comprises: depositing an insulating oxide film over the resultant; Chemical mechanical polishing the insulating oxide film. The method of claim 10, wherein the first and second plugs are tungsten plugs. 15. The method of claim 13, wherein the tungsten plug is formed in the first and second contact holes by selective deposition. The method of claim 13, wherein the forming of the tungsten plug comprises: forming a tungsten film to embed the lower structure on the semiconductor substrate; And etching the tungsten film to expose the surface of the interlayer insulating film. The method of manufacturing a contact structure of a semiconductor device according to claim 10, wherein the first plug serves as a metal wiring. The method of manufacturing a contact structure of a semiconductor device according to claim 10, wherein said field oxide film serves as a gate insulating film. The method of manufacturing a contact structure of a semiconductor device according to claim 10, wherein the first junction region is a source region and the second junction region is a drain region. The method of manufacturing a contact structure of a semiconductor device according to claim 10, wherein the first junction region is a drain region and the second junction region is a source region. The method of manufacturing a contact structure of a semiconductor device according to claim 10, wherein the first conductivity type is P type and the second conductivity type is N type. The method of manufacturing a contact structure of a semiconductor device according to claim 10, wherein the first conductivity type is N type and the second conductivity type is P type.