KR100475715B1 - MML Semiconductor Device Manufacturing Method - Google Patents
MML Semiconductor Device Manufacturing Method Download PDFInfo
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- KR100475715B1 KR100475715B1 KR10-1998-0026241A KR19980026241A KR100475715B1 KR 100475715 B1 KR100475715 B1 KR 100475715B1 KR 19980026241 A KR19980026241 A KR 19980026241A KR 100475715 B1 KR100475715 B1 KR 100475715B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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Abstract
본 발명은 MML반도체소자에 관한 것으로서, 특히, 로직게이트전극의 소오스/드레인영역에 실리사이드층을 형성하는 단계와; 상기 디램영역 및 로직영역의 전면에 일정 두께로 제1인터폴리산화막을 적층하는 단계와; 상기 단계 후에 상기 제1인터폴리산화막 상에 로직영역으로 제1콘택부위를 갖는 제1감광막을 적층한 후에 식각으로 로직게이트전극의 실리사이드층으로 개방되는 제1콘택홀을 형성하는 단계와; 상기 제1콘택홀에 금속층을 적층한 후 식각을 하여 하부금속배선을 형성하는 단계와; 상기 결과물의 전영역에 제2인터폴리산화막을 적층한 후 그 위에 디램영역과 로직영역의 하부금속배선의 위치에 제2콘택부위를 갖는 제2감광막을 적층하는 단계와; 상기 제2콘택부위를 통하여 하부의 산화막을 식각하여 디램콘택홀 및 제2로직콘택홀을 형성하는 단계와; 상기 디램콘택홀 및 제2로직콘택홀을 통하여 금속층을 적층한 후 식각으로 디램금속배선 및 상기 하부금속배선에 연결되는 로직금속배선을 형성하는 단계로 이루어진 MML반도체소자 제조방법인 바, 디램영역 및 로직영역에 콘택홀을 형성하여 제2단계로 금속배선을 형성하므로 로직영역의 실리사이드층의 손상을 방지하고 금속배선의 형성을 정확하고, 용이하게 하도록 하는 매우 유용하고 효과적인 발명이다.The present invention relates to an MML semiconductor device, particularly comprising forming a silicide layer in a source / drain region of a logic gate electrode; Stacking a first interpoly oxide film on the entire surface of the DRAM region and the logic region with a predetermined thickness; After the step of forming a first contact hole on the first interpoly oxide film having a first photoresist film having a first contact portion as a logic region and then etched to open the silicide layer of the logic gate electrode; Stacking a metal layer in the first contact hole and etching to form a lower metal wiring; Stacking a second interpoly oxide film over the entire region of the resultant, and then laminating a second photoresist film having a second contact portion at a position of a DRAM region and a lower metal wiring of a logic region thereon; Etching a lower oxide layer through the second contact portion to form a DRAM contact hole and a second logic contact hole; A method of manufacturing an MML semiconductor device comprising: forming a metal layer through the DRAM contact hole and the second logic contact hole and forming a logic metal wiring connected to the DRAM metal wiring and the lower metal wiring by etching. By forming a contact hole in the logic region to form a metal wiring in the second step, it is a very useful and effective invention to prevent damage to the silicide layer of the logic region and to accurately and easily form the metal wiring.
Description
본 발명은 MML반도체소자에 관한 것으로서, 특히, 로직영역의 트랜지스터를 개방시켜 실리사이드층을 형성한 후 감광막을 이용하여 로직영역에 제1콘택홀을 이용하여 하부금속배선을 형성하고, 다시 산화막을 적층하여 디램영역 및 로직영역에 콘택홀을 형성하여 그 내부에 금속배선을 적층하므로 로직영역의 실리사이드층의 손상을 방지하고 금속배선의 형성을 용이하도록 하는 MML반도체소자 제조방법에 관한 것이다. The present invention relates to an MML semiconductor device, and more particularly, to form a silicide layer by opening a transistor in a logic region, and then forming a lower metal wiring by using a first contact hole in a logic region using a photosensitive film, and then stacking an oxide layer. The present invention relates to an MML semiconductor device manufacturing method for forming a contact hole in a DRAM region and a logic region and stacking metal interconnects therein, thereby preventing damage to the silicide layer of the logic region and facilitating the formation of the metal interconnection.
일반적으로, 메모리(Memory)와 로직(Logic)이 단일칩에 형성되는 복합반도체(MML: Merged Memory Logic)가 최근에 들어 많은 관심을 보이면서 점차적으로 많이 사용하는 추세에 있으며, 이 MML반도체장치는 로직과 메모리를 한 칩에서 단일한 공정으로 제조하는 것이 가능하므로 특별한 설계의 변경 없이도 기존의 칩들에 비하여 고속으로 동작하고, 저전력으로 사용하는 것이 가능한 장점을 지닌다.In general, a mixed semiconductor (MML: Merged Memory Logic), in which memory and logic are formed on a single chip, has been increasingly used in recent years, and this MML semiconductor device has been increasingly used. Since it is possible to manufacture a single process in one chip and memory, it has the advantage that it can operate at a higher speed and use at lower power than existing chips without any special design change.
그 반면에, 메모리제품의 제조공정과 로직제품의 제조공정이 한 칩에서 동시에 제조되므로 단위칩의 크기가 커지며, 이에 따라 제조공정을 진행하기에 많은 어려움을 요하는 단점도 지니고 있을 뿐만아니라 메모리에서의 트랜지스터는 높은 전류 구동력을 요하는 것보다 오히려 누설전류를 방지하는 것에 비중을 두고 있으나 로직제품은 높은 전류구동능력을 요구하는 등 양자의 특성을 모두 갖추어서 한칩으로 제조하여야 한다. On the other hand, since the manufacturing process of the memory product and the manufacturing process of the logic product are manufactured on the same chip at the same time, the size of the unit chip is increased, and therefore, it has a disadvantage that requires a lot of difficulty to proceed with the manufacturing process. Transistors have more emphasis on preventing leakage current than requiring high current driving force, but logic products must be manufactured on one chip with both characteristics such as high current driving capability.
이와 같이, 종래에는 반도체기판에서 메모리영역과 로직영역에 필드산화막과 트랜지스터의 게이트전극을 동시에 형성하여 게이트전극의 측면부분에 스페이서막을 적층하고, 다시 활성영역에 이온을 주입하여 소오스/드레인을 형성한 후 그 공정 후에 메모리영역의 필드산화막 상에 커패시터(Capacitor)를 800℃에 이르는 고온 공정으로 형성하였으며, 연속하여 로직영역의 트랜지스터와 메모리영역의 트랜지스터 및 커패시터 상에 산화막으로 된 절연층 및 금속배선층을 다층으로 적층하여 이후 공정을 진행하게 된다. As described above, in the semiconductor substrate, a field oxide film and a gate electrode of a transistor are simultaneously formed in a memory region and a logic region, a spacer film is stacked on a side portion of the gate electrode, and ions are implanted into an active region to form a source / drain. After the process, a capacitor was formed on the field oxide film of the memory region by a high temperature process of 800 ° C., and the insulating layer and the metal wiring layer of the oxide film were formed on the transistor of the logic region and the transistor and capacitor of the memory region. Lamination is carried out in a multilayer process.
그런데, 상기한 바와 같이, 메모리영역의 트랜지스터는 누설전류방지에 비중을 두는 반면에 로직영역의 트랜지스터의 경우에는 높은 전류구동능력을 가지는 것에 비중을 두게 되는 것으로서, 종래에는 로직영역 및 메모리영역의 트랜지스터를 모두 형성한 후에 메모리영역에서 고온(800℃정도)의 커패시터를 제조하는 공정을 진행하므로 로직영역에서 이미 제조된 트랜지스터에, 특히, 트랜지스터의 소오스/드레인영역 및 활성영역에 형성되는 실리사이드층에 중대한 영향을 가하여 로직영역의 트랜지스터의 전류구동능력을 저하시켜 소자의 성능저하시키는 문제점을 지니고 있었다.By the way, as described above, the transistors in the memory region place emphasis on the prevention of leakage current, while the transistors in the logic region place emphasis on having a high current driving capability. After the formation of all, the process of manufacturing a high temperature capacitor (about 800 ℃) in the memory region is performed, which is important for transistors already manufactured in the logic region, particularly for silicide layers formed in the source / drain and active regions of the transistor. In this case, the current driving ability of the transistor in the logic region is lowered, thereby degrading the performance of the device.
또한, 메모리역할을 하는 디램(DRAM)영역은 트랜지스터와 커패시터가 형성되어지고, 로직(Logic)영역은 트랜지스터만이 형성되므로 양자를 한칩에 형성하여 절연막을 적층하게 되면 전적으로 높이가 높아질 뿐만아니라 디램영역의 커패시터 높이로 인하여 그 후에 진행되는 콘택을 형성하는 공정이 High Aspect Ratio로 인하여 상당한 Deep Contact이 형성되어지므로 정확한 콘택을 형성하지 못하는 문제점을 지니고 있었다. In addition, since a transistor and a capacitor are formed in the DRAM area, which serves as a memory, and only a transistor is formed in the logic area, only a transistor is formed on the same chip to increase the height of the DRAM area. Due to the height of the capacitor, the process of forming a subsequent contact has a problem in that an accurate contact cannot be formed because a considerable deep contact is formed due to a high aspect ratio.
본 발명의 목적은 디램영역에 커패시터를 형성한 후 디램영역 및 로직영역에 적층되어 있는 절연막을 식각하여서 로직영역의 트랜지스터를 개방시켜 실리사이드층을 형성한 후 감광막을 이용하여 로직영역에 제1콘택홀을 이용하여 하부금소구배선을 형성하고, 다시 산화막을 적층하여 디램영역 및 로직영역에 콘택홀을 형성하여 그 내부에 금속배선을 적층하므로 로직영역의 실리사이드층의 손상을 방지하고 금속배선의 형성을 용이하게 하는 것이 목적이다.An object of the present invention is to form a silicide layer by opening a transistor in a logic region by forming a capacitor in the DRAM region and then etching the insulating film stacked in the DRAM region and the logic region to form a silicide layer, and then using the photosensitive film to form a first contact hole in the logic region. The lower metal wiring wiring is formed by using, and the oxide film is stacked again to form contact holes in the DRAM region and the logic region, and the metal wiring is laminated therein, thereby preventing damage to the silicide layer of the logic region and forming the metal wiring. The purpose is to facilitate.
이러한 목적은 디램영역에 디램게이트전극 및 커패시터를 형성하고, 로직영역에는 로직게이트전극을 형성한 후에 전 영역에 절연막을 적층한 단계와; 상기 절연막중에서 로직영역의 부분을 제거하여 로직게이트전극을 개방시킨 후에 소오스/드레인영역에 실리사이드층을 형성하는 단계와; 상기 디램영역 및 로직영역의 전면에 일정 두께로 제1인터폴리산화막을 적층하는 단계와; 상기 단계 후에 상기 제1인터폴리산화막 상에 로직영역으로 제1콘택부위를 갖는 제1감광막을 적층한 후에 식각으로 로직게이트전극의 실리사이드층으로 개방되는 제1콘택홀을 형성하는 단계와; 상기 제1콘택홀에 금속층을 적층한 후 식각을 하여 하부금속배선을 형성하는 단계와; 상기 결과물의 전영역에 제2인터폴리산화막을 적층한 후 그 위에 디램영역과 로직영역의 하부금속배선의 위치에 제2콘택부위를 갖는 제2감광막을 적층하는 단계와; 상기 제2콘택부위를 통하여 하부의 산화막을 식각하여 디램콘택홀 및 제2로직콘택홀을 형성하는 단계와; 상기 디램콘택홀 및 제2로직콘택홀을 통하여 금속층을 적층한 후 식각으로 디램금속배선 및 상기 하부금속배선에 연결되는 로직금속배선을 형성하는 단계로 이루어진 MML반도체소자 제조방법을 제공함으로써 달성된다. 그리고, 상기 제2인터폴리산화막을 증착한 후 평탄화시키는 공정을 더 포함하게 되고, 상기 제1인터폴리산화막의 두께는 1㎛이하로 하며, 상기 하부금속배선, 디램금속배선 및 로직금속배선은 금속층을 CVD법으로 증착한 후에 에치빽공정으로 형성한다, 또한, 상기 절연막은 습식식각 또는 건식식각으로 로직게이트전극을 노출시키도록 하는 MML반도체소자를 제공함으로써 달성된다.The purpose of the present invention is to form a DRAM gate electrode and a capacitor in the DRAM region, and a logic gate electrode in the logic region, and then, depositing an insulating film in all regions; Removing a portion of the logic region from the insulating film to open the logic gate electrode, and then forming a silicide layer in the source / drain region; Stacking a first interpoly oxide film on the entire surface of the DRAM region and the logic region with a predetermined thickness; After the step of forming a first contact hole on the first interpoly oxide film having a first photoresist film having a first contact portion as a logic region and then etched to open the silicide layer of the logic gate electrode; Stacking a metal layer in the first contact hole and etching to form a lower metal wiring; Stacking a second interpoly oxide film over the entire region of the resultant, and then laminating a second photoresist film having a second contact portion at a position of a DRAM region and a lower metal wiring of a logic region thereon; Etching a lower oxide layer through the second contact portion to form a DRAM contact hole and a second logic contact hole; It is achieved by providing a method of manufacturing an MML semiconductor device comprising the step of forming a logic metal wiring connected to the DRAM metal wiring and the lower metal wiring by laminating a metal layer through the DRAM contact hole and the second logic contact hole. The method may further include a process of depositing the second interpoly oxide film and then planarizing the thickness, wherein the thickness of the first interpoly oxide film is 1 μm or less, and the lower metal wiring, the DRAM metal wiring, and the logic metal wiring are metal layers. Is formed by an etch back process after deposition by CVD method. The insulating film is also achieved by providing an MML semiconductor device for exposing a logic gate electrode by wet etching or dry etching.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 1은 디램영역(a)에 디램게이트전극(20) 및 커패시터(30)를 형성하고, 로직영역(b)에는 로직게이트전극(25)을 형성한 후에 전 영역에 절연막(35)을 적층한 상태를 도시하고 있다.1 shows a DRAM gate electrode 20 and a capacitor 30 formed in a DRAM region a, and a logic gate electrode 25 formed in a logic region b, and then an insulating film 35 is stacked on all regions. The state is shown.
도 2는 상기 절연막(35) 가운데에서 로직영역(b)의 부분을 습식식각 혹은 건식식각으로 제거하여 로직게이트전극(25)을 개방시킨 후에 소오스/드레인영역에 실리사이드층(40)을 형성하는 상태를 도시하고 있다.2 is a state in which the silicide layer 40 is formed in the source / drain region after opening the logic gate electrode 25 by removing a portion of the logic region b by wet etching or dry etching in the middle of the insulating layer 35. It is shown.
그리고, 도 3은 상기 디램영역(a) 및 로직영역(b)의 전면에 일정 두께, 특히, 1㎛이하의 두께로 제1인터폴리산화막(45)을 적층하는 상태를 도시하고 있다.3 illustrates a state in which the first interpoly oxide film 45 is laminated on the entire surface of the DRAM region a and the logic region b, in particular, having a thickness of 1 μm or less.
도 4는 상기 단계 후에 상기 제1인터폴리산화막(45) 상에 로직영역(b)으로 제1콘택부위(55)를 갖는 제1감광막(50)을 적층한 상태를 도시하고 있다.FIG. 4 illustrates a state in which the first photoresist film 50 having the first contact portion 55 is stacked in the logic region b on the first interpoly oxide film 45 after the step.
그리고, 도 5는 상기 단계 후에 제1콘택부위(55)를 통하여 식각으로 로직게이트전극(25)의 실리사이드층(40)으로 개방되는 제1콘택홀(47)을 형성하는 상태를 도시하고 있다.FIG. 5 illustrates a state in which a first contact hole 47 is opened to the silicide layer 40 of the logic gate electrode 25 by etching through the first contact portion 55 after the step.
도 6(a)는 상기 제1콘택홀(47)에 금속층을 적층한 후 식각하여 하부금속배선(60)을 형성하는 상태를 도시하고 있다.FIG. 6A illustrates a state in which a lower metal wiring 60 is formed by stacking and etching a metal layer in the first contact hole 47.
도 7(a)은 상기 결과물의 전영역에 제2인터폴리산화막(65)을 적층한 후 평탄화시키고, 그 위에 디램영역(a)과 로직영역(b)의 하부금속배선(60)의 위치에 제2콘택부위(75)를 갖는 제2감광막(70)을 적층하는 상태를 도시하고 있다.FIG. 7A illustrates the planarization process of stacking the second interpoly oxide film 65 over the entire region of the resultant material, and planarizing the second interpoly oxide film 65 on the lower metal wiring 60 of the DRAM region a and the logic region b. The state in which the second photosensitive film 70 having the second contact portion 75 is laminated is shown.
도 8(a)은 상기 제2콘택부위(75)를 통하여 하부의 산화막을 식각하여 디램콘택홀(67) 및 제2로직콘택홀(69)를 형성하는 상태를 도시하고 있다.FIG. 8A illustrates a state in which a DRAM contact hole 67 and a second logic contact hole 69 are formed by etching a lower oxide layer through the second contact portion 75.
도 9(a)는 상기 디램콘택홀(67) 및 제2로직콘택홀(69)을 통하여 금속층을 적층한 후 식각으로 디램금속배선(80) 및 상기 하부금속배선(60)에 연결되는 로직금속배선(85)을 형성하는 상태를 도시하고 있다.9A illustrates a logic metal connected to the DRAM metal wiring 80 and the lower metal wiring 60 by etching after stacking a metal layer through the DRAM contact hole 67 and the second logic contact hole 69. The state which forms the wiring 85 is shown.
그리고, 상기 하부금속배선(60), 디램금속배선(80) 및 로직금속배선(85)은 금속층을 CVD(Chemical Vapor Deposition)법으로 증착한 후에 에치빽(Etch Back)공정으로 형성하도록 한다.The lower metal interconnection 60, the DRAM metal interconnection 80, and the logic metal interconnection 85 may be formed by an etch back process after depositing a metal layer by a chemical vapor deposition (CVD) method.
그리고, 첨부한 도면을 참조하여 본 발명의 바람직한 다른 실시예에 대해 상세하게 설명하고자 한다.And, with reference to the accompanying drawings will be described in detail for another preferred embodiment of the present invention.
한편, 다른 실시예의 경우에도 도 1 내지 도 5의 공정까지는 동일하므로 설명을 생략하도록 하고, 도 6(b) 내지 도 9(b)의 경우를 살펴 보면, 제1콘택홀(47)내에 형성되는 하부금속배선(60')이 상부로 노출되는 것 없이 모두 식각되도록 하고, 그 위에 제2인터폴리산화막(65')을 적층한 후에 제2감광막(70')의 제2콘택부위(75')를 통하여 식각을 하여 디램콘택홀(67') 및 제2로직콘택홀(69')을 형성하도록 하고, 금속층 적층하여 식각을 통하여 디램금속배선(80') 및 로직금속배선(85')을 형성하는 상태를 도시하고 있다.Meanwhile, in the case of other embodiments, the same steps are applied to the processes of FIGS. 1 to 5, and thus description thereof will be omitted. Referring to the cases of FIGS. 6 (b) to 9 (b), the first contact holes 47 are formed in the first contact hole 47. The lower metal wiring 60 'is etched without being exposed to the upper portion, and after the second interpoly oxide film 65' is stacked thereon, the second contact portion 75 'of the second photoresist film 70'. Etching to form the DRAM contact hole 67 'and the second logic contact hole 69', and laminating a metal layer to form the DRAM metal wiring 80 'and the logic metal wiring 85' through etching. The state of doing is shown.
상기한 바와 같이 본 발명에 따른 MML반도체소자 제조방법을 이용하게 되면, 디램영역에 고온 공정으로 커패시터를 형성한 후 디램영역 및 로직영역에 적층되어 있는 절연막을 식각하여서 로직영역의 트랜지스터를 개방시켜 실리사이드층을 형성하므로 디램영역의 커패시터 고온 열공정으로 인한 로직영역의 실리사이드층의 손상을 방지할 뿐만아니라 감광막을 이용하여 로직영역에 제1콘택홀을 이용하여 하부금속배선을 1단계로 형성하고, 다시 산화막을 적층하여 디램영역 및 로직영역에 콘택홀을 형성하여 제2단계로 그 내부에 금속배선을 적층하므로 금속배선의 형성을 정확하고, 용이하게 하도록 하는 매우 유용하고 효과적인 발명이다. As described above, when the MML semiconductor device manufacturing method according to the present invention is used, a capacitor is formed in a DRAM region by a high temperature process, and then an insulating film stacked on the DRAM region and the logic region is etched to open the transistor in the logic region to open the silicide. Forming the layer prevents damage to the silicide layer of the logic region due to the high temperature thermal process of the capacitor in the DRAM region, and also forms the lower metal wiring in one step by using the first contact hole in the logic region using the photosensitive film. Since the oxide film is stacked to form contact holes in the DRAM region and the logic region, and the metal wiring is stacked in the second step, it is a very useful and effective invention to accurately and easily form the metal wiring.
도 1 내지 도 9(a)는 본 발명의 일실시예의 MML반도체소자 제조방법을 순차적으로 보인 도면이고, 1 to 9 (a) is a view sequentially showing a method of manufacturing an MML semiconductor device of an embodiment of the present invention,
도 1 내지 도 9(b)는 본 발명의 다른 실시예에 따른 MML반도체소자 제조방법을 순차적으로 보인 도면이다. 1 to 9 (b) is a view sequentially showing a manufacturing method of MML semiconductor device according to another embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 15 : 필드산화막 10: semiconductor substrate 15: field oxide film
20 : 디램게이트전극 25 : 로직게이트전극 20: DRAM gate electrode 25: logic gate electrode
30 : 커패시터 35 : 절연막 30 capacitor 35 insulation film
40 : 실리사이드층 45 : 제1인터폴리산화막40: silicide layer 45: first interpoly oxide film
50 : 제1감광막 55 : 제1콘택부위50: first photosensitive film 55: first contact portion
60,60' : 금속배선 70,70' : 제2감광막 60,60 ': Metal wiring 70,70': Second photosensitive film
75,75' : 제2콘택부위 80,80' : 디램금속배선75,75 ': Second contact area 80,80': DRAM metal wiring
85,85' : 로직금속배선 85,85 ': Logic metal wiring
Claims (5)
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| JPH08153857A (en) * | 1994-11-29 | 1996-06-11 | Nec Corp | Manufacture of semiconductor storage device |
| JPH09260607A (en) * | 1996-03-27 | 1997-10-03 | Nec Corp | Manufacture of semiconductor |
| KR0144413B1 (en) * | 1994-09-26 | 1998-07-01 | 김주용 | Semiconductor device and manufacturing method |
| KR19990005143A (en) * | 1997-06-30 | 1999-01-25 | 윤종용 | Contact hole formation method of semiconductor device |
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| KR0144413B1 (en) * | 1994-09-26 | 1998-07-01 | 김주용 | Semiconductor device and manufacturing method |
| JPH08153857A (en) * | 1994-11-29 | 1996-06-11 | Nec Corp | Manufacture of semiconductor storage device |
| JPH09260607A (en) * | 1996-03-27 | 1997-10-03 | Nec Corp | Manufacture of semiconductor |
| KR19990005143A (en) * | 1997-06-30 | 1999-01-25 | 윤종용 | Contact hole formation method of semiconductor device |
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