KR100871357B1 - Method for fabricating SRAM device - Google Patents

Method for fabricating SRAM device Download PDF

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KR100871357B1
KR100871357B1 KR1020020037298A KR20020037298A KR100871357B1 KR 100871357 B1 KR100871357 B1 KR 100871357B1 KR 1020020037298 A KR1020020037298 A KR 1020020037298A KR 20020037298 A KR20020037298 A KR 20020037298A KR 100871357 B1 KR100871357 B1 KR 100871357B1
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forming
interlayer insulating
insulating film
film
gate electrode
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KR20040001964A (en
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백성학
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Semiconductor Memories (AREA)
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Abstract

본 발명은 에스램소자의 제조방법에 관한 것으로, 본 발명에 따른 에스램 소자의 제조방법은, 반도체기판에 활성영역과 소자분리영역을 한정하는 필드산화막 을 형성하는 단계; 상기 반도체기판의 활성영역상에 게이트전극을 형성한후 반도체 기판의 활성영역 내에 접합영역을 형성하는 단계; 상기 접합영역 및 필드산화막 상에 상기 게이트전극을 덮도록 제1층간 절연막을 형성한 후 상기 제1층간절연막의 일부분을 일정두께만큼 선택적으로 제거하는 단계; 상기 일정두께만큼 제거된 제1층간절연막의 일부분내에 상기 접합영역과 게이트전극 상면을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀을 포함한 제1층간절연막의 일부분내에 금속막을 형성하여 상기 접합영역 및 게이트전극과 연결시키는 단계; 상기 금속막상에 제2층간절연막을 형성하는 단계; 및 상기 제2층간절연막을 상기 제1층간절연막의 일부분내에만 남도록 CMP처리하는 단계를 포함하여 이루어지고, 변형된 다마신공정을 적용하여 금속 및 배선콘택 형성시의 공정단순화 및 생산원가를 절감시킬 수 있다.The present invention relates to a method of manufacturing an SRAM device, the method of manufacturing an SRAM device according to the present invention comprises the steps of: forming a field oxide film defining an active region and a device isolation region on a semiconductor substrate; Forming a junction region in an active region of the semiconductor substrate after forming a gate electrode on the active region of the semiconductor substrate; Forming a first interlayer insulating film on the junction region and the field oxide film so as to cover the gate electrode, and selectively removing a portion of the first interlayer insulating film by a predetermined thickness; Forming a contact hole exposing the junction region and an upper surface of the gate electrode in a portion of the first interlayer insulating film removed by the predetermined thickness; Forming a metal film in a portion of the first interlayer insulating film including the contact hole and connecting the junction region and the gate electrode; Forming a second interlayer insulating film on the metal film; And CMP treatment so that the second interlayer insulating film remains only in a portion of the first interlayer insulating film, and by applying a modified damascene process, process simplification and production cost can be reduced when forming metal and wiring contacts. have.

Description

에스램소자의 제조방법{Method for fabricating SRAM device} Method for fabricating SRAM device {Method for fabricating SRAM device}

도 1 내지 도 7은 본 발명에 따른 에스램소자의 제조방법을 설명하기 위한 공정단면도이다.1 to 7 are cross-sectional views illustrating a method of manufacturing an SRAM device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

11 : 반도체기판 13 : 필드산화막11: semiconductor substrate 13: field oxide film

15 : 게이트전극 17 : 질화막스페이서15 gate electrode 17 nitride film spacer

19 : 접합영역 21 : 제1층간절연막19 junction area 21 first interlayer insulating film

23 : 제1레지스트막패턴 25 : 제2레지스트막패턴23: first resist film pattern 25: second resist film pattern

27a, 27b : 콘택홀 29 : 티타늄막27a, 27b: contact hole 29: titanium film

31 : 티타늄나이트라이드막 33 : 제2층간절연막31 titanium nitride film 33 second interlayer insulating film

35 : 제3층간절연막35: third interlayer insulating film

본 발명은 에스램소자의 제조방법에 관한 것으로서, 보다 상세하게는 에스램제조시에 셀크기를 줄이기 위해 로컬(local) 배선공정 기술에 적합한 에스램소자의 제조방법이다. The present invention relates to a method for manufacturing an SRAM device, and more particularly, to a method for manufacturing an SRAM device suitable for a local wiring process technology in order to reduce a cell size during SRAM manufacturing.                         

풀(full) CMOS 소자 제조시에, 셀밀도 향상을 위해 단위셀을 어떻게 구현하는지가 상당히 중요하다. 따라서, 셀밀도(cell density) 향상을 위해 로컬(local) 배선공정을 적용하고 있다. When manufacturing a full CMOS device, how to implement a unit cell to improve cell density is very important. Therefore, a local wiring process is applied to improve cell density.

그러나, 로컬(local) 배선공정을 적용하는 경우, 공정단계 및 공정의 복잡성으로 인해 수율 감소 및 단가가 비싸지는 문제점이 있다.However, in the case of applying a local wiring process, there is a problem in that the yield is reduced and the cost is high due to the complexity of the process steps and processes.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 변형된 다마신공정을 적용하여 금속 및 배선콘택형성시의 공정단순화 및 생산원가를 절감시킬 수 있는 에스램소자의 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above problems of the prior art, and provides a method for manufacturing an SRAM device that can reduce the process simplification and production cost when forming a metal and wiring contact by applying a modified damascene process. Has its purpose.

상기 목적을 달성하기 위한 본 발명에 따른 에스램소자의 제조방법은, 반도체기판에 활성영역과 소자분리영역을 한정하는 필드산화막을 형성하는 단계; 상기 반도체기판의 활성영역상에 게이트전극을 형성한후 반도체기판의 활성영역 내에 접합영역을 형성하는 단계; 상기 접합영역 및 필드산화막 상에 상기 게이트전극을 덮도록 제1층간 절연막을 형성한 후 상기 제1층간절연막의 일부분을 일정두께만큼 선택적으로 제거하는 단계; 상기 일정두께만큼 제거된 제1층간절연막의 일부분내에 상기 접합영역과 게이트전극 상면을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀을 포함한 제1층간절연막의 일부분내에 금속막을 형성하여 상기 접합영역 및 게이트전극과 연결시키는 단계; 상기 금속막상에 제2층간절연막을 형성하는 단계; 및 상기 제2층간절연막을 상기 제1층간절연막의 일부분내에만 남도록 CMP처리하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing an SRAM device, including: forming a field oxide layer on a semiconductor substrate to define an active region and an isolation region; Forming a junction region in an active region of the semiconductor substrate after forming a gate electrode on the active region of the semiconductor substrate; Forming a first interlayer insulating film on the junction region and the field oxide film so as to cover the gate electrode, and selectively removing a portion of the first interlayer insulating film by a predetermined thickness; Forming a contact hole exposing the junction region and an upper surface of the gate electrode in a portion of the first interlayer insulating film removed by the predetermined thickness; Forming a metal film in a portion of the first interlayer insulating film including the contact hole and connecting the junction region and the gate electrode; Forming a second interlayer insulating film on the metal film; And CMP processing the second interlayer insulating film so that only a portion of the first interlayer insulating film remains.

또한, 상기 금속막 형성후 제2층간절연막을 적층한후 이들을 상기 제1층간 절연막의 일부분내에만 남도록 CMP처리한다.Further, after the formation of the metal film, the second interlayer insulating film is laminated and then subjected to CMP treatment so as to remain only in a part of the first interlayer insulating film.

그리고, 상기 CMP처리된 전체 구조의 상면에 제3층간절연막을 형성한다.A third interlayer insulating film is formed on the upper surface of the CMP-treated whole structure.

더욱이, 상기 제1층간절연막의 일부분은 1000 내지 1500 Å만큼 제거하며, 상기 금속막은 티타늄막 및 티타늄나이트라이드막의 적층구조로 되어 있다.
아울러, 상기 제1층간절연막은 다마신공정을 통해 일정깊이만큼 제거된다.
또한, 상기 콘택홀은 일정두께만큼 제거된 제1층간절연막의 일부분을 포함한 전체 상면상에 레지스트패턴을 형성한후 이를 마스크로 상기 일정두께만큼 제거된 제1층간절연막의 일부분을 선택적으로 제거하여 형성한다.Further, a part of the first interlayer insulating film is removed by 1000 to 1500 mW, and the metal film has a laminated structure of titanium film and titanium nitride film.
In addition, the first interlayer insulating film is removed to a certain depth through a damascene process.
In addition, the contact hole is formed by forming a resist pattern on the entire upper surface including a portion of the first interlayer insulating film removed by a predetermined thickness, and then selectively removing a portion of the first interlayer insulating film removed by the predetermined thickness with a mask. do.

(실시예)(Example)

이하, 본 발명에 따른 에스램소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing an SRAM device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 7은 본 발명에 따른 에스램소자의 제조방법을 설명하기 위한 공정단면도이다.1 to 7 are cross-sectional views illustrating a method of manufacturing an SRAM device according to the present invention.

본 발명에 따른 에스램소자의 제조방법은, 도 1에 도시된 바와같이, 먼저 반도체기판(11)에 필드산화막(13)을 형성한후 반도체기판(11)의 활성영역상에 게이트형성용 폴리실리콘을 증착한후 이를 선택적으로 제거하여 게이트전극(15)을 형성한다.In the method of manufacturing an SRAM device according to the present invention, as shown in FIG. 1, a field oxide film 13 is first formed on a semiconductor substrate 11, and then a gate forming poly is formed on an active region of the semiconductor substrate 11. After depositing silicon, it is selectively removed to form a gate electrode 15.

그다음, 상기 게이트전극(15)의 측면에 질화막스페이서(17)을 형성한후 반도체기판(11)내에 불순물을 주입하여 접합영역(19)을 형성한다.Next, after forming the nitride film spacer 17 on the side of the gate electrode 15, the impurity is implanted into the semiconductor substrate 11 to form the junction region 19.

이어서, 도 2에 도시된 바와같이, 전체 구조의 상면에 제1층간절연막(21), 예를들어 BPSG막을 증착한 후 CMP처리한다.Subsequently, as shown in FIG. 2, the first interlayer insulating film 21, for example, a BPSG film, is deposited on the upper surface of the entire structure, followed by CMP treatment.

그다음, 도 3에 도시된 바와같이, CMP처리된 제1층간절연막(21)상에 제1레지스트를 도포한후 상기 제1레지스트를 선택적으로 패터닝하여 레지스트막패턴(23)을 형성한다음 상기 제1레지스트막패턴(23)을 마스크로 상기 제1층간절연막(21)을 선택적으로 패터닝하여 일정깊이만큼 제거한후 상기 제1레지스트막패턴(23)을 제거한다. 이때, 상기 제1층간절연막(21)은 약 1000 Å ∼ 1500 Å 만큼 건식식각한다.Next, as shown in FIG. 3, after applying the first resist on the CMP-treated first interlayer insulating film 21, the first resist is selectively patterned to form a resist film pattern 23. The first interlayer insulating film 21 is selectively patterned using the first resist film pattern 23 as a mask to be removed to a predetermined depth, and then the first resist film pattern 23 is removed. At this time, the first interlayer insulating film 21 is dry etched by about 1000 kV to 1500 kPa.

이어서, 도 4에 도시된 바와같이, 제1레지스트패턴(23)을 제거한후 일정깊이만큼 제거되고 남은 상기 제1층간절연막(21)상에 제2레지스트막패턴(25)을 형성한후 이를 마스크로 상기 제1층간절연막(21)을 선택적으로 제거하여 상기 접합영역(19) 및 게이트전극(15)을 각각 노출시키는 콘택홀(27a)(27b)을 형성한다.Subsequently, as shown in FIG. 4, after the first resist pattern 23 is removed, a second resist film pattern 25 is formed on the first interlayer insulating film 21 remaining after being removed to a certain depth and then masked. The first interlayer insulating film 21 is selectively removed to form contact holes 27a and 27b exposing the junction region 19 and the gate electrode 15, respectively.

그다음, 도 5에 도시된 바와같이, 상기 제2레지스트막패턴25)을 제거한후 상기 콘택홀(27a)(27b)을 포함한 전체 구조의 상면에 티타늄막(29) 및 티타늄나이트라이드막(31)을 순차적으로 적층하여 상기 접합영역(19) 및 게이트전극(15)과 연결된다.Next, as shown in FIG. 5, after the second resist film pattern 25 is removed, the titanium film 29 and the titanium nitride film 31 are formed on the upper surface of the entire structure including the contact holes 27a and 27b. Are sequentially stacked to be connected to the junction region 19 and the gate electrode 15.

이어서, 도 6에 도시된 바와같이, 전체 구조의 상면에 제2층간절연막(33), 예를들어 산화막을 증착한후 이를 CMP처리하여 평탄화시킨다.Subsequently, as shown in FIG. 6, a second interlayer insulating film 33, for example, an oxide film is deposited on the upper surface of the entire structure and then planarized by CMP treatment.

그다음, 도 7에 도시된 바와같이, 전체 구조의 상면에 제3층간절연막(35)을 증착한다.Then, as shown in Fig. 7, a third interlayer insulating film 35 is deposited on the upper surface of the entire structure.

상기에서 설명한 바와같이, 본 발명에 따른 에스램소자의 제조방법에 의하면, 로컬 배선공정 적용시에 에스램소자의 드라이브 트랜지스터의 출력부(out put)가 다른 트랜지스터의 입력 게이트와 연결되는 부분을 변형된 다마신 공정을 적용하여 얇은 티타늄 및 티타늄 나이트라이드막으로 배선을 형성하므로써 간단히 로컬 배선을 형성할 수 있다.As described above, according to the method of manufacturing an SRAM device according to the present invention, a portion in which an out put of a drive transistor of an SRAM device is connected to an input gate of another transistor when applying a local wiring process is modified. The local damascene can be simply formed by applying a thin damascene titanium and titanium nitride film by applying the damascene process.

따라서, 에스램소자 개발시 셀밀도 향상을 위해 로컬 배선공정시에 변형된 다마신공정을 적용하므로써 공정의 단순화 및 원가절감을 이룰 수 있다.Therefore, by applying the modified damascene process in the local wiring process to improve the cell density in the development of the SRAM device, the process can be simplified and the cost can be reduced.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (7)

반도체기판에 활성영역과 소자분리영역을 한정하는 필드산화막을 형성하는 단계;Forming a field oxide layer on the semiconductor substrate, the field oxide layer defining an active region and an isolation region; 상기 반도체기판의 활성영역상에 게이트전극을 형성한후 반도체기판의 활성영역내에 접합영역을 형성하는 단계;Forming a junction region in an active region of the semiconductor substrate after forming a gate electrode on the active region of the semiconductor substrate; 상기 접합영역 및 필드산화막 상에 상기 게이트전극을 덮도록 제1층간 절연막을 형성한 후 상기 제1층간절연막의 일부분을 일정두께만큼 선택적 으로 제거하는 단계;Forming a first interlayer insulating film on the junction region and the field oxide film to cover the gate electrode, and then selectively removing a portion of the first interlayer insulating film by a predetermined thickness; 상기 일정두께만큼 제거된 제1층간절연막의 일부분내에 상기 접합영역과 게이트전극상면을 노출시키는 콘택홀을 형성하는 단계;Forming a contact hole in a portion of the first interlayer insulating film removed by the predetermined thickness to expose the junction region and the upper surface of the gate electrode; 상기 콘택홀을 포함한 제1층간절연막의 일부분내에 금속막을 형성하여 상기 접합영역 및 게이트전극과 연결시키는 단계; Forming a metal film in a portion of the first interlayer insulating film including the contact hole and connecting the junction region and the gate electrode; 상기 금속막상에 제2층간절연막을 형성하는 단계; 및Forming a second interlayer insulating film on the metal film; And 상기 제2층간절연막을 상기 제1층간절연막의 일부분내에만 남도록 CMP처리하는 단계;를CMP processing the second interlayer dielectric so that only a portion of the first interlayer dielectric is left; 포함하여 이루어지는 것을 특징으로하는 에스램소자의 제조방법.Method of manufacturing an S-RAM device comprising a. 삭제delete 제1항에 있어서, 상기 CMP처리된 전체 구조의 상면에 제3층간절연막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 에스램소자의 제조방법.The method of claim 1, further comprising forming a third interlayer dielectric layer on the upper surface of the CMP-treated whole structure. 제1항에 있어서, 상기 제1층간절연막의 일부분은 1000 내지 1500 Å만큼 제거하는 것을 특징으로하는 에스램소자의 제조방법.The method of claim 1, wherein a portion of the first interlayer insulating layer is removed by 1000 to 1500 Å. 제1항에 있어서, 상기 금속막은 티타늄막 및 티타늄나이트라이드막의 적층 구조인 것을 특징으로 하는 에스램소자의 제조방법.The method of claim 1, wherein the metal film has a laminated structure of a titanium film and a titanium nitride film. 제1항에 있어서, 상기 제1층간절연막은 다마신공정을 통해 일정부분만큼 제거되는 것을 특징으로하는 에스램소자의 제조방법.The method of claim 1, wherein the first interlayer dielectric film is removed by a predetermined portion through a damascene process. 제1항에 있어서, 상기 콘택홀은 일정두께만큼 제거된 제1층간절연막의 일부분을 포함한 전체 상면상에 레지스트패턴을 형성한후 이를 마스크로 상기 일정두께만큼 제거된 제1층간절연막의 일부분을 선택적으로 제거하여 형성하는 것을 특징으로하는 에스램소자의 제조방법.The method of claim 1, wherein the contact hole is formed by forming a resist pattern on the entire top surface including a portion of the first interlayer insulating layer removed by a predetermined thickness, and then selectively selecting a portion of the first interlayer insulating layer removed by the predetermined thickness using a mask. Method for manufacturing the SRAM element, characterized in that formed by removing.
KR1020020037298A 2002-06-29 2002-06-29 Method for fabricating SRAM device KR100871357B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6083827A (en) * 1998-12-15 2000-07-04 United Microelectronics Corp. Method for fabricating local interconnect
US6194313B1 (en) * 1997-04-30 2001-02-27 Texas Instruments Incorporated Method for reducing recess for the formation of local interconnect and or plug trench fill for etchback process
JP2001077213A (en) * 1999-09-08 2001-03-23 Mitsubishi Electric Corp Static semiconductor storage device and semiconductor device
JP2001085433A (en) 1999-09-10 2001-03-30 Nec Corp Semiconductor device and manufacturing-method therefor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6194313B1 (en) * 1997-04-30 2001-02-27 Texas Instruments Incorporated Method for reducing recess for the formation of local interconnect and or plug trench fill for etchback process
US6083827A (en) * 1998-12-15 2000-07-04 United Microelectronics Corp. Method for fabricating local interconnect
JP2001077213A (en) * 1999-09-08 2001-03-23 Mitsubishi Electric Corp Static semiconductor storage device and semiconductor device
JP2001085433A (en) 1999-09-10 2001-03-30 Nec Corp Semiconductor device and manufacturing-method therefor

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