KR100481985B1 - Manufacturing method of highly integrated MML semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MML semiconductor device, and in particular, after forming a DRAM transistor and a logic transistor on a semiconductor substrate of a DRAM region and a logic region, sequentially depositing a first interlayer oxide film and a first interlayer nitride film on the resulting product. Wow; After the step of laminating a first photoresist film on the logic transistor, and etching the first interlayer nitride oxide film of the DRAM region by etching; Removing the first photoresist film after the above step, laminating a second interlayer insulating film in the DRAM region and the logic region, forming bit lines and capacitors in the DRAM region by a high temperature thermal process, and forming a buffer oxide film in all regions; Stacking a second photoresist film on the resultant of the DRAM region and removing the buffer oxide film, the second interlayer insulating film, the first interlayer nitride oxide film and the first interlayer oxide film by an etching process; Forming a titanium silicide layer in the source / drain region of the logic transistor after the step; A method of manufacturing a highly integrated MML semiconductor device comprising: laminating a third interlayer insulating film after the step, and then laminating a third photosensitive film so that only the cell region of the DRAM region is opened, and then etching the third interlayer insulating layer of the cell region. Since the silicide layer is formed on the source / drain of the logic transistor after the high temperature thermal process is performed first, it is a very useful and effective invention to improve the yield of semiconductor devices by preventing damage due to deterioration of the silicide layer.

Description

Manufacturing method of highly integrated MML semiconductor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MML semiconductor device, and in particular, to form a DRAM gate electrode and a logic gate electrode of a DRAM region and a logic region at the same time, and then, an insulating film is laminated on the DRAM region, and a capacitor and a bit line are formed by a high temperature thermal process. The gate electrode of the logic region is opened by masking etching, a silicide layer is laminated on the field oxide layer of the logic gate electrode, and a plurality of metal layers and intermetallic insulating layers are stacked on the resultant to prevent damage to the silicide layer of the logic region. It relates to a method for manufacturing a highly integrated MML semiconductor device.

In general, a mixed semiconductor (MML: Merged Memory Logic), in which memory and logic are formed on a single chip, has been increasingly used in recent years, and this MML semiconductor device has been increasingly used. Since it is possible to manufacture a single process in one chip and memory, it has the advantage that it can operate at a higher speed and use at lower power than existing chips without any special design change.

On the other hand, since the manufacturing process of the memory product and the manufacturing process of the logic product are manufactured on the same chip at the same time, the size of the unit chip is increased, and therefore, it has a disadvantage that requires a lot of difficulty to proceed with the manufacturing process. Transistors have more emphasis on preventing leakage current than requiring high current driving force, but logic products must be manufactured in one chip with both characteristics such as high current driving capability.

As described above, in the semiconductor substrate, a field oxide film and a gate electrode of a transistor are simultaneously formed in a memory region and a logic region, a spacer film is stacked on a side portion of the gate electrode, and ions are implanted into an active region to form a source / drain. After the process, a capacitor was formed on the field oxide film of the memory region by a high temperature process of 800 ° C., and the insulating layer and the metal wiring layer of the oxide film were formed on the transistor of the logic region and the transistor and capacitor of the memory region. Lamination is carried out in a multilayer process.

By the way, as described above, the transistors in the memory region place emphasis on the prevention of leakage current, while the transistors in the logic region place emphasis on having a high current driving capability. After the formation of all, the process of manufacturing a high temperature capacitor (about 800 ℃) in the memory region is performed, which is important for transistors already manufactured in the logic region, particularly for silicide layers formed in the source / drain and active regions of the transistor. It had a problem of lowering the current driving ability of the transistor in the logic region to affect the device performance.

An object of the present invention is to form a DRAM gate electrode and a logic gate electrode of the DRAM region and the logic region at the same time, and then to insulate an insulating film in the DRAM region, and to form a capacitor and a bit line by a high temperature thermal process, and then the gate of the logic region by masking etching The purpose is to prevent damage to the silicide layer of the logic region by opening the electrode, laminating a silicide layer on the field oxide film of the logic gate electrode, and laminating a plurality of metal layers and an intermetallic insulating layer on the resultant.

The object is to form a DRAM transistor and a logic transistor on the semiconductor substrate of the DRAM region and the logic region, and then sequentially depositing the first interlayer oxide film and the first interlayer nitride oxide film on the resultant material; After the step of laminating a first photoresist film on the logic transistor and etching the first interlayer nitride oxide film of the DRAM region by etching; Removing the first photoresist film after the above step, laminating a second interlayer insulating film in the DRAM region and the logic region, forming bit lines and capacitors in the DRAM region by a high temperature thermal process, and forming a buffer oxide film over the entire region; Stacking a second photoresist film on the resultant of the DRAM region and removing the buffer oxide film, the second interlayer insulating film, the first interlayer nitride oxide film and the first interlayer oxide film by an etching process; Forming a titanium silicide layer in the source / drain region of the logic transistor after the step; Stacking a third interlayer insulating film after the step, and then laminating a third photoresist film to open only the cell region of the DRAM region, and then etching the third interlayer insulating layer of the cell region; Removing the third photoresist film and reducing the step between the third interlayer insulating film over the entire region by a chemical mechanical polishing process; It is achieved by providing a method for fabricating a highly integrated MML semiconductor device comprising the step of laminating a plurality of metal layers and intermetallic insulating films on the third interlayer insulating film.

The buffer oxide layer and the second interlayer dielectric layer of the logic region may be removed by wet etching, and the first interlayer nitride oxide layer and the first interlayer oxide layer may be removed by dry etching, and the titanium may be removed. The silicide layer is achieved by providing a rapid thermal processing process, and the third interlayer insulating film is achieved by providing a method for manufacturing a highly integrated MML semiconductor device, which is allowed to proceed by a flowing process at 650 to 700 ° C.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 1 illustrates the formation of a DRAM transistor 20 and a logic transistor 25 on a semiconductor substrate 10 in a DRAM area and a logic area. Then, a first interlayer oxide film 30 and A state in which the first interlayer nitride oxide film 35 is sequentially stacked is shown.

FIG. 2 illustrates a state in which the first interlayer nitride oxide film 35 in the DRAM region is etched after the first photoresist film 40 is stacked on the logic transistor 25 after the step.

3, the first photoresist film 40 is removed after the above step, and the second interlayer insulating film 50 is laminated in the DRAM region and the logic region, and then the bit line 45 is formed by a high temperature thermal process in the DRAM region. And a capacitor 55 and a buffer oxide film 60 stacked in the DRAM and logic regions.

4 and 5 illustrate a buffer oxide film 60, a second interlayer insulating film 50, a first interlayer nitride oxide film 35, and a buffer oxide film 60 in a logic region by an etching process after stacking a second photoresist film on the result of the DRAM region. The state which removes the 1st interlayer oxide film 30 is shown.

At this time, the buffer oxide layer 60 and the second interlayer dielectric layer 50 of the logic region are removed by wet etching, and the first interlayer nitride oxide layer 35 and the first interlayer oxide layer 30 of the logic region are removed. ) Is preferably removed by dry etching.

FIG. 6 shows a state in which a titanium silicide layer (TiSi ₂ ) 70 is formed in the source / drain region of the logic transistor 25 after the step, wherein the titanium silicide layer 70 is formed by a rapid thermal treatment process (RTP); Rapid Thermal Processing).

FIG. 7 illustrates a state in which the third photoresist layer 75 is laminated with the third interlayer dielectric layer 75 stacked after the above step, and the Periphery region of the DRAM region is stacked and only the cell region is opened. The third interlayer insulating film 75 is subjected to a flow process at a temperature of 650 to 700 ° C.

FIG. 8 illustrates a state in which the third interlayer dielectric layer 75 in the cell region is etched by laminating the third photoresist layer 80.

FIG. 9 illustrates a state in which the third photoresist film 80 is removed and the step difference is reduced by the chemical mechanical polishing process of the third interlayer insulating film 75 in all regions.

FIG. 10 illustrates a state in which the first metal layer 85 is formed after the metal plug is formed using the metal contact mask.

FIG. 11 shows a state where a first interlayer insulating film 90 is formed on the resultant product.

FIG. 12 shows a state in which the second metal layer 95 is formed by masking etching on the resultant.

FIG. 13 illustrates a state in which a second interlayer insulating film 100 is stacked, and a third and fourth metal interlayer insulating film 110, a third intermetallic insulating film 110, and a protective oxide film 120 are stacked on the resultant. It is shown.

As described above, when the method for fabricating the highly integrated MML semiconductor device according to the present invention is used, the DRAM gate electrode and the logic gate electrode of the DRAM region and the logic region are simultaneously formed, and then an insulating film is laminated on the DRAM region, and the capacitor is subjected to a high temperature thermal process. After forming the bit line, the gate electrode of the logic region is opened by masking etching, a silicide layer is laminated on the field oxide layer of the logic gate electrode, and a plurality of metal layers and intermetallic insulating layers are stacked on the resultant DRAM region. It is very useful to improve the yield of the semiconductor device by preventing the damage caused by deterioration of the silicide layer because the silicide layer is formed on the source / drain of the logic transistor after the high temperature thermal process of forming the capacitor and the bit line first. It is an effective invention.

1 to 13 are views sequentially showing a method for manufacturing a highly integrated MML semiconductor device according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10: semiconductor substrate 15: field oxide film

20: DRAM transistor 25: Logic transistor

30: first interlayer oxide film 35: first interlayer oxide film

40: first photosensitive film 45: bit line

50: second interlayer insulating film 55: capacitor

60: buffer oxide film 65: second photosensitive film

70: titanium silicide layer 75: third interlayer insulating film

80: third photosensitive film 85: first metal layer

90: first interlayer insulating film 95: second metal layer

100: second interlayer insulating film 105: third metal layer

110: third metal interlayer insulating film 115: fourth metal layer

120: protective oxide film

Claims (5)

Forming a DRAM transistor and a logic transistor on the semiconductor substrate of the DRAM region and the logic region, and then sequentially depositing the first interlayer oxide film and the first interlayer nitride oxide film on the resultant material; After the step of laminating a first photoresist film on the logic transistor, and etching the first interlayer nitride oxide film of the DRAM region by etching; Removing the first photoresist film after the above step, laminating a second interlayer insulating film in the DRAM region and the logic region, forming bit lines and capacitors in the DRAM region by a high temperature thermal process, and forming a buffer oxide film over the entire region; Stacking a second photoresist film on the resultant of the DRAM region and removing the buffer oxide film, the second interlayer insulating film, the first interlayer nitride oxide film and the first interlayer oxide film by an etching process; Forming a titanium silicide layer in the source / drain region of the logic transistor after the step; After the step of laminating a third interlayer insulating film, etching the third interlayer insulating film of the cell region by laminating a third photosensitive film so that only the cell region of the DRAM region is opened; Removing the third photoresist film and polishing the third interlayer insulating film in the DRAM region and the logic region by a chemical mechanical polishing process to reduce the step difference; A method for manufacturing a highly integrated MML semiconductor device, comprising: stacking a plurality of metal layers and an intermetallic insulating film on the third interlayer insulating film. The method of claim 1, wherein the buffer oxide layer and the second interlayer dielectric layer of the logic region are removed by wet etching. The method of claim 1, wherein the first interlayer nitride oxide layer and the first interlayer oxide layer of the logic region are removed by dry etching. The method of claim 1, wherein the titanium silicide layer is subjected to a rapid heat treatment process. The method of claim 1, wherein the third interlayer dielectric film is processed at 650 to 700 占 폚.