591758 五、發明說明（1) 【發明所屬之技術領域】 本發明係關於一種在單一電晶體靜態唯讀存取記憶體 (IT SRAM)之製程中，改善因上電極層的應力所誘導出的 縫隙（v 〇 i d )之方法，特別是添加一内介電層於電容的上電 極層和其抗反射層中間。 【先前技術】 傳統的靜態隨機存取記憶體（SRAM )之基本元件配置是 由六個電晶體組成，通常是四個N通道（N-channel)的金屬 氧化半導體場效電晶體（MOSFET)加兩個P通道的MOSFET。 為了要降低製程成本，半導體業試著製造更小的晶片，且 至少和原先晶片的密度相同，甚至更大。只要能夠在一定 大小的基材上切割出更多的晶片，每單一晶片的成本便降 低。然而，在SRAM製造技術中，將六個電晶體放置於一較 小的半導體晶片上，是一件有些困難的事。因此，SRAM的 製造技術就專注在一個電晶體，即1 T SRAM的晶胞上，其 包括一金屬氧化半導體場效電晶體（MOSFET)，及一電容結 構。這樣的一個單一電晶體及電容結構之特徵，卻提供了 與六個電晶體的SRA Μ相同的功效，也逐漸邁向設計更小的 半導體晶片之路。 由於製程整合一直在改善，目前半導體業製造積體電 路的趨勢，即為整合記憶胞陣列與高速邏輯電路於一單一 晶片上，形成一内嵌式記憶體（例如内嵌式動態隨機存取 記憶體、内嵌式1 T SRAM)。内嵌式同時包含了記憶陣列及591758 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for improving the induction induced by the stress of the upper electrode layer in a single transistor static read-only access memory (IT SRAM) process. The method of the gap (V oid), in particular, an internal dielectric layer is added between the capacitor's upper electrode layer and its anti-reflection layer. [Prior technology] The basic element configuration of traditional static random access memory (SRAM) is composed of six transistors, usually four N-channel metal oxide semiconductor field effect transistors (MOSFETs) plus Two P-channel MOSFETs. To reduce process costs, the semiconductor industry is trying to make smaller wafers that are at least as dense as the original wafers, or even larger. As long as more wafers can be cut on a certain size substrate, the cost per single wafer is reduced. However, in SRAM manufacturing technology, it is a bit difficult to place six transistors on a small semiconductor wafer. Therefore, the manufacturing technology of SRAM is focused on a transistor, that is, a unit cell of 1 T SRAM, which includes a metal oxide semiconductor field effect transistor (MOSFET), and a capacitor structure. The characteristics of such a single transistor and capacitor structure, however, provide the same efficacy as the SRA M of six transistors, and they are gradually moving towards the design of smaller semiconductor wafers. Because process integration has been improving, the current semiconductor industry's trend in manufacturing integrated circuits is to integrate memory cell arrays and high-speed logic circuits on a single chip to form an embedded memory (such as embedded dynamic random access memory Body, embedded 1 T SRAM). Embedded contains both memory array and
第5頁 591758 五、發明說明（2) 邏輯電路，能夠大大地減少電路面積以增加處理速率。對 於1 T SRAM製程來說，電容製程必須在邏輯製程開始前完 成，而其間為了要縮小胞的尺寸，閘極勢必會覆蓋整個電 容。所以小於0. 1 3// m (百萬分之一米）的製程是極具挑戰 性的。由於電容製程在邏輯製程開始前就需完成，因此電 容將會有一連串的高溫製程，例如閘極氧化層之成長、源 /汲極之離子植入。由於這些接續的高溫製程，上電極層 與抗反射層間的應力不平衡會導致縫隙（vo i d )在上電極層 與抗反射層之間形成。也由於這些縫隙的產生，閘極成長 時會經過縫隙與上電極層相接觸，而導致閘極與上電極層 之間的短路。 【發明内容】 有鑑於上述之發明背景中，電容的上電極層和其抗反 射層中間應力不平衡，並會產生縫隙；同時，該縫隙會導 致閘極與上電極層間的短路。 因此，本發明的目的就是在提供一種單一電晶體靜態唯讀 存取記憶體電容器的製造方法，可以避免上電極層與抗反 射層之間不平衡的應力。 本發明的另一目的就是在提供一種單一電晶體靜態唯讀存 取記憶體電容器的製造方法，可以避免後續高溫製程中縫 隙的產生。 本發明的再一目的就是在提供一種單一電晶體靜態唯讀存 取記憶體電容器的製造方法，可以避免閘極成長時，經過Page 5 591758 V. Description of the invention (2) The logic circuit can greatly reduce the circuit area to increase the processing rate. For the 1 T SRAM process, the capacitor process must be completed before the logic process starts, and in order to reduce the cell size, the gate is bound to cover the entire capacitor. So processes smaller than 0.1 3 // m (parts per millionth of a meter) are extremely challenging. Because the capacitor process needs to be completed before the logic process starts, the capacitor will have a series of high temperature processes, such as the growth of the gate oxide layer and the source / drain ion implantation. Due to these successive high-temperature processes, a stress imbalance between the upper electrode layer and the anti-reflection layer may cause a gap (vo i d) to be formed between the upper electrode layer and the anti-reflection layer. Because of these gaps, when the gate grows, it will contact the upper electrode layer through the gap, resulting in a short circuit between the gate and the upper electrode layer. [Summary of the Invention] In view of the above-mentioned background of the invention, the stress between the upper electrode layer of the capacitor and its anti-reflection layer is unbalanced and a gap may be generated; at the same time, the gap may cause a short circuit between the gate and the upper electrode layer. Therefore, an object of the present invention is to provide a method for manufacturing a single transistor static read-only memory capacitor, which can avoid unbalanced stress between the upper electrode layer and the anti-reflection layer. Another object of the present invention is to provide a method for manufacturing a single transistor static read-only memory capacitor, which can avoid the generation of gaps in subsequent high-temperature processes. Another object of the present invention is to provide a method for manufacturing a single transistor static read-only memory capacitor, which can prevent the
第6頁 591758 五、發明說明（3) 縫隙與上電極層相接觸，而導致閘極與上電極層間的短 路。 根據以上的目的，本發明的實施方法步驟如下：在半 導體基材上形成淺溝渠隔離結構，在其上依序形成一墊氧 化層及一第一罩幕層。形成一圖案化光阻層在主動區及淺 溝渠隔離結構上，暴露出預定之電容製作區域。向下蝕刻 移除部分淺溝渠隔離結構以定義出複數個開口 ，接著，移 除光阻層，共形地沉積一第一導體層。依序移除在第一罩 幕層上之第一導體層，移除墊氧化層上之第一罩幕層，使 得第一導體層可覆蓋於該淺溝渠隔離結構之内。 接著依序形成一第一介電層、一第二導體層、一第二介電 層及一抗反射層於該主動區及淺溝渠隔離結構上。然後非 等向蝕刻部分該及抗反射層、第二介電層、第二導體層及 第一介電層，並以墊氧化層為停止層以定義出一電容結 構。接著形成一間隙壁於該墊氧化層上，然後形成一閘極 氧化層於主動區上，最後形成閘極結構跨過該電容結構、 該主動區及淺溝渠隔離結構之上。 【實施方式】 為了讓本發明和上述之目的、特徵和優點更能明顯易 懂，僅將一較佳實施方式及結果列於後，並配合所附圖示 加以詳述： 請參考第1圖，在一半導體基材1 0 0上形成一淺溝渠隔離結 構102(STI)，並定義出一主動區104(Active Area)。接Page 6 591758 V. Description of the invention (3) The gap is in contact with the upper electrode layer, resulting in a short circuit between the gate and the upper electrode layer. According to the above purpose, the method of implementing the present invention comprises the following steps: forming a shallow trench isolation structure on a semiconductor substrate, and sequentially forming a pad oxidation layer and a first mask layer thereon. A patterned photoresist layer is formed on the active area and the shallow trench isolation structure to expose a predetermined capacitor fabrication area. Etching down removes part of the shallow trench isolation structure to define a plurality of openings. Then, the photoresist layer is removed, and a first conductor layer is conformally deposited. The first conductor layer on the first mask layer is sequentially removed, and the first mask layer on the pad oxide layer is removed, so that the first conductor layer can cover the shallow trench isolation structure. A first dielectric layer, a second conductor layer, a second dielectric layer, and an anti-reflection layer are sequentially formed on the active area and the shallow trench isolation structure. Then, the anti-reflection layer, the second dielectric layer, the second conductor layer, and the first dielectric layer are anisotropically etched, and a pad oxide layer is used as a stop layer to define a capacitor structure. A gap wall is then formed on the pad oxide layer, then a gate oxide layer is formed on the active area, and finally a gate structure is formed across the capacitor structure, the active area, and the shallow trench isolation structure. [Embodiment] In order to make the present invention and the above-mentioned objects, features, and advantages more obvious and understandable, only a preferred embodiment and result are listed below, and are described in detail with the accompanying drawings: Please refer to FIG. A shallow trench isolation structure 102 (STI) is formed on a semiconductor substrate 100, and an active area 104 is defined. Pick up
第7頁 591758 五、發明說明（4) 著，對該主動區1 0 4進行離子佈植，以形成摻雜井區（未繪 示於圖上）。 請參考第2圖，在基材上依序沉積墊氧化層18(Pad Oxide) 及第一罩幕層2 0。其中，該第一罩幕層2 0之材質係例如氮 化矽，且係利用電漿加強型-化學氣相沉積（PE-CVD)法， 或是低壓-化學氣相沉積（LP-CVD)法形成。接著塗佈一光 阻層（未繪示於圖上）覆蓋住主動區及淺溝渠隔離結構上 方，圖案化光阻層（未繪示於圖上）暴露出部分淺溝渠隔離 10 2及主動區104，以主動區上的第一罩幕層2 0為罩幕，以 一蝕刻製程在淺溝渠隔離結構1 0 2中形成複數個開口 ，這 些開口係用來作為電容器開口之結構。 請參照第3圖，移除光阻層（未繪示於圖上）。接著共 形地沉積一第一導體層2 2於該些開口及第一罩幕層2 0之 上。該第一導體層之材質可以是多晶石夕（Polysilicon)或 其他導電金屬層。 請參照第4圖，利用化學機械研磨或回蝕法移除下電 極層22，而第一罩幕層2 0作為停止層（stop layer)。接著 利用熱磷酸（hot Η 3P04)移除第一罩幕層20。 請參照第5圖，共形地依序沉積第一介電層2 4、第二 導體層26、第二介電層2 8及抗反射層30。其中，第一介電 層2 4之材質係一氮化矽與氧化矽的雙層結構。第二導體層 26，其材質可以是多晶矽或其他導電金屬層。第二介電層 2 8可以是氧化物或氮化物。抗反射層3 0之材質可以是具延 展力的氮氧化石夕（S i 0 N )，係利用低壓-化學氣相沉積Page 7 591758 V. Description of the Invention (4) The ion implantation is performed on the active region 104 to form a doped well region (not shown in the figure). Referring to FIG. 2, a pad oxide layer 18 (Pad Oxide) and a first mask layer 20 are sequentially deposited on the substrate. Wherein, the material of the first cover layer 20 is, for example, silicon nitride, and the plasma enhanced chemical vapor deposition (PE-CVD) method or low pressure chemical vapor deposition (LP-CVD) is used. Law formation. Next, a photoresist layer (not shown in the figure) is coated to cover the active area and the shallow trench isolation structure. The patterned photoresist layer (not shown in the figure) exposes a part of the shallow trench isolation 10 2 and the active area. 104. Using the first mask layer 20 on the active area as a mask, an opening process is used to form a plurality of openings in the shallow trench isolation structure 102, and these openings are used as a capacitor opening structure. Please refer to Figure 3 to remove the photoresist layer (not shown). Next, a first conductor layer 22 is conformally deposited on the openings and the first mask layer 20. The material of the first conductor layer may be polysilicon or other conductive metal layers. Referring to FIG. 4, the lower electrode layer 22 is removed by chemical mechanical polishing or etch-back, and the first mask layer 20 is used as a stop layer. The first mask layer 20 is then removed using hot phosphoric acid (hot Η 3P04). Referring to FIG. 5, the first dielectric layer 24, the second conductive layer 26, the second dielectric layer 28, and the anti-reflection layer 30 are sequentially deposited conformally. The material of the first dielectric layer 24 is a double-layer structure of silicon nitride and silicon oxide. The material of the second conductor layer 26 may be polycrystalline silicon or other conductive metal layers. The second dielectric layer 28 may be an oxide or a nitride. The material of the anti-reflection layer 30 can be a stretched oxynitride (S i 0 N), which uses low pressure-chemical vapor deposition.
第8頁 591758 五、發明說明（5) (LP-CVD)的方式形 請參照第6圖 導體層26、第二介 為停止層以定義出 沉積氮化矽層於該 化石夕層上。然後蚀 4 0緊鄰氮化矽層。 隙壁42於墊氧化層 因此形成了 一種氮 成閘極氧化層4 6於 即可。 其中要說明的 層2 2係為電容結構 結構中。而第二導 特別要說明的是， 第二介電層28於電 電極層，與抗反射 中縫隙（vo i d )的產 續高溫製程中縫隙 隙與上電極層相接 正如習知技藝 例揭露如上，並非 本發明之精神所做 請專利範圍内。 成。 非等向蝕刻部分第一介電層24 電層2 8及抗反射層3 〇，並以塾氧 一電容結構44於STI之上。接著^ 電谷之上’之後再沉積氧化石夕層 刻移除該氮化矽層，形成氧化矽 然後餘刻移除氮化矽層，形成氮 1 8之上、電容之兩側，大體上成 化矽與氧化矽之複合型間隙壁。 主動區1 0 4之上，最後形成閘極立 是’本發明之較佳實施例中，第 4 4之下電極層，且此下電極層位 體層2 6係為電容結構4 4之上電極 本發明之較佳實施例，其特徵在 容中’可平衡第二導體層26，也 層3 0之間的應力，以減少後續高 生。此外，由於應力的平衡，減 的產生，更避免在閘極成長時， 觸，而導致閘極與上電極層間的 的人員所瞭解，本發明係以較佳 限定本發明之申請專利範圍；凡 的潤飾、改變或更動，均包含以 第二 化層18 ^形地 於該氮 間隙壁 化矽間 L型。 接著形 I線5 6 一導體 於STI 層。 於添加 就是上 溫製裎 少了後 經過縫 短路。 的實施 未脫離 下之申 591758 圖式簡單說明 【圖 式簡單說明】 為配合本發明之 做詳細說明，其中： 第1至第6圖係依 面示 意圖。 【元 件代表符號簡單 18 塾氧化層（Pad 20 第一罩幕層 22 第一導體層 24 第一介電層 26 第二導體層 28 第二介電層 30 抗反射層（ARC) 40 氧化矽間隙壁 42 氮化矽間隙壁 44 電容結構 46 閘極氧化層 56 閘極連線 100 基材 102 淺溝渠隔離結. 104 主動區Page 8 591758 V. Method Description of Invention (5) (LP-CVD) Please refer to Fig. 6. The conductor layer 26 and the second dielectric are stop layers to define a silicon nitride layer deposited on the fossil layer. Then etch 40 next to the silicon nitride layer. The barrier wall 42 and the pad oxide layer thus form a nitrogen-forming gate oxide layer 46. Among them, the layer 2 2 is a capacitor structure. The second guide particularly states that the second dielectric layer 28 is on the electrical electrode layer, and the gap is connected to the upper electrode layer during the continuous high-temperature process of the anti-reflection gap (vo id), as disclosed in the conventional art. As mentioned above, the spirit of the present invention is not within the scope of the patent. to make. The non-isotropically etched portion of the first dielectric layer 24, the electric layer 28, and the anti-reflection layer 30, is formed on the STI with a yttrium-capacitance structure 44. Then ^ on top of the electric valley, and then deposit a silicon oxide layer to remove the silicon nitride layer to form silicon oxide, and then remove the silicon nitride layer at a later time to form nitrogen over 18 and two sides of the capacitor. Generally, A composite spacer of silicon and silicon oxide. Above the active region 104, the gate electrode is finally formed. In a preferred embodiment of the present invention, the electrode layer below the fourth electrode layer 4 and the lower electrode layer body layer 26 is the electrode above the capacitor structure 4 4 A preferred embodiment of the present invention is characterized in that it can balance the stress between the second conductor layer 26 and the layer 30 to reduce subsequent hyperplasia. In addition, due to the balance of stress and the reduction of the occurrence, it is more avoided to contact the gate during the growth of the gate, which leads to the understanding between the gate and the upper electrode layer. Retouching, changing, or changing, all include L-shaped siliconized interlayer silicon formed in the shape of a second layer 18 ^. Then form a conductor I 6 5 6 on the STI layer. After the addition, the temperature is lowered and the short circuit occurs after sewing. The implementation does not depart from the following application 591758 Brief description of the drawings [Simplified description of the drawings] In order to cooperate with the present invention, detailed descriptions are made, wherein: Figures 1 to 6 are shown according to the intent. [Element symbol is simple 18 塾 oxide layer (Pad 20 first cover layer 22 first conductor layer 24 first dielectric layer 26 second conductor layer 28 second dielectric layer 30 anti-reflection layer (ARC) 40 silicon oxide gap Wall 42 Silicon nitride gap wall 44 Capacitor structure 46 Gate oxide layer 56 Gate connection 100 Substrate 102 Shallow trench isolation junction. 104 Active area
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