TW483157B - Formation method of buried capacitor of embedded memory - Google Patents

Abstract

This invention provides a formation method of capacitor for the application in single transistor dynamic random access memory (DRAM). The bottom electrode of capacitor is buried in the recess area of etched oxide layer of shallow trench isolation region through lithography and etching steps. The spacer between the top electrode and the bottom electrode can be used to prevent short circuit between the mutually connected polysilicon and source/drain region. The method of the present invention also utilizes anti-reflection coating effect and insulation characteristics of oxynitride layer as the cap layer of the top electrode formed by mutually connected polysilicon, which can further reduce the area of unit memory cell.

Description

483157 V. Description of the Invention Field of the Invention The present invention relates to a method. BACKGROUND OF THE INVENTION Computers: They also care about the system: doubt, the key to the unit price of memory is the capacity of the capacitor / (refresh can be longer, / the degree of aggregation is the industry's same chip! The key to consider is shown at the top Electricity; Compound silicon gate: Reduced size-—— ⑴

It relates to a semiconductor memory stacked capacitor used in a static and random process, especially a method for accessing memory cells. Hi Corinthin 1 The electronics industry not only requires an increase in the memory size of the integrated circuit, Not only will it be low, but it will also affect the price of the computer. Usually it is not a method in active components, because the size of the capacitor and time) are related to it. The larger it is, the more it will occupy more. Therefore, how to pursue the goal with the smallest unit. In addition, the phase of the self-reporting § self-memory process is related to the overall performance of the process and decreases. As far as computers are concerned, none will affect the performance of the computer, ^. And it is related to the cost of memory, electricity and time, but the capacitance of passive components and data storage and renewal time, 1afresh time, and the area of the substrate, and reducing the maximum area to generate the maximum capacitance has always been the memory cell and logic circuit. Can not fail to consider the degree of complexity 'that is, cost.

The shown silicon substrate planar capacitor 10 (pUnar capacitor) (top plate and capacitor dielectric layer can be completely compatible with 20 and gate oxide layers in the logic process, but it is difficult to make the memory cell. The reason is Planar capacitance 丨 〇 itself is an occupation

483157 V. Description of the invention (2) Large-area components. To reduce the area of the planar capacitor by reducing the thickness of the capacitor dielectric layer will be limited by the minimum thickness of the capacitor dielectric layer. This is because capacitor dielectric layers having a thickness of less than 30 angstroms are susceptible to the problem of leakage current. Therefore, another traditional method to solve the above problems is to use trench capacitors instead of purely reducing the dielectric layer of the capacitor. However, the conventional method of forming a trench capacitor has a problem of complicated steps. In addition, traditional stack capacitors require many additional thermal budgets. And it is not completely compatible with the logic process. In view of the above, the present invention will propose a capacitor buried in the oxide layer of the shallow trench isolation region (ST I), which can form a capacitance of about 3.5 to 5.0 fF per unit of memory cell. Such a capacitor can be applied. In it SRAM 'single transistor static random access memory. The 1T SRM capacitor does not need to be very large, because its renewal time (r e f r e s h t i m e) is very short, about the refresh time of lms to O.lms. In addition, as an interchangeable function of the word line and interconductor wire, the polycrystalline spar layer can use the way of the top electrode of the capacitor to make full use of each unit of silicon area to achieve The goal of reducing the capacitance of the capacitor is to reduce the area of each silicon substrate. Object and Summary of the Invention: One object of the present invention is to provide a concept that a capacitor is buried in a shallow trench isolation area (s τ I). 5. The concept of the invention (3) ^. Another object of the present invention is to provide a stabbed field _ You Xianxian ~ formed by means of a capacitor across the = interconnection, crystalline silicon layer (isolated by nitrogen silicon oxide layer). It is used to reduce the traditional problem, and open the inter-connected short circuit caused by the compound crystal dream, and the semiconductor substrate with more waves f. The present invention utilizes a silicon nitride spacer wall of six π, addressing% ~ ~ Η 双 double U to reduce the problem of passergate and 乂 interconnected polycrystalline stone stringer. The invention provides an embedded memory method, particularly a method for forming a process method for a single transistor static capacitor. Contains the following bulk / precursor: Capacitors for accessing memory. A shallow trench isolation area has been formed on a thousand-conductor substrate. ^ The bulk substrate forms an n-well. Lai, formed: among them. In turn, Yu Fengdao-a photoresist pattern on the capacitor node oxide layer:: emulsion layer. Then, the left and right sides of the shallow trench isolation area are formed, and the opening position of the photoresist pattern is defined as the position of the crown-shaped capacitor. After that, a photoresist is used to form recessed areas for the left and right of the tomb isolation area. Second, the semiconductor substrate is engraved with money to make the shallow trench adjacent. Then, the & plane, ::, and the shallow trench isolation region are implanted with a P-type conductive impurity ion and the first polycrystalline silicon layer is deposited. In the process, the capacitor node oxide layer is polished, and the back stop is chemically / polished, and the first polycrystalline stone layer on the sidewall is removed to produce two or two removals higher than the concave region. The bottom of the solid-phase isolation capacitor in Tian 1 was then wet-etched to remove the exposed electricity to remove the oxide layer on the node.

483157 V. Description of the invention (4) Exposing the semiconductor capacitor dielectric layer. Immediately after, a p-type layer was applied. Then use the top electrode of the microcomputer. After forming the gap wall, sequentially and etch define the gate and the side walls that are electrically connected to form a nitride stone and the implantation of nitride ions in order to form metal silicide and the source / drain invention. Problem. Not too incompatible, such as the surface of a traditional stacked substrate. Next, a capacitor dielectric layer No is formed. After the formation, a second polycrystalline silicon layer is deposited on the capacitor dielectric layer. An anti-reflection coating is deposited on the second polycrystalline silicon layer. No. 9 Conductive impurity ions are implanted, and the second polycrystalline silicon layer is defined by doping the second polycrystalline silicon lithography and etching technology as a capacitor, and then the exposed capacitor dielectric layer is removed. Immediately, on the sidewalls of the top electrode and the bottom electrode, a gate electrode, an oxide layer, and a third polycrystalline silicon layer are formed again.

Two polycrystalline silicon layers and a gate oxide layer to form a transistor-connected polycrystalline silicon connecting wire. After the M pole is defined, ldd ion implantation is applied, and then the gap wall is on the side of the transistor gate and the side wall of the polycrystalline silicon connecting wire layer. The source / inverted area a is then applied. Implant p-type conductive impurities. Finally, a self-aligned process layer is formed on the transistor gate and the polycrystalline silicon connection conductor. Capacitors made with traditional methods have a lot of area, such as planar capacitors, which are related to logic processes such as trench capacitors, or capacitors that require a lot of thermal budget. The method of the present invention can solve the above-mentioned problem 483157 V. Description of the invention (5). Please refer to FIG. 2A. First, a photoresist pattern (not shown) is used to define a n-type well 1 10 region on a semiconductor substrate of a shallow trench isolation region 105 formed by conventional techniques as a capacitor and logic. In the area where the transistor is located, the photoresist pattern (not shown) is used as a mask, and ions of n-type conductive impurities are implanted to form the n-type well 110 area shown in the figure. Then, a capacitor node oxide layer 120 is formed by a thermal oxidation process or a chemical vapor deposition method. The thickness of the oxide layer 12 of the capacitor node is about 5 0-8 0 0 angstroms, and the depth of the shallow trench isolation region 105 is about 3 0 0 0-5 0 0 angstroms. Of course, if the thermal oxidation process is used, the increase in the height of the oxide layer in the shallow trench isolation will be much smaller than the oxide layer on the upper surface of the n-type well 110. If the chemical vapor deposition method is used, the thickness of the capacitor node oxide layer 120 deposited on the upper surface of the shallow trench isolation zone 105 and the n-type well 110 is about the same. Subsequently, as shown in FIG. 2B, a photoresist pattern 125 is formed on the capacitor node oxide layer 120 to define a crown-shaped capacitor range. As shown in the figure, the photoresist pattern block 1 25 is formed in the center of the shallow trench isolation area 105 (about one third of the width of the shallow trench isolation area 105 is weak), and the capacitor node oxide layer 120 m In this way, the oxide layer 105 of the shallow trench isolation area 105 (the left and right sides each is about one-third of the width of the shallow trench isolation area 105) is exposed, and some adjacent η-types are exposed at the same time. The capacitor node oxide layer 120 on the top surface of the well 110 is also exposed. 483157 V. Description of the invention (6) Still refer to FIG. 2B. Next, the photoresist pattern 125 is used as a mask, and etching is performed to remove the I oxidation of the shallow trench isolation area not covered by the photoresist pattern 125. Layer and the capacitor node oxide layer 20 until the semiconductor substrate under the capacitor node oxide layer 120 is exposed. Since the oxide layer in the shallow trench isolation region and the valley electrode node layer 120 are both of the same oxide layer material, a recessed region 127 will be formed after etching, as shown in the figure. The recessed area 127 includes adjacent semiconductor substrates on both sides of the shallow trench isolation area 12 7. The exposed semiconductor substrate is used to connect the bottom electrode of the capacitor to the source / drain region of the logic region. In a preferred embodiment, the depth of the recessed region ^ can be about half of the total depth of the shallow trench isolation region 105. For example, if the depth of the shallow trench isolation region 105 is 350 nm, the depth of the recessed region is about 180 nm. As shown in the figure, the center of the shallow trench isolation zone is like a plateau. #Next, after the photoresist pattern 125 is removed, please refer to FIG. 2c | 検 The cross section is not intended, and then a low-pressure chemical vapor deposition method (LpcvD method) is used to deposit a polycrystalline silicon layer 13 0 after etching. The shallow trench isolation area ι5 is on the semiconductor substrate 110 and the capacitor node oxide layer 120. The thickness of the polycrystalline silicon layer 130 is about 200 to 4/0 angstroms. Subsequently, a p-type conductive impurity ion implantation is applied to dope the polycrystalline silicon layer 130. The implantation of P-type conductive impurities instead of n-type transconductance has the advantages of reducing electron mobility and reducing the chance of soft errors. Please refer to the schematic cross-sectional view shown in FIG. Chemical / mechanical

Page 9 483157 V. Description of the invention (7) A type polishing process (CMP) to remove the polycrystalline silicon layer above the sidewall of the recessed area. The capacitor node oxide layer 120 is used as an etch stop layer. After this step, the polycrystalline silicon layer 130 will be left on the sidewall and bottom of the recessed region 1 2 7. At the same time, the two polycrystalline silicon layers 1 30 of the two recessed regions 1 2 7 are isolated from each other, and a two bottom electrode 1 3 0 A plate is formed. With this CMP step back #, there is an advantage that a photomask can be omitted. Next, please refer to the schematic cross-sectional view shown in FIG. Then, the capacitor node oxide layer 120 is removed by a wet etching method. After this step, the upper surface of the n-type well 1 10 that is not covered by the first polycrystalline silicon layer 130 will be exposed. Then, a nitrided layer 14 is formed on the bottom electrode 13 A and the exposed semiconductor substrate 110 by the LPCCVD method. Then, a high-temperature thermal oxidation process is performed to form a N / 0 capacitor interlayer 140 structure. Of course, it is also possible to use 0 n 0 as the capacitor dielectric layer. The thickness of the capacitor dielectric layer 14 is about 4-6 nm. Still referring to FIG. 2E, a low-pressure chemical vapor deposition method is used to deposit a second polycrystalline stone layer 150 thicker than the bottom electrode 130A # on the capacitor dielectric layer 140, as the top electrode of the capacitor. . Subsequently, a silicon nitride oxide layer (S i NO X) 1 6 0 was formed by a chemical vapor deposition method in the first-borrowed stone shovel i5〇 ^ 2 > 0 0-40 0 Angstrom} silicon nitride oxide layer 16 〇 Can be used as the top electrode patterned anti-reflection coating to improve lithographic resolution. Subsequently, a p-type impurity ion implantation is applied to dope the polycrystalline silicon layer. as the picture shows. — The top electrode is etched again to remove the capacitance that is not covered by the polycrystalline silicon layer 150. =

Page 10 483157 V. Description of the invention (8) The electrical layer 140 exposes the semiconductor substrate.

Next, please refer to the schematic cross-sectional view shown in FIG. A photoresist pattern (not shown) is formed on the silicon nitride oxide layer 160 to define the top electrode. The capacitor on the left as shown in the figure, because it is close to the logic area, the second polycrystalline silicon layer 15 is truncated and cut off within the sidewall of the recessed area, and the length L adjacent to the sidewall is about 50. 0-100 Angstroms. The capacitor on the right side of the figure is connected to other capacitors in the capacitor area. Therefore, the polycrystalline silicon layer 15 on the right side of the figure is not. After removing the resist pattern, the dielectric layer i 40 which is not the second polycrystalline stone layer 15 o * 电 is removed to expose _ o and the upper surface of the electrode 130A. -1 Still refer to FIG. 2F, and then, the gasification stone layer side of the capacitor is formed. The spacers 170B and 170A are formed on the side wall of the top electrode 150 and the outer side wall of the bottom electrode, respectively. The forming method is as follows: a silicon nitride layer is formed first, and then a silicon nitride spacer is formed on the side wall of the top electrode 150 by anisotropic etching, and the nitride is formed on the side wall of the bottom electrode 130 A. Silicon spacer 170B. Please refer to the schematic cross-sectional view shown in FIG. Then, a thermal oxidation process is called to form a gate oxide layer 180 on the upper surface of the exposed n-type well 110. Immediately after the 'reopening', a second polycrystalite layer is formed on all surfaces. Then use the photoresist pattern and the money engraving technique to define the interconnected polycrystalline silicon layer i 9 0 and the logic region complex crystal Shi Xiwen electrode layer 19 0 B on the upper surface of the n-type well 11 10. Exposed gate oxide layer 8

Page 11 483157 V. Description of the invention (9)-Removal by wet etching. Please note that the interconnect polycrystalline silicon layer 19A is located above the silicon nitride oxide layer 160 on the top electrode plates of the two capacitors around the shallow trench isolation zone 105. Next, pLDD ion implantation is applied to implant p-type conductive i impurities into the exposed n-type well 11 to form a pLDD doped region 195. Recently, as shown in Fig. 2A, a nitrided nitride spacer or a silicon oxide spacer 2 0 0A is formed by a conventional method on the inter-connected polycrystalline silicon layer 190A and the spacer 2 0 0B of the polycrystalline gate 19B. . In addition, the side wall of the partition wall 170A will also form a small partition wall 200C. Next, a source / electrode region of P-type conductive impurities is implanted to form a source / drain region 210. After that, the quasi-process of forming a gold i region 190 B and interconnects includes the first formation of _i metal silicide, and the remaining low-value and high-value ions are formed. In addition, the doping is further improved. Refer to the cross-sectional schematic diagram shown in FIG. 2I for the activation process, and then use the self-pairing silicide layer 2 2 0 in the source / drain region 2 1 0, the polycrystalline gate line polycrystalline stone layer 1 9 0 A on. The metal layer of the metallization self-alignment process is then annealed to form an unreacted metal layer on the lower-temperature gold-engraved barrier wall and a metal silicide in the high-temperature annealing process. The ions in the hetero bottom electrode will also diffuse out of the polycrystalline silicon layer out of the region 230 to connect to the ^ 1) 1) region 195, so that during the process of conductive flame, impurities will also be caused by the annealing process and the aforementioned hot oxygen The present invention has the following advantages: < 1 > The present invention

Bright capacitors are suitable for applications from 3.5 to 5.0fF

Page 12 483157 V. Description of the Invention (1) ~ 1 transistor SRAM, and because the bottom-embedded bottom electrode plate is applied with shallow trench isolation area, it can save considerable area. For example, taking the process of m. 丨 3 as an example, a SRAM of a 6-transistor cell requires an area of 2.2 / z m, while a SRAM of a conventional 1-transistor cell requires 1.1 to 1! 2 with an area of m2, and the application of the present invention will further reduce the area to 0.6 to 0.7 m. <2 &gt; Because the bottom electrode has P-split conductive impurities implanted, these impurities can diffuse outward when the metal silicide is annealed, which is beneficial to the connection between the capacitor node and PLDD.

&lt; 3 &gt; Since a small node area is used (relative to a planar capacitor), I, the node junction leakage current can be relatively reduced. | &lt; 4 &gt; The capacitor interactive connection line is directly made on the capacitor, so the waste of the planar area of the silicon substrate can be further reduced. &lt; 5 &gt; After the top electrode is defined, an additional nitride stone spacer is formed on the top electrode sidewall, so it can prevent the short circuit caused by the polycrystalline silicon stringer between the pass-gate and the interconnect wiring. opportunity. (The present invention is described above with reference to the preferred embodiment. Those skilled in the art can make some modifications without departing from the spirit of the present invention. Equivalent field depends.

Page 13 483157 Brief description of the drawings The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: Figure 1 shows a schematic diagram of a conventional transistor and a planar capacitor. FIG. 2A is a schematic cross-sectional view of a semiconductor substrate that sequentially defines an n-type well and forms an oxide valley node oxide layer in a shallow trench isolation region process according to the method of the present invention. FIG. 2B is a schematic cross-sectional view of a photoresist pattern as a mask for etching to form two recessed regions according to the method of the present invention. Fig. 2C shows a schematic cross-sectional view of the first polycrystalline spar layer and the implantation of p-type conductive impurity ions according to the method of the present invention. FIG. 2D is a schematic cross-sectional view of a bottom electrode of two adjacent capacitors subjected to a CMP polishing process according to the method of the present invention. Fig. 2E shows a schematic cross-section of a capacitor dielectric layer, a second polycrystalline stone layer, a nitrogen stone oxide layer, and a p-type conductive impurity ion implantation according to the method of the present invention. Fig. 2F shows a schematic cross-sectional view of the method according to the present invention for defining the top electrode, removing the exposed capacitor dielectric layer, and then forming a silicon nitride spacer. FIG. 2G is a schematic cross-sectional view of forming a gate oxide layer, a polycrystalline stone layer, defining an interconnected polycrystalline silicon layer 190 and a polycrystalline silicon gate layer and applying PLDD ion implantation according to the method of the present invention. . Fig. 2 is a schematic cross-sectional view showing the formation of a silicon nitride spacer according to the method of the present invention and the implantation of ion implantation in the source / drain region of a P-type conductive impurity. 483157 Schematic illustration Figure 2I shows a schematic cross-sectional view of a metal silicide layer formed on a source / drain region, a complex gate region, and an interconnect polysilicon layer formed by a self-aligned process according to the method of the present invention. . Comparative description of drawing numbers: Shallow trench isolation region 105 Doped region 230 η-type well 110 Capacitance node oxide layer 120 Photoresist pattern 125 Recessed region 127 First polycrystalline layer 130 Bottom electrode 130A Capacitor dielectric layer 140 Second polycrystalline silicon layer 150 top electrode 150A silicon nitride oxide layer 170 silicon nitride spacer 170A and 170B gate oxide layer 180 third polycrystalline silicon layer 180 interconnect polycrystalline silicon layer 190A silicon nitride spacer or silicon oxide spacer 2 0 0 A, .200B, 200C PLDD doped region 195 source / &gt; and electrode region 210 metal silicide layer 220

Page 15

Claims (1)

483157 VI. Application for patent scope 1. A method for manufacturing embedded capacitors in embedded memory, the method includes at least the following steps: \ Provide a semiconductor substrate, the semiconductor substrate has formed a shallow trench isolation region therein; forming η -Well in the semiconductor substrate; forming a capacitor node oxide layer on all surfaces of the semiconductor substrate, wherein the openings of the first photoresist pattern are respectively located on the left and right sides of the shallow trench isolation area, and the semiconductors of the adjacent portions and the body substrate On the surface of the η well, the position of the crown-shaped capacitor is defined; using the first photoresist pattern as a mask, an etching technique is applied to etch the exposed oxide layer of the capacitor node and the oxide layer of the shallow trench isolation area to form a left And a right depression area on both sides of the shallow trench isolation area, the depression area including the surface of the η well adjacent to the shallow trench isolation area; removing the first photoresist pattern; i depositing a first polycrystalline silicon layer on the A shallow trench isolation region, the semiconductor substrate, and the I capacitor node oxide layer; applying conductive impurity ion implantation to dope the first polycrystalline silicon layer; A chemical / mechanical polishing process to remove the first polycrystalline silicon layer above the i-side of the recessed area to generate two isolated capacitor bottom electrodes, and use the capacitor node oxide layer as a polishing termination layer; Wet-etching the exposed oxide layer of the capacitor node to expose the semiconductor substrate; forming a capacitor dielectric layer on the semiconductor substrate, the capacitor bottom electrode, and the oxide layer in the exposed shallow trench isolation; Page 16 483157 6. Application scope Deposition of a second polycrystalline silicon layer on the capacitor dielectric layer; deposition of a dielectric layer on the second polycrystalline silicon layer; implantation of conductive impurity ions for doping Hybrid the second polycrystalline silicon layer; I define the second polycrystalline silicon layer and the dielectric layer as the top electrode of the capacitor; remove the exposed capacitor dielectric layer; form a barrier wall on the top electrode and the capacitor dielectric Layer, the sidewall of the bottom i electrode;! Gate oxide layer, a third polycrystalline silicon layer are sequentially formed on the semiconductor substrate I and the dielectric layer on the top electrode of the capacitor; i! Lithography and etching to define the The third polycrystalline silicon layer and the gate oxide layer are used to form the gate of the transistor and connect the polycrystalline silicon connecting wire in an interactive manner; applying LDD ion implantation to form an LDD region on the semiconductor substrate; forming a nitrogen Silicon spacers are placed on the side of the transistor gate and the polycrystalline silicon connection lead layer and the sidewalls of the silicon nitride spacer; | Source / drain region ion implantation is applied to implant conductive impurities in the Semi | conductor substrate; and from An alignment process is performed to form a metal silicide layer on the transistor gate and the polycrystalline silicon connecting wire layer and the source / drain region. Page 17 483157 VI. Scope of patent application The recessed area contains a part of the semiconductor substrate adjacent to the shallow trench isolation area, "" so that the bottom electrode of the capacitor can be connected to the source / drain area of the logic area. 4 The method according to item 1 of the scope of patent application, wherein the capacitor dielectric layer is selected from one of N / 0 or 0 / N / 0, and the thickness is about 40-60 Angstroms. Ί 5. If the scope of patent application is The method of item 1, wherein the dielectric layer on the top electrode of the capacitor is a silicon nitride oxide layer with a thickness of about 200 to 40 angstroms. 6. The method of item 1 in the scope of patent application, wherein the depth of the above-mentioned recessed area Approximately between one third and two thirds of the depth of the shallow trench isolation area. 7. The method of item 1 in the scope of the patent application, wherein the second definition i: the compound silicon layer is used as the top electrode of the capacitor The steps include at least the following steps: forming a photoresist pattern layer on the dielectric layer, where the photoresist block is closer to one side of the logic region than the bottom electrode, so that the defined top electrode is shorter than the bottom electrode The electrodes are transported away from the logic area and the short length is about 500-1000 angstroms; and using the photoresist pattern layer as a mask, etching the dielectric layer and the second polycrystalline silicon layer to form the above top electrode; and removing the photoresist pattern. 8.-Embedding A method for manufacturing a buried capacitor in an embedded memory. The method includes at least the following steps: Page 18 483157 6. The scope of the patent application provides a semiconductor substrate 'the semiconductor substrate has formed a shallow trench isolation region therein; ·· formation of η -well in the semiconductor substrate; formation of a capacitor node oxide layer on all surfaces of the semiconductor substrate; A first photoresist pattern is on the capacitor node oxide layer, wherein the openings of the first photoresist pattern are respectively located on the left and right sides of the shallow trench isolation area, and the η well surface on the adjacent semiconductor substrate to define the crown The shape of the capacitor; using the first photoresist pattern as a mask and applying an etching technique to etch the exposed capacitor node oxide layer and the shallow trench isolation region oxide layer to form left 0 and right recessed areas in the shallow trench The recessed area on both sides of the isolation area includes the surface of the η well adjacent to the shallow trench isolation area; removing the first photoresist pattern; depositing a first polycrystalline silicon layer on the shallow trench isolation area and the shallow trench isolation The surface of the n-well adjacent to the region and the oxide layer of the capacitor node; implanted with P-type conductive impurity ions to dope the first polycrystalline silicon layer; Chemical / mechanical polishing process to remove the first polycrystalline silicon layer above the side of the recessed area | wall to produce two isolated capacitor bottom electrodes, with the capacitor node oxide layer as the polishing termination layer; Etching the exposed oxide layer of the capacitor node to expose the semiconductor substrate; forming a capacitor dielectric layer on the semiconductor substrate, the bottom electrode of the capacitor, and the oxide layer in the exposed shallow trench isolation; Page 19, 483157 VI. Application scope Deposition of a second polycrystalline silicon layer on the capacitor dielectric layer A nitrogen silicon oxide layer is deposited on the second polycrystalline stone ^: P-type conductive impurity ion implantation is applied ,: The upper layer, from the doping of the second polycrystalline silicon, the first polycrystalline silicon layer is defined as the capacitor A, wherein the second polycrystalline silicon near the logic region side is an electrode, and So that it is farther away from the logic region; the bottom electrode is short and the exposed capacitor and dielectric layer are removed; the capacitor dielectric layer forms a gap on the side wall of the bottom electrode of the top electrode; A gate oxide layer and a second polycrystalline silicon layer are sequentially formed on the half and a dielectric layer on the top electrode of the capacitor; a bulk phase, lithography, and etching to define the third polycrystalline silicon layer, the gate An oxide layer to form the gate of the transistor and to interconnect the polycrystalline silicon connection wires; it is known that it is implanted with p-type ions for forming a pLDD region on the semiconductor beauty board; &amp; forming a silicon nitride gap Wall on the transistor gate and the side wall of the polycrystalline silicon connection wire layer and the side wall of the silicon nitride spacer; applying source / drain region ion implantation to implant conductive impurities in the semiconductor substrate; And ^ using a self-aligned process to form a metal silicide layer on the transistor gate and the subsequent Shi Xi connection wire layer and the source / drain region. 9 If * • As described in A, the method of item 8 of the patent, which is described in the above steps Page 20 483157 6. Scope of patent application The recessed area includes a part of the semiconductor substrate adjacent to the shallow trench isolation area, which is used to connect the bottom electrode of the capacitor to the source / drain area of the logic area. 10. The method according to item 8 of the patent application range, wherein the capacitor dielectric layer is selected from one of N / 0 or 0 / N / 0 and has a thickness of about 40-60 angstroms. 1 1. The method according to item 8 of the scope of patent application, wherein the dielectric layer on the top electrode of the capacitor is a silicon nitride oxide layer with a thickness of about 200 to 40 angstroms. 1 2. The method according to item 8 of the scope of patent application, wherein the depth of the above-mentioned recessed area is about 1/3 to 2/3 of the depth of the shallow trench isolation area. Page 21