JP4399934B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing technique of a semiconductor integrated circuit device, and more particularly to a technique effective when applied to the manufacture of a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
[0002]
[Prior art]
Recent DRAMs have a so-called stacked capacitor structure in which an information storage capacitor element is disposed above a memory cell selection MISFET in order to compensate for a decrease in the amount of charge stored in the information storage capacitor element due to miniaturization of the memory cell. Is adopted. A DRAM employing this stacked capacitor structure is roughly divided into a capacitor under bitline (CUB) structure (for example, Japanese Patent Laid-Open No. 7-192723) in which an information storage capacitor is arranged below the bit line. And JP-A-8-204144) and a capacitor over bitline (COB) structure (for example, JP-A-7-122654) in which an information storage capacitor element is disposed above a bit line. (Kaihei 7-106437).
[0003]
Of the two types of stacked capacitor structures described above, the COB structure in which the information storage capacitor element is disposed above the bit line is more suitable for miniaturization of the memory cell than the CUB structure. This is because a CUB structure in which a bit line is arranged above the information storage capacitor element because it is necessary to increase the surface area by increasing the surface area of the structure in order to increase the amount of charge stored in the miniaturized information storage capacitor element. This is because the aspect ratio of the contact hole connecting the bit line and the memory cell selecting MISFET becomes extremely large, and it is difficult to open the hole.
[0004]
Further, in recent large capacity DRAMs such as 64 megabits (Mbit) or 256 megabits, contacts for connecting a bit line or an information storage capacitive element and a substrate to a space of a gate electrode of a miniaturized memory cell selection MISFET. When forming the hole, the top and side walls of the gate electrode are covered with a silicon nitride film, and the contact hole is opened in a self-aligned manner with respect to the gate electrode by utilizing the etching rate difference between the silicon oxide film and the silicon nitride film. In order to employ a self-align contact (SAC) technique (for example, Japanese Patent Laid-Open No. 9-252098) that makes holes, or to reduce the resistance of the gate electrode, the gate electrode is made of W (tungsten) or the like. A polymetal gate structure (Japanese Patent Laid-Open No. 7-94716) composed mainly of a refractory metal material is adopted. It is or.
[0005]
[Problems to be solved by the invention]
As the present inventor has developed 256 megabit (Mbit) DRAM and 1 gigabit (Gbit) DRAM, the present inventor is considering reducing the bit line capacity as a measure for increasing the refresh time interval. .
[0006]
The component of the bit line capacitance is divided into a pair of adjacent bit lines, a pair of substrates, a pair of storage electrodes, a pair of word lines, and a pair of plate electrodes. In the case of the COB structure in which the information storage capacitor element is disposed above the bit lines, Although depending on the structure such as the word line spacer film thickness, the capacitance component to the word line is one of the main components. Therefore, in order to reduce the bit line capacitance, first, it is the highest priority to reduce the capacitance against the word line.
[0007]
As described above, a DRAM employing the self-aligned contact (SAC) technique needs to cover the upper portion and side walls of the gate electrode with a silicon nitride film. However, since the dielectric constant of the silicon nitride film is about twice as large as that of the silicon oxide film, if the upper part of the gate electrode and the side wall are covered with the silicon nitride film, the capacity of the bit line with respect to the word line must be increased. Absent.
[0008]
An object of the present invention is to provide a technique capable of reducing the bit line capacity in a DRAM with a reduced memory cell size.
[0009]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
Forming a plurality of gate electrodes including a refractory metal film whose sidewalls are silicided on a semiconductor substrate;
Converting the silicidized refractory metal film side walls into a silicon oxide film;
Forming a source or drain on the surface of the semiconductor substrate located between two adjacent gate electrodes;
Forming a first insulating film on the semiconductor substrate including the gate electrode;
Forming a second insulating film on the first insulating film;
Forming a contact hole exposing the source or drain by etching using a difference in etching rate between the first insulating film and the second insulating film;
Forming a conductive layer in the contact hole;
It is characterized by having.
In addition, the step of forming a plurality of gate electrodes including a refractory metal film whose sidewalls are silicided on the semiconductor substrate,
Forming a plurality of gate electrodes including a refractory metal film with exposed sidewalls on the semiconductor substrate;
Introducing silicon ions into the exposed sidewall of the refractory metal film, or covering the exposed sidewall of the refractory metal film with a silicon layer;
A step of silicidizing the sidewall of the refractory metal film by heat-treating the semiconductor substrate.
In addition, the step of forming a plurality of gate electrodes including a refractory metal film whose sidewalls are silicided on the semiconductor substrate,
Forming a refractory metal film on the semiconductor substrate;
Forming a mask on the refractory metal film;
Introducing silicon ions into the refractory metal film exposed from the mask, or forming a silicon layer on the exposed surface of the refractory metal film;
Siliciding the refractory metal film exposed from the mask and the refractory metal film located immediately below the side wall of the mask to the bottom by heat-treating the semiconductor substrate;
Using the mask as an etching mask, and removing the silicided refractory metal film exposed from the mask by etching.
Further, the first insulating film is a silicon nitride film, and the second insulating film is a silicon oxide film.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
[0012]
(Embodiment 1)
A manufacturing method of the DRAM according to the present embodiment will be described in the order of steps with reference to FIGS.
[0013]
First, as shown in FIG. 1, an element isolation trench 2 is formed in an element isolation region on a main surface of a semiconductor substrate (hereinafter referred to as a substrate) 1 made of, for example, p-type single crystal silicon. The element isolation trench 2 is formed by etching the surface of the substrate 1 to form a trench having a depth of about 300 to 400 nm, and subsequently depositing a silicon oxide film 4 on the substrate 1 including the inside of the trench by the CVD method. The silicon oxide film 4 is formed by polishing back by a chemical mechanical polishing (CMP) method. At this time, the silicon oxide film 4 inside the trench is flattened so that the surface thereof is almost the same height as the surface of the active region.
[0014]
Next, an n-type impurity, for example, P (phosphorus) is ion-implanted into the substrate 1 to form a p-type well 3, and then the surface of the p-type well 3 is cleaned with an HF (hydrofluoric acid) -based cleaning solution. A clean gate oxide film 5 is formed on the surface of the p-type well 3 by wet-oxidizing the substrate 1.
[0015]
Next, as shown in FIG. 2, a gate electrode conductive film 6 is deposited on the gate oxide film 5, and then a silicon nitride film 10 is deposited on the conductive film 6 by the CVD method. The conductive film 6 for the gate electrode includes, for example, a polycrystalline silicon film 7 doped with an n-type impurity such as P (phosphorus), a barrier metal film 8 made of WN (tungsten nitride) or TiN (titanium nitride), and a W film. 9. The barrier metal film 8 is formed to prevent the polycrystalline silicon film 7 and the upper W film 9 from reacting during high-temperature heat treatment to form a high-resistance silicide layer at the interface between them.
[0016]
Next, as shown in FIG. 3, by patterning the silicon nitride film 10 by dry etching using the photoresist film 11 as a mask, a hard mask 10A for etching the conductive film 6 is formed. Next, after removing the photoresist film 11, as shown in FIG. 4, silicon ions are implanted into the conductive film 6 (W film 9) in the region exposed by the etching of the silicon nitride film 10.
[0017]
Next, as shown in FIG. 5, the W film 9 and silicon are reacted by heat-treating the substrate 1 to convert the W film 9 in the region where the hard mask 10A is not formed into a W silicide layer 9A. At this time, due to the diffusion of silicon, the W film 9 immediately below the side wall of the hard mask 10A is also silicided to some extent.
[0018]
Next, as shown in FIG. 6, the conductive film 6 (W silicide layer 9A, barrier metal film 8, and polycrystalline silicon film 7) is patterned by dry etching using the hard mask 10A as a mask. As a result, the gate electrode 12 in which a part of the side wall is covered with the W silicide layer 9A is formed.
[0019]
When the above dry etching is performed, the gate oxide film 5 in a region not covered by the gate electrode 12 is removed, and the gate oxide film 5 at the end of the side wall of the gate electrode 12 is also isotropically etched, resulting in an undercut. As a result, problems such as a decrease in the breakdown voltage of the gate electrode 12 occur. Therefore, the substrate 1 is thermally oxidized in order to improve the profile of the side wall end portion of the undercut gate electrode 12.
[0020]
When the thermal oxidation is performed, as shown in FIG. 7, the W silicide layer 9A exposed on the side wall of the gate electrode 12 is oxidized to form a silicon oxide layer 9B. In the polycrystalline silicon film 7 constituting another part of the gate electrode 12, the side wall portion of the gate electrode 12 is oxidized to form a silicon oxide layer 7A.
[0021]
Next, as shown in FIG. 8, an n-type impurity, for example, P (phosphorus) is ion-implanted into the p-type well 3, and an n-type semiconductor region 13 (source, drain) is formed in the p-type well 2 on both sides of the gate electrode 12. As a result, the memory cell selecting MISFET Qs is substantially completed.
[0022]
Next, as shown in FIG. 9, a silicon nitride film 14 is deposited on the substrate 1 by the CVD method. Since the silicon oxide layers 7A and 9B are formed on the side wall of the gate electrode 12 in the above-described process, the silicon nitride film 14 and the silicon oxide layer (7A or 9B) are formed on the side wall of the gate electrode 12 when the silicon nitride film 14 is deposited. It will be covered with.
[0023]
Next, as shown in FIG. 10, after depositing the silicon oxide film 15 on the substrate 1 by the CVD method, the n-type semiconductor region is dry-etched using the etching rate difference between the silicon oxide film 15 and the silicon nitride film 14. Contact holes 16 and 17 are formed on the upper portion of 13 (source and drain) by self-alignment (self-alignment) with respect to the gate electrode 12.
[0024]
Next, as shown in FIG. 11, plugs 18 are formed inside the contact holes 16 and 17. The plug 18 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, As (arsenic)) on the silicon oxide film 15 by a CVD method, and then polishing the polycrystalline silicon film by a CMP method to contact holes. 16 and 17 are formed by leaving them inside.
[0025]
Next, as shown in FIG. 12, after depositing a silicon oxide film 19 on the silicon oxide film 15 by the CVD method, the substrate 1 is heat-treated to remove n-type impurities in the polycrystalline silicon film constituting the plug 18. By diffusing from the bottom of the contact holes 16 and 17 into the n-type semiconductor region 13 (source and drain), the resistance of the n-type semiconductor region 13 (source and drain) 9 is reduced.
[0026]
Next, a through hole 20 is formed by removing the silicon oxide film 19 above the contact hole 16 by dry etching using a photoresist film (not shown) as a mask, and then a plug 21 is inserted into the through hole 20. Form. The plug 21 is formed by depositing a TiN film and a W film on the silicon oxide film 19 by sputtering and then polishing these films by CMP to leave them inside the through holes 20.
[0027]
Next, as shown in FIG. 13, the bit line BL is formed on the silicon oxide film 19, and then the information storage capacitor element C is formed on the bit line BL, whereby the memory cell selection MISFET Qs and A memory cell composed of the information storage capacitive element C connected in series with this is substantially completed. The bit line BL is made of, for example, a W film, and the information storage capacitor element C is made of, for example, a lower electrode 22 made of polycrystalline silicon, a capacitor insulating film 23 made of tantalum oxide (Ta ₂ O ₅ ), and an upper electrode made of TiN. 24.
[0028]
Thus, according to the present embodiment, the sidewall of the gate electrode 12 (word line WL) is covered with the laminated film of the silicon nitride film 14 and the silicon oxide layer (7A or 9B) having a smaller dielectric constant. The capacity of the bit line BL to the word line can be reduced without hindering the formation of the contact holes 16 and 17 by self-alignment.
[0029]
As a result, the capacity of the bit line is reduced, so that if the stored charge amount (Cs) of the memory cell is the same, the amplitude of the voltage detected by the sense amplifier increases, the noise margin is expanded, and the refresh time interval is increased. Can be lengthened. In addition, since the refresh time interval becomes longer, power consumption can be reduced.
[0030]
Further, since the number of memory cells connected to one bit line can be increased, the number of memory arrays can be reduced. That is, since the number of sense amplifier arrays can be reduced, the chip area can be reduced and the number of chips acquired per wafer can be increased.
[0031]
(Embodiment 2)
A DRAM manufacturing method according to this embodiment will be described in the order of steps with reference to FIGS.
[0032]
First, a conductive film 6 for a gate electrode (polycrystalline silicon film 7, barrier metal film 8 and W film 9) is deposited on the gate oxide film 5 in accordance with the steps shown in FIGS. Subsequently, after the silicon nitride film 10 is deposited on the conductive film 6, the silicon nitride film 10 is patterned by dry etching using the photoresist film 11 as a mask, and the conductive film 6 is etched, as shown in FIG. For this purpose, a hard mask 10A is formed. The steps up to here are the same as those in the first embodiment.
[0033]
Next, as shown in FIG. 15, the gate electrode 12 is formed by patterning the conductive film 6 (W film 9, barrier metal film 8, and polycrystalline silicon film 7) by dry etching using the hard mask 10A as a mask. To do.
[0034]
Next, as shown in FIG. 16, after covering the upper part and side wall of the gate electrode 12 with a thin silicon film (or amorphous silicon film) 30 deposited on the substrate 1 by sputtering or CVD, as shown in FIG. Then, the substrate 1 is heat-treated to cause the W film 9 and silicon to react to convert the W film 9 in the region where the hard mask 10A is not formed into the W silicide layer 9A. At this time, due to the diffusion of silicon, the W film 9 immediately below the side wall of the hard mask 10A is also silicided to some extent.
[0035]
Further, instead of the means for covering the upper part and the side wall of the gate electrode 12 with the silicon film 30, silicon ions are implanted into the silicon oxide film 30 on the side wall of the gate electrode 12 by using an oblique ion implantation method, and then the substrate 1 is heat-treated. By doing so, the W silicide layer 9 </ b> A may be formed on a part of the side wall of the gate electrode 12.
[0036]
Next, when the upper part and the side wall of the gate electrode 12 are covered with the silicon oxide film 30, the silicon oxide film 30 is removed by wet etching or the like, and then the substrate 1 is thermally oxidized to thereby form the side wall end of the gate electrode 12. Improve the profile of the department. When this thermal oxidation is performed, as shown in FIG. 18, the W silicide layer 9A exposed on the side wall of the gate electrode 12 is oxidized to form a silicon oxide layer 9B. In the polycrystalline silicon film 7 constituting another part of the gate electrode 12, the side wall portion of the gate electrode 12 is oxidized to form a silicon oxide layer 7A.
[0037]
Next, as shown in FIG. 19, an n-type impurity, for example, P (phosphorus) is ion-implanted into the p-type well 3, and an n-type semiconductor region 13 (source, drain) is formed in the p-type well 2 on both sides of the gate electrode 12. As a result, the memory cell selecting MISFET Qs is substantially completed. Although not shown, after that, according to the steps shown in FIGS. 9 to 13 of the first embodiment, the bit line BL is formed above the memory cell selecting MISFET Qs, and then the information storage capacitor is formed above the bit line BL. Element C is formed.
[0038]
According to the present embodiment, the sidewall of the gate electrode 12 (word line WL) is covered with the laminated film of the silicon nitride film 14 and the silicon oxide layers (7A, 9B) having a smaller dielectric constant, so that contact by self-alignment is possible. The capacity of the bit line BL against the word line can be reduced without hindering the formation of the holes 16 and 17, and the same effect as in the first embodiment can be obtained.
[0039]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0040]
For example, in the first embodiment, silicon ions are implanted into the conductive film 6 (W film 9) in the region exposed by etching the silicon nitride film 10, and then the substrate 1 is heat-treated to react the W film 9 and silicon. Then, the W film 9 in the region where the hard mask 10A is not formed is converted into the W silicide layer 9A (FIGS. 4 and 5), but the thin silicon film deposited on the substrate 1 as in the second embodiment. After covering the conductive film 6 (W film 9) with the (or amorphous silicon film) 30, the substrate 1 is heat-treated to cause the W film 9 to react with silicon, and a W silicide layer is formed on a part of the side wall of the gate electrode 12. 9A may be formed.
[0041]
The present invention can be applied not only to a general-purpose DRAM but also to a system LSI in which a DRAM and a logic LSI are mixedly mounted.
[0042]
【The invention's effect】
Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0043]
According to the present invention, the sidewall of the gate electrode (word line) is covered with the laminated film of the silicon nitride film and the silicon oxide layer having a smaller dielectric constant, thereby preventing the formation of the contact hole by self-alignment. Therefore, it is possible to reduce the capacity of the bit line with respect to the word line.
[Brief description of the drawings]
FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to a first embodiment of the present invention;
FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the first embodiment of the present invention;
FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the first embodiment of the present invention;
FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the first embodiment of the present invention;
FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the first embodiment of the present invention;
6 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention; FIG.
FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the first embodiment of the present invention;
FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention;
FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention;
FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the first embodiment of the present invention;
FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention;
FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;
13 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the DRAM according to the first embodiment of the invention; FIG.
FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM which is a second embodiment of the present invention;
FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM which is a second embodiment of the present invention;
FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM which is a second embodiment of the present invention;
FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM which is a second embodiment of the present invention;
FIG. 18 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM which is a second embodiment of the present invention;
FIG. 19 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM which is a second embodiment of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation groove 3 P-type well 4 Silicon oxide film 5 Gate oxide film 6 Conductive film 7 Polycrystalline silicon film 7A Silicon oxide layer 8 Barrier metal film 9 W film 9A W silicide layer 9B Silicon oxide layer 10 Silicon nitride film 10A hard mask 11 photoresist film 12 gate electrode 13 n-type semiconductor region (source, drain)
14 Silicon nitride film 15 Silicon oxide film 16, 17 Contact hole 18 Plug 19 Silicon oxide film 20 Through hole 21 Plug 22 Lower electrode 23 Capacitor insulating film 24 Upper electrode 30 Silicon film C Information storage capacitor Qs Memory cell selection MISFET
WL Word line

Claims (4)

  Forming a plurality of gate electrodes including a refractory metal film whose sidewalls are silicided on a semiconductor substrate;
  Converting the silicidized refractory metal film side walls into a silicon oxide film;
  Forming a source or drain on the surface of the semiconductor substrate located between two adjacent gate electrodes;
  Forming a first insulating film on the semiconductor substrate including the gate electrode;
  Forming a second insulating film on the first insulating film;
  Forming a contact hole exposing the source or drain by etching using a difference in etching rate between the first insulating film and the second insulating film;
  Forming a conductive layer in the contact hole;
A method for manufacturing a semiconductor integrated circuit device, comprising:   Forming a plurality of gate electrodes including a refractory metal film whose sidewalls are silicided on the semiconductor substrate;
  Forming a plurality of gate electrodes including a refractory metal film with exposed sidewalls on the semiconductor substrate;
  Introducing silicon ions into the exposed sidewall of the refractory metal film, or covering the exposed sidewall of the refractory metal film with a silicon layer;
  2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the step of silicidizing a side wall of the refractory metal film by heat-treating the semiconductor substrate.   Forming a plurality of gate electrodes including a refractory metal film whose sidewalls are silicided on the semiconductor substrate;
  Forming a refractory metal film on the semiconductor substrate;
  Forming a mask on the refractory metal film;
  Introducing silicon ions into the refractory metal film exposed from the mask, or forming a silicon layer on the exposed surface of the refractory metal film;
  Siliciding the refractory metal film exposed from the mask and the refractory metal film located immediately below the side wall of the mask to the bottom by heat-treating the semiconductor substrate;
  2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising: etching away the silicided refractory metal film exposed from the mask using the mask as an etching mask.   4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film is a silicon nitride film, and the second insulating film is a silicon oxide film.

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