KR100449246B1 - Method for forming the gate electrode in semiconductor device - Google Patents
Method for forming the gate electrode in semiconductor device Download PDFInfo
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- KR100449246B1 KR100449246B1 KR10-2001-0084407A KR20010084407A KR100449246B1 KR 100449246 B1 KR100449246 B1 KR 100449246B1 KR 20010084407 A KR20010084407 A KR 20010084407A KR 100449246 B1 KR100449246 B1 KR 100449246B1
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- gate
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- -1 spacer nitride Chemical class 0.000 claims abstract description 19
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 239000007943 implant Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 반도체소자의 게이트 스페이서 형성방법에 있어서, 반도체기판 상에 게이트전극과 하드마스크 등으로 이루어진 게이트라인 전체에 버퍼산화막을 형성하고, 하드마스크 측벽의 버퍼산화막을 습식식각하여 제거한 후, 스페이서 질화막을 게이트라인 측벽에 형성하여 스페이서 질화막이 하드마스크에 직접 접촉되게 함으로써, 후속 비트라인 콘택 형성 시, 버퍼산화막이 손상되는 것을 방지하며, 그 결과 게이트라인과 비트라인의 쇼트 현상을 방지하여 반도체소자의 신뢰성을 향상시키도록 하는 이점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in a method of forming a gate spacer of a semiconductor device, a buffer oxide film is formed over an entire gate line including a gate electrode and a hard mask on a semiconductor substrate, and a buffer oxide film on a sidewall of a hard mask is formed. After the wet etching is removed, a spacer nitride film is formed on the sidewall of the gate line so that the spacer nitride film is in direct contact with the hard mask, thereby preventing the buffer oxide film from being damaged during subsequent bit line contact formation. There is an advantage to improve the reliability of the semiconductor device by preventing a short phenomenon.
Description
반도체소자 제조방법에 관한 것으로, 보다 상세하게는 반도체소자의 게이트 스페이서 형성방법에 있어서, 하드마스크 측벽의 버퍼산화막을 습식식각하여 제거한 후, 스페이서 질화막을 게이트라인 측벽에 형성하여 스페이서 질화막이 하드마스크에 직접 접촉되게 하여 후속 비트라인 콘택 형성 시, 버퍼산화막이 손상되는 것을 방지하여 그 결과 게이트라인과 비트라인의 쇼트 현상을 방지하여 반도체소자의 신뢰성을 향상시킬 수 있는 반도체소자의 게이트전극 형성방법에 관한 것이다.A method of manufacturing a semiconductor device, and more particularly, in a method of forming a gate spacer of a semiconductor device, after the wet etching and removal of the buffer oxide film on the sidewall of the hard mask, a spacer nitride film is formed on the sidewall of the gate line to form a spacer nitride film on the hard mask. A method for forming a gate electrode of a semiconductor device which can improve the reliability of the semiconductor device by preventing direct contact between the buffer oxide film and forming a bit line contact, thereby preventing short circuit between the gate line and the bit line. will be.
최근 게이트전극 물질로서 폴리실리콘 상부에 비저항이 낮으면서도 고온에서 텅스텐(W), 티타늄(Ti), 탄탈륨(Ta) 등의 고융점 금속을 추가한 금속 게이트전극을 형성하고 있으며, 그 중에서도 텅스텐을 사용한 금속 게이트는 소자의 고집적화에 따른 신호처리 속도 개선의 측면에서 기존 폴리사이드 게이트전극을 대체하고 있는 실정에 있다.Recently, as gate electrode materials, metal gate electrodes have been formed on top of polysilicon with high melting point metals such as tungsten (W), titanium (Ti), and tantalum (Ta) at a high temperature, with tungsten being used. Metal gates are replacing existing polyside gate electrodes in terms of improving signal processing speed due to high integration of devices.
도 1은 종래 반도체소자의 게이트전극 형성방법에 의해 형성된 게이트전극의 문제점을 나타내는 SEM 사진이다.1 is a SEM photograph showing a problem of a gate electrode formed by a gate electrode forming method of a conventional semiconductor device.
도 1에 도시된 바와 같이, 필드산화막이 형성된 반도체기판 상에 게이트산화막과 폴리실리콘막 및 금속층 등을 순차적으로 적층한 후, 노광공정 및 식각 공정에 의해 게이트전극이 패터닝되어 게이트라인이 형성된다.As illustrated in FIG. 1, a gate oxide film, a polysilicon film, a metal layer, and the like are sequentially stacked on a semiconductor substrate on which a field oxide film is formed, and then a gate electrode is patterned by an exposure process and an etching process to form a gate line.
그리고, 상기 결과물 상에 게이트 라이트 산화(Gate Light oxidation)공정을실시한 후, 엘디디(LDD : Lightly Doped Drain) 임플란트(Implant) 공정이 진행되어 소오스/드레인이 형성되었다.After the gate light oxidation process was performed on the resultant, a lightly doped drain (LDD) implant process was performed to form a source / drain.
이어서, 상기 결과물 전체에 CVD 공정으로 게이트 버퍼산화막을 형성한 후, 게이트라인 측벽에 스페이서 질화막와 스페이서 산화막을 순차적으로 형성하여 이중구조의 게이트 스페이서를 형성하였다.Subsequently, after forming the gate buffer oxide film through the CVD process, the spacer nitride film and the spacer oxide film were sequentially formed on the sidewall of the gate line to form a gate spacer having a dual structure.
그런데, 상기 종래와 같은 방법을 이용하게 되면, 후속 비트라인 콘택 식각 공정 시, 게이트 버퍼산화막이 식각되어 "A"와 같이 나칭(notching)이 발생되어 게이트라인과 비트라인 또는 스토리지 노드와 게이트라인이 쇼트(short)되는 문제점이 있었다.However, if the conventional method is used, in the subsequent bit line contact etching process, the gate buffer oxide layer is etched and notching occurs, such as "A", so that the gate line and the bit line or the storage node and the gate line are formed. There was a problem of shorting.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 반도체소자의 게이트 스페이서 형성방법에 있어서, 반도체기판 상에 게이트전극과 하드마스크 등으로 이루어진 게이트라인 전체에 버퍼산화막을 형성하고, 하드마스크 측벽의 버퍼산화막을 습식식각하여 제거한 후, 스페이서 질화막을 게이트라인 측벽에 형성하여 스페이서 질화막이 하드마스크에 직접 접촉되게 함으로써, 후속 비트라인 콘택 형성 시, 버퍼산화막이 손상되는 것을 방지하며, 그 결과 게이트라인과 비트라인의 쇼트 현상을 방지하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a buffer oxide film on an entire gate line including a gate electrode and a hard mask on a semiconductor substrate in a method of forming a gate spacer of a semiconductor device. After the wet etching and removal of the buffer oxide film on the sidewalls of the hard mask, a spacer nitride film is formed on the sidewalls of the gate line so that the spacer nitride film is in direct contact with the hard mask, thereby preventing the buffer oxide film from being damaged during subsequent bit line contact formation. As a result, an object of the present invention is to prevent shorting of gate lines and bit lines.
도 1은 종래 반도체소자의 게이트전극 형성방법에 의해 형성된 게이트전극의 문제점을 나타내는 SEM 사진이다.1 is a SEM photograph showing a problem of a gate electrode formed by a gate electrode forming method of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 게이트전극 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2E are cross-sectional views sequentially illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.
도 3은 본 발명에 따른 반도체소자의 게이트전극 형성방법에 의해 형성된 게이트전극을 나타내는 SEM 사진이다.3 is a SEM photograph showing a gate electrode formed by a method of forming a gate electrode of a semiconductor device according to the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 반도체기판 105 : 필드산화막100: semiconductor substrate 105: field oxide film
110 : 게이트전극 120 : 하드마스크110: gate electrode 120: hard mask
125 : 게이트라인 130 : 게이트 버퍼산화막125 gate line 130 gate buffer oxide film
140 : 감광막 160 : 스페이서 질화막140: photosensitive film 160: spacer nitride film
170 : 스페이서 산화막 180 : 게이트 스페이서170: spacer oxide film 180: gate spacer
상기 목적을 달성하기 위하여, 본 발명은 소정의 하부구조를 가지고 있는 반도체기판 상에 게이트전극과 하드마스크로 이루어진 게이트라인을 형성하는 단계와, 상기 결과물 전체에 게이트 라이트 옥시데이션 공정을 진행하여 게이트 버퍼산화막을 형성하는 단계와, 상기 결과물 상의 게이트전극까지 감광막을 도포한 후 그 감광막을 식각베리어로 게이트전극 상부의 게이트 버퍼산화막을 습식식각하여 제거하는 단계와, 상기 감광막을 제거한 후 스텝 커버리지가 낮은 질화막과 산화막을 순차적 적층하여 스페이서 질화막과 스페이서 산화막으로 구성된 이중구조의 게이트 스페이서를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 게이트전극 형성방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming a gate line consisting of a gate electrode and a hard mask on a semiconductor substrate having a predetermined substructure, the gate light oxidization process for the entire result of the gate buffer Forming an oxide film, applying a photoresist to the gate electrode on the resultant, and then wet etching the gate buffer oxide layer on the gate electrode with an etch barrier to remove the photoresist; and removing the photoresist, and then removing the nitride film having low step coverage. And forming a gate spacer having a dual structure consisting of a spacer nitride film and a spacer oxide film by sequentially stacking the peroxide film.
바람직하게, 본 발명은 상기 스페이서 질화막을 싱글 챔버형 LPCVD 공정 또는 PECVD 공정으로 나이트라이드막을 증착하여 형성하는 것을 특징으로 한다.Preferably, the spacer nitride film is formed by depositing a nitride film by a single chamber type LPCVD process or a PECVD process.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 게이트전극 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이며, 도 3은 본 발명에 따른 반도체소자의 게이트전극 형성방법에 의해 형성된 게이트전극을 나타내는 SEM 사진이다.2A to 2D are cross-sectional views sequentially illustrating a method of forming a gate electrode of a semiconductor device according to the present invention, and FIG. 3 is a SEM photograph showing a gate electrode formed by a method of forming a gate electrode of a semiconductor device according to the present invention. to be.
도 2a에 도시된 바와 같이, 필드산화막(105)이 형성된 반도체기판(100) 상에 게이트전극(110) 및 하드마스크(120)등을 순차적으로 적층한 후, 식각 공정에 의해 게이트전극이 패터닝되어 게이트라인(125)을 형성하며, 이때, 상기 게이트전극 (110)은 텅스텐을 사용하여 증착한다.As illustrated in FIG. 2A, the gate electrode 110 and the hard mask 120 are sequentially stacked on the semiconductor substrate 100 on which the field oxide film 105 is formed, and then the gate electrode is patterned by an etching process. A gate line 125 is formed, and in this case, the gate electrode 110 is deposited using tungsten.
또한, 상기 게이트라인(125) 형성 시, 손상된 게이트라인 측벽에 손실이 유발되어 결과물 전체에 게이트 라이트 산화(Gate Light oxidation)공정을 실시한 후, 엘디디(LDD : Lightly Doped Drain) 임플란트(Implant) 공정을 진행하여 소오스/드레인(미도시함)이 형성한다.In addition, when the gate line 125 is formed, a loss is caused in a damaged gate line sidewall, and a gate light oxidation process is performed on the entire resultant, followed by an LDD (Lightly Doped Drain) implant process. Proceed to form a source / drain (not shown).
그리고, 도 2b에 도시된 바와 같이, 상기 결과물 전체에 CVD 공정으로 게이트 버퍼산화막(130)을 형성한 후, 게이트전극(110)의 높이까지 후속 식각베리어로 사용될 감광막(140)을 도포한다.As shown in FIG. 2B, the gate buffer oxide film 130 is formed by the CVD process on the entire resultant, and then the photosensitive film 140 to be used as a subsequent etching barrier is applied to the height of the gate electrode 110.
그 후, 도 2c에 도시된 바와 같이, 상기 감광막(140)을 식각베리어로 사용해 게이트전극(110) 상부의 하드마스크(120)를 둘러싸고 있는 게이트 버퍼산화막(미도시함)을 습식식각하여 제거한다.Thereafter, as illustrated in FIG. 2C, the gate buffer oxide layer (not shown) surrounding the hard mask 120 on the gate electrode 110 is wet-etched using the photosensitive layer 140 as an etch barrier. .
이어서, 도 2d에 도시된 바와 같이, 상기 결과물 상에 스페이서 질화막(160)와 스페이서 산화막(160)을 순차적으로 형성하여 이중구조의 게이트 스페이서(180)를 형성하며, 도 3에 상기와 같은 방법에 의해 형성된 게이트전극을 이를 구체화하여 나타내고 있다.Subsequently, as shown in FIG. 2D, a spacer nitride layer 160 and a spacer oxide layer 160 are sequentially formed on the resultant to form a gate spacer 180 having a dual structure. The gate electrode formed by this is shown in detail.
또한, 상기 스페이서 질화막(160)은 스텝 커버리지가 낮은 질화물을 증착하여 형성하며, 이때, 싱글 챔버형 LPCVD 공정 또는 PECVD 공정으로 나이트라이드막을 증착하여 형성한다.In addition, the spacer nitride layer 160 is formed by depositing nitride having low step coverage, and in this case, is formed by depositing a nitride layer by a single chamber type LPCVD process or PECVD process.
상기 스페이서 질화막(160)은 후속 비트라인 콘택 식각 공정 시, 버퍼산화막이 식각되는 것을 방지하여 게이트라인과 비트라인 또는 스토리지 노드와 게이트라인이 쇼트(short)되는 현상을 방지한다.The spacer nitride layer 160 may prevent the buffer oxide layer from being etched during the subsequent bit line contact etching process, thereby preventing the gate line and the bit line or the storage node and the gate line from shorting.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 게이트전극 형성방법을 이용하게 되면, 반도체기판 상에 게이트전극과 하드마스크 등으로 이루어진 게이트라인 전체에 버퍼산화막을 형성하고, 하드마스크 측벽의 버퍼산화막을 습식식각하여 제거한 후, 스페이서 질화막을 게이트라인 측벽에 형성하여 스페이서 질화막이 하드마스크에 직접 접촉되게 함으로써, 후속 비트라인 콘택 형성 시, 버퍼산화막이 손상되는 것을 방지하며, 그 결과 게이트라인과 비트라인의 쇼트 현상을 방지하여 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.Therefore, as described above, when the gate electrode forming method of the semiconductor device according to the present invention is used, the buffer oxide film is formed on the entire gate line including the gate electrode and the hard mask on the semiconductor substrate, and the buffer of the hard mask sidewall is formed. After wet etching to remove the oxide film, a spacer nitride film is formed on the sidewall of the gate line so that the spacer nitride film is in direct contact with the hard mask, thereby preventing the buffer oxide film from being damaged during subsequent bit line contact formation. There is an effect that can prevent the short circuit of the line to improve the reliability of the semiconductor device.
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| JPH11317459A (en) * | 1998-02-05 | 1999-11-16 | Internatl Business Mach Corp <Ibm> | Manufacture of dual-gate oxide dual work function cmos |
| KR20000041749A (en) * | 1998-12-23 | 2000-07-15 | 김영환 | Method for fabrication a split gate flash eeprom cell |
| JP2001185696A (en) * | 1999-12-24 | 2001-07-06 | Hitachi Ltd | Manufacturing method of semiconductor integrated circuit device |
| JP2001203349A (en) * | 2000-01-20 | 2001-07-27 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
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| KR19990020395A (en) * | 1997-08-30 | 1999-03-25 | 김영환 | Flash Ipyrom Cell Manufacturing Method |
| JPH11317459A (en) * | 1998-02-05 | 1999-11-16 | Internatl Business Mach Corp <Ibm> | Manufacture of dual-gate oxide dual work function cmos |
| KR20000041749A (en) * | 1998-12-23 | 2000-07-15 | 김영환 | Method for fabrication a split gate flash eeprom cell |
| JP2001185696A (en) * | 1999-12-24 | 2001-07-06 | Hitachi Ltd | Manufacturing method of semiconductor integrated circuit device |
| JP2001203349A (en) * | 2000-01-20 | 2001-07-27 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
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