JP2004342979A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an element having a laminate gate structure such as a non-volatile memory in which a hole to be formed in an insulating film on the source/drain areas is made shallow, and the dimension is easily made fine. <P>SOLUTION: A control gate electrode 22 of a non-volatile memory is formed in a hole formed in an inter-layer insulating film, and a hole 22a formed in the inter-layer insulating film on source/drain areas is made shallow. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a nonvolatile memory and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, the development of LSI has been remarkable. The performance of the device has been improved based on the miniaturization of the device dimensions, and the density of the device has been increased. In addition, the applications of LSIs have become diversified, and demands for LSIs having a plurality of functions called a system-on-chip in which a memory circuit, a logic circuit, and the like are integrated into one chip according to the application are increasing.
[0003]
When an LSI in which a memory circuit and a logic circuit are mixed is manufactured, a memory cell is present in the memory circuit, and there is a portion where a manufacturing process is different from that of a normally used MOS transistor. Therefore, there is a demand for assembling a manufacturing process with consistency, including a manufacturing process of a logic circuit.
[0004]
For example, in the case of an electrically rewritable nonvolatile memory circuit called a flash memory, the structure of a gate electrode is different from the structure of a MOS transistor used in a logic circuit. That is, the nonvolatile memory circuit has a gate structure in which a floating gate electrode and a control gate electrode are stacked via a gate insulating film, and is more complicated than a logic circuit having a single gate structure. For this reason, in an LSI in which a nonvolatile memory circuit and a logic circuit are mixed, a device is devised such that the gate electrode formation process of the logic circuit is matched with one of the gate electrode formation processes of the nonvolatile memory circuit (for example, And Patent Document 1.).
[0005]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2000-23076 (page 10, FIG. 1)
[0006]
[Problems to be solved by the invention]
Although an LSI in which a nonvolatile memory circuit and a logic circuit are mixed is manufactured by using the above-described method and the like, it is required to further reduce the element size and improve the performance. However, an LSI in which a nonvolatile memory circuit and a logic circuit are mixed has a problem specific to the element structure. That is, in an LSI including only a logic circuit that does not include a nonvolatile memory circuit, since the gate electrode is a single layer, the source and drain regions formed in the interlayer insulating film and the holes in the wiring layer formed thereover are relatively small. shallow. On the other hand, when a stacked gate structure is used in a nonvolatile memory circuit, the hole is necessarily deeper. For this reason, a more advanced fine processing technology is required, and there is a problem that it is difficult to reduce the size of an LSI in which a nonvolatile memory circuit and a logic circuit are mounted.
[0007]
The present invention has been made in view of such circumstances, and a purpose of the present invention is to provide a semiconductor device having a non-volatile memory in which holes formed in an interlayer insulating film on source and drain regions are made shallow and dimensions can be easily miniaturized. And a method for manufacturing the same.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, a first invention of the present invention provides a semiconductor device, comprising: a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; A floating electrode formed, a second gate insulating film formed on the floating electrode, a control electrode formed on the second gate insulating film, and the semiconductor under the first gate insulating film A source and drain region formed in the semiconductor substrate so as to sandwich one region of the substrate, wherein the control electrode is formed at least in a hole of an interlayer insulating film provided on the second gate insulating film; Characterized by having a nonvolatile memory as described above.
[0009]
According to the present invention, in the stacked gate structure in the nonvolatile memory, the control electrode is formed in the hole formed in the interlayer insulating film, and the hole formed in the interlayer insulating film on the source and drain regions is formed. A shallower element structure is enabled. Therefore, a semiconductor device which can be easily miniaturized can be provided.
[0010]
According to a second aspect of the present invention, as a method of manufacturing a semiconductor device, a step of forming an element isolation region so as to surround an element formation region of a semiconductor substrate; and forming a first gate insulating film on the semiconductor substrate. Forming, forming a floating gate electrode film on the first gate insulating film, selectively patterning the floating gate electrode film and the first gate insulating film; Introducing a impurity into the surface region of the semiconductor substrate using the floating gate electrode film as a mask, selectively forming a second gate insulating film on the floating gate electrode film; Forming an interlayer insulating film on the second gate insulating film, selectively forming a hole in the interlayer insulating film, and forming a control electrode in the selectively formed hole. Unfortunate It characterized by having a nonvolatile memory.
[0011]
According to a third aspect of the present invention, as a method of manufacturing a semiconductor device, a step of forming a first gate insulating film on a semiconductor substrate and a step of forming a first gate electrode film on the first gate insulating film Performing the step of selectively patterning the first gate electrode film and the first gate insulating film; and using the patterned first gate electrode film and the first gate insulating film as a mask to form the semiconductor. Forming an element isolation region in the base, forming a second gate electrode film on the first gate electrode film, selectively patterning the second gate electrode film, A floating gate electrode composed of the first gate electrode film and the second gate electrode film by selectively patterning the first gate electrode film, the second gate electrode film, and the first gate insulating film; Including Forming a gate region, introducing impurities into a surface region of the semiconductor substrate using the patterned floating gate electrode as a mask, and selectively forming a second gate insulating film on the floating gate electrode Performing a step of forming an interlayer insulating film on the semiconductor substrate and the second gate insulating film; a step of selectively forming a hole in the interlayer insulating film; and forming a control electrode in the hole. And a non-volatile memory provided with the steps.
[0012]
According to the second and third aspects of the present invention, in a stacked gate structure in a nonvolatile memory, a structure is employed in which a control electrode is formed in a hole formed in an interlayer insulating film, and is formed on a source and a drain region. This allows an element structure in which a hole formed in the interlayer insulating film becomes shallow. Therefore, a semiconductor device which can be easily miniaturized can be provided.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
(First Embodiment)
1 to 7 are cross-sectional views showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps. 1A is a cross-sectional view showing a method of manufacturing a complementary insulated gate field-effect transistor according to the present embodiment in the order of steps, and FIG. 4B is a cross-sectional view showing the method for manufacturing the nonvolatile memory in this embodiment in the order of steps. FIG. 7 shows a first embodiment of the semiconductor device according to the present invention.
[0015]
First, as shown in FIGS. 1A and 1B, a P-type silicon substrate 10 is prepared as a semiconductor substrate. Next, an N-type well region 10a and a P-type well region 10b shown in FIG. 1A are formed. On the other hand, the non-volatile memory area shown in FIG. 1B is used as a P-type semiconductor area, so that a well is not usually formed. However, if necessary, a P-type well is formed.
[0016]
Subsequently, after a silicon oxide film and a silicon nitride film (not shown) are formed by a CVD method, a mask is formed by patterning the silicon oxide film and the silicon nitride film using a lithography method, a dry etching method, or the like. Further, a shallow groove is formed in a region other than the masked silicon substrate 10, and a silicon oxide film is formed in the groove while filling the groove by a CVD method. Thus, the device isolation region 11 is obtained. At this time, an element isolation region is also formed in a part of the nonvolatile memory region, but is not shown because it does not appear in the cross-sectional portion of FIG.
[0017]
Next, as shown in FIG. 2, the first gate insulating film 11 is formed to a thickness of, for example, 6 nm by a thermal oxidation method. Note that the first gate insulating film 11 is used as a gate oxide film of a complementary insulated gate field effect transistor and a tunnel oxide film of a nonvolatile memory. Therefore, when the thickness of the gate oxide film of the complementary insulated gate field effect transistor and the thickness of the tunnel oxide film of the nonvolatile memory are set to different thicknesses, the following is performed. First, oxidation is performed under one of the conditions for forming an oxide film, and then unnecessary oxide films are selectively peeled off, and then selectively oxidized under the other conditions for forming an oxide film.
[0018]
Thereafter, if necessary, channel ion implantation is performed on each region using a lithography method, an ion implantation method, or the like. Next, after forming a polycrystalline silicon film of, for example, 100 nm on the first gate insulating film 11 by a CVD method, a silicon nitride film (not shown) is formed, and the silicon nitride film is formed by a lithography method, a dry etching method, or the like. The polycrystalline silicon film is patterned as a mask, and the floating gate electrode 13 is formed in the nonvolatile memory region, and the gate electrode 13a is formed in the complementary insulated gate field effect transistor region.
[0019]
Next, an impurity is introduced by ion implantation using the floating gate electrode 13 and the gate electrode film 13a as a mask to form the extension region 14. First, the P-type well region and the nonvolatile memory region in the complementary insulated gate field-effect transistor region are covered with a mask, and the N-type well region in the complementary insulated gate field-effect transistor region is doped with boron at a dose of 1E14 cm. ^-2 ~ 1E15cm ^-2 Implant ions to a degree.
[0020]
Subsequently, the N-type well region 10b in the complementary insulated gate field effect transistor region is covered with a mask, and the P-type well region 10a and the nonvolatile memory region in the complementary insulated gate field effect transistor region are doped with arsenic at a dose of 1E14 cm. ^-2 ~ 1E15cm ^-2 Implant ions to a degree. When ion implantation is performed under different conditions in the P-type well region 10a and the non-volatile memory region in the complementary insulated gate field effect transistor region, the other regions may be covered with a mask and ion implantation may be performed. Thereafter, for example, a heat treatment is performed at 950 ° C. to activate the impurities to form the extension region 14.
[0021]
Then, as shown in FIG. 3, a post-oxidation is performed to form a silicon oxide film as the post-oxide film 15 on the gate electrode 13a, the floating gate electrode 13 and the silicon substrate 10 to a thickness of, for example, about 50 nm. A film is formed with a thickness of, for example, about 100 nm. Subsequently, a process by directional etching is performed using a dry etching method or the like so that the side peripheral wall insulating film 16 and the post-oxide film 15 remain on the side peripheral wall portion.
[0022]
Subsequently, in the complementary insulated gate field effect transistor region, the gate electrode 13a, the side peripheral wall insulating film 16 and the post-oxide film 15 are used as a mask, and in the nonvolatile memory region, the floating gate electrode 13, side peripheral wall insulating film 16 and the post-oxide film are used. Using the mask 15 as a mask, source and drain regions are formed by ion implantation or the like. First, the P-type well region 10a and the nonvolatile memory region in the complementary insulated gate field effect transistor region are covered with a mask, and the N-type well region 10b in the complementary insulated gate field effect transistor region is doped with boron at a dose of 1E15 cm. ^-2 ~ 1E16cm ^-2 Implant ions to a degree.
[0023]
Subsequently, the N-type well region 10b in the complementary insulated gate field effect transistor region is covered with a mask, and the P-type well region 10a and the nonvolatile memory region in the complementary insulated gate field effect transistor region are doped with arsenic at a dose of 1E15 cm. ^-2 ~ 1E16cm ^-2 Implant ions to a degree. When ion implantation is performed under different conditions in the P-type well region 10a and the non-volatile memory region in the complementary insulated gate field effect transistor region, the other regions may be covered with a mask and ion implantation may be performed. Thereafter, for example, a heat treatment is performed at 950 ° C. to activate the impurities to form the source and drain regions 17.
[0024]
Next, as shown in FIG. 4, a second gate insulating film 18 is formed on the floating gate electrode 13a in the nonvolatile memory region. That is, first, an ultra-thin silicon oxide film 18a of about 6 nm is formed on the floating gate electrode 13a by using the CVD method, and then an ultra-thin silicon nitride film 18b of about 4 nm is formed by using the CVD method. Further, a mask insulating film 19, which is a silicon oxide film, is formed to a thickness of about 20 nm by a CVD method. Next, the mask insulating film 19, the ultrathin silicon nitride film 18b, and the ultrathin silicon oxide film 18a are left only on the floating gate electrode 13a in the nonvolatile memory region by using a lithography method, an etching method, or the like. Is formed.
[0025]
Next, as shown in FIG. 5, a salicide electrode 20 is formed on the source and drain regions 17, and a gate salicide electrode 20a is formed on the gate electrode 13a in the complementary insulated gate field effect transistor region. That is, first, a titanium film (not shown) is formed on the silicon substrate 10 to a thickness of about 50 nm by a sputtering method. Subsequently, a heat treatment is performed at about 900 ° C. to cause a silicide reaction between silicon in the source and drain regions 17 and silicon in the gate electrode 13 a and the titanium film to form titanium silicide. Subsequently, the remaining unreacted titanium is removed by an etching method. Further, the mask insulating film 19 is removed by an etching method. As a result, a salicide electrode 20 of titanium silicide is formed on the source and drain regions 17, and a gate salicide electrode 20a of titanium silicide is formed on the gate electrode 13a in the complementary insulated gate field effect transistor region.
[0026]
Next, as shown in FIG. 6, an interlayer insulating film 21 is formed. That is, after forming a silicon oxide film on the silicon substrate 10 by using the CVD method, the surface layer is flattened by the CMP method to form the interlayer insulating film 21.
[0027]
Subsequently, as shown in FIG. 7, a hole is formed in the interlayer insulating film 21 by using a lithography method, an etching method, or the like, and then about 200 nm of Al is formed on the silicon substrate 10 while filling the hole by a sputtering method. Further, by using a lithography method, an etching method, or the like, a part of Al is left, and the control gate electrode 22 is formed on the second gate insulating film 18 in the nonvolatile memory region, and the control gate electrode 22 is formed on the source and drain regions 17. The hole electrode 22a is formed. At this time, since Al on the interlayer insulating film 21 can be formed also as a wiring, a structure in which the electrode and the wiring are integrated is adopted. Therefore, the electrodes and the wiring can be formed by the same process including the wiring in the complementary insulated gate field effect transistor.
[0028]
Thereafter, a silicon oxide film or the like (not shown) is formed on the entire surface of the silicon substrate 10. After further opening a contact hole in the silicon oxide film or the like, a metal wiring layer is formed. Further, if necessary, the formation of a silicon oxide film or the like and the formation of a metal wiring layer are repeated to form a multilayer wiring structure, and then the entire surface is covered with a surface protection film, and a pad portion is opened to include a nonvolatile memory. Complete the semiconductor device.
[0029]
According to the present embodiment, by taking a structure in which the control gate electrode in the nonvolatile memory is formed in the hole formed in the interlayer insulating film, the hole formed in the interlayer insulating film on the source and drain regions is shallow, and the electrode In addition, a semiconductor device having a nonvolatile memory which can easily form wiring and can cope with miniaturization of elements can be obtained.
[0030]
(Second embodiment)
8 to 14 are sectional views showing a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps. 1A is a cross-sectional view showing a method of manufacturing a complementary insulated gate field-effect transistor according to the present embodiment in the order of steps, and FIG. 4B is a cross-sectional view showing the method for manufacturing the nonvolatile memory in this embodiment in the order of steps. FIG. 14 shows a second embodiment of the semiconductor device according to the present invention.
[0031]
First, as shown in FIGS. 8A and 8B, a P-type silicon substrate 30 is prepared as a semiconductor substrate. Next, an N-type well region 30a and a P-type well region 30b shown in FIG. 8A are formed. On the other hand, the non-volatile memory area shown in FIG. 8B is used as a P-type semiconductor area, so that a well is not usually formed. However, if necessary, a P-type well is formed.
[0032]
Subsequently, as shown in FIG. 8A, a first gate insulating film 11 is formed to a thickness of, for example, 6 nm by a thermal oxidation method. Note that the first gate insulating film 31 is used as a gate oxide film of a complementary insulated gate field effect transistor and a tunnel oxide film of a nonvolatile memory. Thereafter, if necessary, channel ion implantation is performed on each region using a lithography method, an ion implantation method, or the like. Further, after forming a first gate electrode film 32a, which is a polycrystalline silicon film, for example, with a thickness of 100 nm by a CVD method, a silicon nitride film (not shown) is formed, and the silicon nitride film is masked using a lithography method, a dry etching method or the like. Then, the first gate electrode film 32a and the gate insulating film 31 are patterned, and a groove is also formed in the silicon substrate 30 by directional etching. Subsequently, a silicon oxide film is formed on the entire surface of the silicon substrate 30 including the groove by using the CVD method, and subsequently, the silicon formed in the groove of the silicon substrate while planarizing the surface by using the CMP method, the etching method, or the like. The oxide film is left to form the element isolation region 33. At this time, an element isolation region is also formed in a part of the nonvolatile memory region, but is not shown in the cross-sectional portion of FIG.
[0033]
Next, after a second gate electrode film 32b, which is a polycrystalline silicon film, is formed to a thickness of, for example, 100 nm by a CVD method, using a silicon nitride film or the like (not shown) as a mask, the lithography method and the etching method are used to form FIG. Patterning is performed as shown in FIG. The structure in which the first gate electrode film 33 and the second gate electrode film 32b are stacked functions as the gate electrode 32c in the complementary insulated gate field effect transistor region and as the floating gate electrode 32 in the nonvolatile memory region. .
[0034]
Next, an impurity is introduced by ion implantation using the floating gate electrode 32 and the gate electrode 32c as a mask to form an extension region. First, the P-type well region 30a and the nonvolatile memory region in the complementary insulated gate field effect transistor region are covered with a mask, and the N-type well region 30b in the complementary insulated gate field effect transistor region is doped with boron at a dose of 1E14 cm. ^-2 ~ 1E15cm ^-2 Implant ions to a degree.
[0035]
Subsequently, the N-type well region 30b in the complementary insulated gate field effect transistor region is covered with a mask, and the P-type well region and the nonvolatile memory region in the complementary insulated gate field effect transistor region are dosed with arsenic at a dose of 1E14 cm. ^-2 ~ 1E15cm ^-2 Implant ions to a degree. When ion implantation is performed under different conditions in the P-type well region 30a and the non-volatile memory region in the complementary insulated gate field effect transistor region, the other regions may be covered with a mask, and the ion implantation may be performed. Thereafter, for example, a heat treatment is performed at 950 ° C. to activate the impurities to form the extension regions 34.
[0036]
Next, as shown in FIG. 10, post-oxidation is performed to form a post-oxide film 35 as a silicon oxide film on the gate electrode 32c, the floating gate electrode 32, and the silicon substrate 30 to a thickness of, for example, about 50 nm. A nitride film is formed, for example, to about 100 nm. Subsequently, directional etching is performed using a dry etching method or the like so that the side peripheral wall insulating film 36 and the post-oxide film 35, which are silicon nitride films, remain on the side peripheral wall.
[0037]
Subsequently, in the complementary insulated gate field effect transistor region, the gate electrode 32c, the side peripheral wall insulating film 36 and the post-oxide film 35 are used as a mask, and in the nonvolatile memory region, the floating gate electrode 32, side peripheral wall insulating film 36 and the post-oxide film are used. Using the mask 35 as a mask, the source and drain regions 37 are formed by ion implantation or the like. First, the P-type well region 30a and the nonvolatile memory region in the complementary insulated gate field effect transistor region are covered with a mask, and the N-type well region 30b in the complementary insulated gate field effect transistor region is doped with boron at a dose of 1E15 cm. ^-2 ~ 1E16cm ^-2 Implant ions to a degree.
[0038]
Subsequently, the N-type well region 30b in the complementary insulated gate field-effect transistor region is covered with a mask, and the P-type well region 30a in the complementary insulated gate field-effect transistor region and the nonvolatile memory region are dosed with arsenic at a dose of 1E15 cm. ^-2 ~ 1E16cm ^-2 Implant ions to a degree. When ion implantation is performed under different conditions for the P-type well region 30a and the non-volatile memory region in the complementary insulated gate field effect transistor region, the other regions may be covered with a mask and the ion implantation may be performed. Thereafter, for example, a heat treatment is performed at 950 ° C. to activate the impurities to form the source and drain regions 37.
[0039]
Next, as shown in FIG. 11, a second gate insulating film 38 is formed on the floating gate electrode 32 in the nonvolatile memory region. That is, first, an ultra-thin silicon oxide film 38a of about 6 nm is formed on the floating gate electrode 32 by using the CVD method, and then an ultra-thin silicon nitride film 38b of about 4 nm is formed by using the CVD method. Further, using a CVD method, a mask insulating film 38c, which is a silicon oxide film, is formed to a thickness of about 20 nm. Next, the mask insulating film 38c, the ultra-thin silicon nitride film 38b, and the ultra-thin silicon oxide film 38a are left only on the floating gate electrode 32 in the nonvolatile memory region by using a lithography method, an etching method, or the like. Of the gate insulating film 38 is formed.
[0040]
Next, as shown in FIG. 12, a salicide electrode 39 is formed on the source and drain regions 37, and a gate salicide electrode 39a is formed on the gate electrode 32c in the complementary insulated gate field effect transistor region. That is, first, a titanium film (not shown) is formed on the silicon substrate 30 to a thickness of about 50 nm by a sputtering method. Subsequently, heat treatment is performed at about 900 ° C. to cause a silicide reaction between the silicon in the source and drain regions 37 and the silicon in the gate electrode 32 c and the titanium film to form titanium silicide. Subsequently, the remaining unreacted titanium is removed by an etching method. Further, the mask insulating film 38c is removed by an etching method. Thus, a salicide electrode 39 made of titanium silicide is formed on the source and drain regions 37, and a gate salicide electrode 41a made of titanium silicide is formed on the gate electrode 39a in the complementary insulated gate field effect transistor region.
[0041]
Next, as shown in FIG. 13, an interlayer insulating film 40 is formed. That is, after forming a silicon oxide film on the silicon substrate 10 by using the CVD method, the surface layer is flattened by the CMP method to form the interlayer insulating film 40.
[0042]
Subsequently, as shown in FIG. 14, a hole is formed in the interlayer insulating film by using a lithography method, an etching method, or the like, and then about 200 nm of Al is formed on the silicon substrate 30 by filling the hole with the sputtering method. Further, by using a lithography method, an etching method, or the like, a part of Al is left, a control gate electrode 41 is formed in a hole above the second gate insulating film 38 in the nonvolatile memory region, and a source and drain region 37 is formed. A hole electrode 41a is formed thereon. At this time, since Al on the interlayer insulating film 40 can be formed also as a wiring, a structure in which the electrode and the wiring are integrated is adopted. Therefore, the electrodes and the wiring can be formed by the same process including the wiring in the complementary insulated gate field effect transistor.
[0043]
Thereafter, a silicon oxide film or the like (not shown) is formed on the entire surface of the silicon substrate 30. After further opening a contact hole in the silicon oxide film or the like, a metal wiring layer is formed. Further, if necessary, the formation of a silicon oxide film or the like and the formation of a metal wiring layer are repeated to form a multilayer wiring structure, and then the entire surface is covered with a surface protection film, and a pad portion is opened to include a nonvolatile memory. Complete the semiconductor device.
[0044]
According to the present embodiment, by taking a structure in which the control gate electrode in the nonvolatile memory is formed in the hole formed in the interlayer insulating film, the hole formed in the interlayer insulating film on the source and drain regions is shallow, and the electrode In addition, a semiconductor device having a nonvolatile memory which can easily form wiring and can cope with miniaturization of elements can be obtained.
[0045]
Further, since the element isolation region is formed after the formation of the first gate insulating film, a stable operation as a nonvolatile memory can be obtained.
[0046]
The present invention is not limited to the above-described embodiment at all, and can be implemented with various modifications without departing from the gist of the present invention.
[0047]
For example, if high-concentration N-type silicon conventionally used as a material for the control gate electrode is used, there is a possibility that application as a semiconductor device can be relatively easily performed. When other materials are used, not limited to aluminum, metals such as copper, gold, silver, tungsten, molybdenum, and titanium; metal silicides such as tungsten silicide, molybdenum silicide, and titanium silicide; and high-concentration P-type impurities May be doped silicon.
[0048]
In addition, by laying the barrier metal under the above-described material, advantages such as suppressing the reaction of the holes with silicon can be obtained. In this case, a structure in which a metal such as tungsten, molybdenum, or titanium, a metal silicide such as tungsten silicide, molybdenum silicide, or titanium silicide, or a metal nitride such as titanium nitride or tungsten nitride may be formed as the barrier metal.
[0049]
Further, the gate insulating films such as the first gate insulating film and the second gate insulating film are not limited to the silicon oxide film and the silicon nitride film, but may be a silicon oxynitride film containing both oxygen and nitrogen in various compositions. Alternatively, a metal oxide film such as a hafnium oxide film or a titanium oxide film, a composite film of these films, or a film using a laminated structure may be used.
[0050]
Further, as the semiconductor substrate, an SOI substrate, a compound semiconductor substrate such as GaAs, or the like can be used other than the silicon substrate.
[0051]
Further, it is needless to say that the stacked gate structure can be applied not only to the nonvolatile memory but also to other types of devices. In addition, circuits configured in the semiconductor device can include various logic circuits, peripheral circuits, and the like.
[0052]
【The invention's effect】
As described in detail above, according to the present invention, by forming a control gate electrode in a nonvolatile memory in a hole formed in an interlayer insulating film, the control gate electrode is formed in the interlayer insulating film on the source and drain regions. Thus, a semiconductor device having a non-volatile memory capable of easily forming electrodes and wiring and capable of responding to miniaturization of elements can be obtained.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 2 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 3 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 4 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 5 is a cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 6 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 7 is a sectional view illustrating a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 8 is a sectional view illustrating a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 9 is a sectional view showing a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 10 is a sectional view showing a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 11 is a sectional view showing a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 12 is a cross-sectional view showing a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 13 is a sectional view illustrating a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 14 is a sectional view illustrating a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
[Explanation of symbols]
10, 30 silicon substrate
10a, 30a P-type well region
10b, 30b N-type well region
11, 33 element isolation region
12, 31 First gate insulating film
13, 32 Floating gate electrode
13a, 32c Gate electrode
14, 34 Extension area
15, 35 Post-oxide film
16, 36 Side wall insulating film
17, 37 source and drain regions
18, 38 Second gate insulating film
18a, 38a Ultra-thin silicon nitride film
18b, 38b Ultra-thin silicon oxide film
19, 38c Mask insulating film
20, 39 Salicide electrode
20a, 39a Gate salicide electrode
21, 40 interlayer insulating film
22, 41 control gate electrode
22a, 41a Contact hole electrode
32a first gate electrode film
32b second gate electrode film

Claims (18)

A semiconductor substrate;
A first gate insulating film formed on the semiconductor substrate,
A floating electrode formed on the first gate insulating film;
A second gate insulating film formed on the floating electrode;
A control electrode formed on the second gate insulating film;
A source and a drain region formed in the semiconductor base so as to sandwich one region of the semiconductor base under the first gate insulating film;
A semiconductor device, wherein the control electrode has at least a nonvolatile memory formed in a hole of an interlayer insulating film provided on the second gate insulating film. 2. The semiconductor device according to claim 1, wherein the material of the control electrode is made of the same material as a wiring connected to the control electrode. 3. The semiconductor device according to claim 1, wherein the control electrode has a stacked structure including a plurality of materials. 4. 4. The semiconductor device according to claim 1, wherein the control electrode includes high-concentration N-type silicon. 5. The semiconductor device according to claim 1, wherein the floating electrode has a stacked structure of a first gate electrode film and a second gate electrode film. 6. 6. The semiconductor device according to claim 1, wherein the second gate insulating film formed on the floating electrode has a stacked structure of a silicon oxide film and a silicon nitride film. The semiconductor device according to claim 1, wherein a memory circuit is configured by the nonvolatile memory, and at least a logic circuit is included in addition to the memory circuit. The logic circuit is composed of a complementary insulated gate field effect transistor, and the gate electrode of the complementary insulated gate field effect transistor has the same conductivity type as the channel conductivity type of each transistor. The semiconductor device according to claim 7, wherein the gate electrode has an N-type conductivity. 9. The method according to claim 7, wherein the thickness of the first gate insulating film of the nonvolatile memory is different from the thickness of the gate insulating film of the complementary insulated gate field effect transistor in the logic circuit. Semiconductor device. Forming an element isolation region so as to surround an element formation planned region of the semiconductor substrate;
Forming a first gate insulating film on the semiconductor substrate;
Forming a floating gate electrode film on the first gate insulating film;
Selectively patterning the floating gate electrode film and the first gate insulating film;
Introducing impurities into the surface region of the semiconductor substrate using the patterned floating gate electrode film as a mask,
Selectively forming a second gate insulating film on the floating gate electrode film;
Forming an interlayer insulating film on the semiconductor substrate and the second gate insulating film; and selectively forming holes in the interlayer insulating film;
Forming a control electrode in the hole formed selectively. A method for manufacturing a semiconductor device, comprising: Forming a first gate insulating film on the semiconductor substrate;
Forming a first gate electrode film on the first gate insulating film;
Selectively patterning the first gate electrode film and the first gate insulating film;
Forming an element isolation region in the semiconductor substrate using the patterned first gate electrode film and the first gate insulating film as a mask;
Forming a second gate electrode film on the first gate electrode film;
Selectively patterning the second gate electrode film;
The first gate electrode film, the second gate electrode film, and the first gate insulating film are selectively patterned to form a floating structure including the first gate electrode film and the second gate electrode film. Forming a gate region including a gate electrode;
Introducing an impurity into the surface region of the semiconductor substrate using the patterned floating gate electrode as a mask,
Selectively forming a second gate insulating film on the floating gate electrode;
Forming an interlayer insulating film on the semiconductor substrate and the second gate insulating film; and selectively forming holes in the interlayer insulating film;
Forming a control electrode in the hole. The method of manufacturing a semiconductor device according to claim 10, wherein a wiring connected to the control electrode is also formed in the step of forming the control electrode. 13. The method according to claim 10, wherein the control electrode is formed by laminating a plurality of conductive materials. 14. The semiconductor device according to claim 10, wherein the control electrode is formed of a material containing high-concentration N-type silicon. 15. The semiconductor device according to claim 10, wherein the second gate insulating film on the floating electrode is formed by stacking a silicon oxide film and a silicon nitride film. Manufacturing method. 16. The semiconductor device according to claim 10, wherein a memory circuit is formed by forming the non-volatile memory, and at least a logic circuit is formed in addition to the memory circuit. Production method. The logic circuit is formed by a complementary insulated gate field effect transistor, and the gate electrodes of the P-channel and N-channel transistors of the complementary insulated gate field effect transistor have impurities of the same conductivity type as those of the respective channels. 17. The method according to claim 16, wherein an N-type impurity is introduced into the floating gate electrode of the nonvolatile memory. After the step of forming the first gate insulating film, the first gate insulating film is selectively peeled off, and a gate insulating film of the logic circuit is selectively formed on the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 16, wherein:

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