JP2010062499A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of a CIS transistor using a high permittivity film as a gate insulating film. <P>SOLUTION: On the principal plane of a substrate 1, the active region of a pMIS transistor and the active region of an nMIS transistor insulated and separated from each other by an element isolation region 2 are provided. A hafnium-based oxide film 5 configuring the gate insulating film of the nMIS transistor is provided on the active region of the nMIS transistor so as to be on the element isolation region 2, and a hafnium-based oxide film 9 configuring the gate insulating film of the pMIS transistor comprising a material different from that of the hafnium-based oxide film 5 is brought into contact with the hafnium-based oxide film 5 on the element isolation region 2 and provided on the active region of the pMIS transistor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device including an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a p-channel MISFET.

  As one means for improving transistor drive capability such as an increase in on-current while miniaturizing and integrating MISFETs (hereinafter referred to as MIS transistors) constituting a semiconductor integrated circuit, a gate insulating film is thinned. However, when the gate insulating film is composed only of silicon oxide that has been used in the past, if the film thickness becomes too thin, electrons will pass through the gate insulating film due to a quantum effect called direct tunneling. An electric current increases and it does not function as an insulating film.

  Therefore, a high dielectric constant (high-k) material having a dielectric constant higher than that of silicon oxide has been used for the gate insulating film. This is because when the gate insulating film is made of a high dielectric constant material, the actual physical film thickness (the dielectric constant of the high dielectric constant material / the dielectric constant of the silicon oxide) is the same even if the insulation capacitance in terms of the silicon oxide film thickness is the same. This is because the leakage current can be reduced while maintaining the driving capability. Therefore, by using a high dielectric constant film having a physical film thickness that functions as an insulating film, the transistor characteristics can be improved by making the EOT (Equivalent Oxide Thickness) of the gate insulating film thinner (smaller). It is illustrated.

  In addition, when the gate electrode is composed only of conventionally used polysilicon, a phenomenon occurs in which the polysilicon is depleted at the interface between the gate insulating film and the gate electrode. Since the depleted polysilicon film functions as a capacitive insulating film, even if the EOT is made thinner using a high dielectric constant material, the thickness of the gate insulating film is substantially increased by the amount of depleted polysilicon. It will be thick. For this reason, since the capacity between the gate electrode and the semiconductor substrate is reduced, it is difficult to ensure sufficient on-current.

  Therefore, when a high dielectric constant material is used for the gate insulating film, it has been studied to use a metal instead of polysilicon as the gate electrode material disposed thereon. Note that the gate electrode material of the n-channel MIS transistor (hereinafter referred to as nMIS transistor) and the p-channel MIS transistor (hereinafter referred to as pMIS transistor) is composed of the same metal (single metal), and is composed of different metals. There is a case (dual metal).

  Furthermore, when considering the high speed and low power consumption of the transistor, a low threshold voltage is required, and therefore, it is necessary to design to a desired threshold voltage. However, when a high dielectric constant material is used for the gate insulating film, there is a problem that controllability of the threshold voltage becomes difficult due to a phenomenon (Fermi level pinning) in which the Fermi level of electrons in the insulating film is fixed. Since the threshold voltage greatly depends on the effective work function, the effective work function may be controlled in order to obtain a desired threshold voltage. This effective work function is different from the physical work function due to various factors of the MIS structure. For this reason, different high dielectric constant materials (dual high-k) are used for the gate insulating film materials of the nMIS transistor and the pMIS transistor to adjust the respective threshold values.

In SCSong et al., Symp. VLSI Tech., Dig., Pp.13-14, 2006 (Non-patent Document 1), in a CMIS (Complementary MIS) transistor, the gate insulating film structure is dual high-k, A manufacturing technique using a dual metal electrode structure is disclosed.
SCSong et al., Symp. VLSI Tech., Dig., Pp.13-14, 2006

  The present inventors have studied a semiconductor device in which different high dielectric constant materials (dual high-k) are used as the gate insulating film materials of the nMIS transistor and the pMIS transistor. Below, the problems found by the present inventors will be described with reference to the drawings. 51 to 54 are cross-sectional views schematically showing main parts of the semiconductor device in the manufacturing process studied by the present inventors. Each figure shows an nMIS region in which an nMIS transistor is formed and a pMIS region in which a pMIS transistor is formed so as to correspond to each other.

  In the case where the gate insulating films of the nMIS transistor and the pMIS transistor are dual high-k, it is conceivable that after forming one gate insulating film material film first, another gate insulating film material film is formed.

  As shown in FIG. 51, the active region of the pMIS transistor (configured in the n well 3) and the active region of the nMIS transistor (configured in the p well 4) isolated from each other by the element isolation region 2 having the width W ′. A hafnium-based oxide film 5 (for example, an HfMgO film) that forms a gate insulating film of a pMIS transistor is formed on a main surface of a semiconductor substrate (hereinafter referred to as a substrate) 1 having a). Next, after forming a protective film 6 for protecting the hafnium-based oxide film 5 and a hard mask 7 on the protective film 6, a resist mask 8 is formed so as to cover the entire active region of the pMIS transistor in the element isolation region 2. To do. Next, the hard mask 7 is etched using the resist mask 8. Thereafter, after removing the resist mask 8, the protective film 6 and the hafnium-based oxide film 5 are etched using the etched hard mask 7, as shown in FIG. The hard mask 7, the protective film 6, and the hafnium-based oxide film 5 remain so as to cover the entire active region.

  Subsequently, as shown in FIG. 52, a hafnium-based oxide film 9 (for example, an HfAlO film) made of a material different from the hafnium-based oxide film 5 constituting the gate insulating film of the nMIS transistor is formed on the main surface of the substrate 1. . Next, after forming a protective film 10 for protecting the hafnium-based oxide film 9 and a hard mask 11 on the protective film 10, a resist mask 12 is formed so as to cover the entire active region of the nMIS transistor in the element isolation region 2. To do.

  Next, the hard mask 11 is etched using the resist mask 12. Thereafter, after removing the resist mask 12, the protective film 10 is etched using the etched hard mask 11, so as to cover the entire active region of the nMIS transistor in the element isolation region 2, as shown in FIG. The hard mask 11 and the protective film 10 remain.

  Next, the hard masks 7 and 11 are removed, and the hafnium-based oxide film 9 in the pMIS region is removed, and then the protective films 6 and 10 are removed, as shown in FIG. As a result, the hafnium-based oxide film 5 is provided on the n-well 3 constituting the active region of the pMIS transistor in relation to the element isolation region 2, and the hafnium-based oxide film 9 is related to the element isolation region 2 in the nMIS transistor. It is provided on the p well 4 constituting the active region. Note that the hafnium-based oxide film 5 and the hafnium-based oxide film 9 are not in contact with each other on the element isolation region 2. That is, there is a region where no gate insulating film exists on the element isolation region 2.

  Next, as shown in FIG. 54, after forming a metal film 13 (for example, titanium nitride film) constituting the gate electrode material and a polysilicon film 14 on the main surface of the substrate 1, the gate electrode G is formed by patterning. Form. Thereafter, a semiconductor region to be a source / drain region is formed on the main surface of the substrate 1 in alignment with the gate electrode G.

  Here, for example, when the hard masks 7 and 11 shown in FIG. 53 are removed and the protective films 6 and 10 are further removed, the element isolation region 2 is shaved off at the boundary between the nMIS region and the pMIS region. May end up. 55 is a perspective view schematically showing a main part of the semiconductor device in which the shaving 101 is generated in the element isolation region 2, and FIG. 56 is a plan view schematically showing the semiconductor device. In these drawings, a p-type semiconductor region 18 serving as a source / drain region of a pMIS transistor and an n-type semiconductor region 19 serving as a source / drain region of an nMIS transistor formed in alignment with the gate electrode G are shown. Yes.

  For example, when an n-type impurity (for example, phosphorus or arsenic) is implanted into the main surface of the substrate 1 in order to form the n-type semiconductor region 19 in a state where the shaving 101 is generated in the element isolation region 2, below the element isolation region 2. In some cases, the n-type impurity reaches the substrate 1 and the semiconductor region 102 is formed. In this case, a parasitic MIS transistor is formed. If a parasitic MIS transistor is formed, it may cause a malfunction, which may reduce the reliability of the semiconductor device.

  Further, the region covered by the resist mask 8 shown in FIG. 51 and the resist mask 12 shown in FIG. 52 has a non-overlapping region V ′. This is due to a problem in device characteristics such that when overlapped, a region in which the height of the gate formed in the subsequent process is locally high is generated. Therefore, the device structure has no overlap region. Non-Patent Document 1 discloses a CMIS transistor formed without overlapping and having a gate insulating film structure of dual high-k and a gate electrode structure of dual metal.

  However, in order to cope with future miniaturization / reduction of the semiconductor device, it is necessary to reduce the width of the element isolation region (indicated by reference numeral W ′ in FIGS. 51 and 52). That is, it is necessary to reduce the area of the semiconductor device by reducing the width of the element isolation region while solving the problem in device characteristics.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  Another object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, an element isolation region provided on the main surface of the semiconductor substrate, and an insulating isolation provided on the main surface of the semiconductor substrate. A first active region and a second active region. Further, a first gate insulating film of a first MIS transistor (for example, an nMIS transistor) provided on the first active region so as to be related to the element isolation region, the first gate insulating film, and the element isolation region And a second gate insulating film of a second MIS transistor (for example, a pMIS transistor) which is made of a material different from that of the first gate insulating film and is provided on the second active region. Furthermore, a first gate electrode of the first MIS transistor provided on the first gate insulating film and a second gate electrode of the second MIS transistor provided on the second gate insulating film are provided. .

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to this embodiment, the reliability of the semiconductor device can be improved. In addition, the semiconductor device can be reduced in size.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof may be omitted. In the drawings for explaining the following embodiments, hatching may be given even in plan views for easy understanding of the configuration.

(Embodiment 1)
In this embodiment, a case where the present invention is applied to a semiconductor device provided with SRAM (static random access memory) will be described.

  FIG. 1 is a plan view schematically showing the main part (SRAM cell) of the semiconductor device in the present embodiment, and FIG. 2 is a cross-sectional view schematically showing the semiconductor device along the line AA ′ in FIG. 3 is a cross-sectional view schematically showing the semiconductor device taken along line BB ′ of FIG. In FIG. 1, in order to clarify the relationship between the gate electrode G and the n well 3 and the p well 4 constituting the active region, a part of the interlayer insulating film 22 as shown in FIGS. 2 and 3 is omitted. As shown. Although not shown in FIGS. 2 and 3, the semiconductor device in this embodiment may have a multilayer wiring structure, and a protective film (passivation film) is provided on the outermost surface. The pMIS region shown in FIGS. 2 and 3 is a region where the pMIS transistor Qp is formed, and the nMIS region is a region where the nMIS transistor Qn is formed.

  First, the layout configuration of the SRAM in this embodiment will be described. As shown in FIG. 1, a semiconductor substrate (hereinafter referred to as a substrate) 1 is divided into a plurality of active regions by element isolation regions 2. In FIG. 1, n well 3 (p-type semiconductor region 18) is shown as an active region of pMIS transistor Qp, and p well 4 (n-type semiconductor region 19) is shown as an active region of nMIS transistor Qn. Has been.

  In the n-well 3 constituting the pMIS transistor Qp, a p-type semiconductor region (source / drain) 18 is formed by implanting a p-type impurity such as boron. A gate electrode G is formed on the n-well 3 between the source region and the drain region via a gate insulating film. Similarly, an n-type semiconductor region (source / drain) 19 is formed in the p-well 4 constituting the nMIS transistor Qn by introducing an n-type impurity such as phosphorus or arsenic. A gate electrode G is formed on the p-well 4 between the source region and the drain region via a gate insulating film. In FIG. 1, the gate electrode G extends in a second direction (horizontal direction in the drawing) that intersects the first direction (vertical direction in the drawing) in which the active region extends.

  In the SRAM, in addition to the formation of a plurality of memory cells made up of a plurality of MIS transistors, a substrate potential supply unit for obtaining a potential in terms of the structure of the SRAM is formed, and these are formed by contacts 24 and wirings 25 (see FIG. 3). It is electrically connected via.

  Next, the configuration of the pMIS transistor Qp in the present embodiment will be described. As shown in FIGS. 2 and 3, an n well 3 is formed in the pMIS region of the substrate 1 made of, for example, p-type single crystal silicon. The pMIS transistor Qp has a gate electrode G on the n-well 3 (substrate 1) via a hafnium-based oxide film 5 constituting a gate insulating film.

The gate insulating film of the pMIS transistor Qp has a higher dielectric constant than silicon oxide (SiO ₂ ) provided on the main surface (element formation surface) of the substrate 1, and is an HfAlO film containing a metal element aluminum (Al) ( It consists of a hafnium-based oxide film 5). In this way, by using the hafnium-based oxide film 5 for the gate insulating film, the leakage current is suppressed and the MIS transistor is miniaturized and integrated as compared with the case where the gate insulating film is composed only of the silicon oxide film. In addition, transistor driving capability such as an increase in on-current can be improved. A silicon oxide (SiO ₂ ) film may be provided as an interface layer between the substrate 1 and the hafnium-based oxide film 5. Further, the HfAlO film constituting the hafnium-based oxide film 5 may be a HfAlON film having a structure containing nitrogen (N).

  Further, the hafnium-based oxide film 5 containing the metal element is used as a gate insulating film of the pMIS transistor Qp regardless of whether any metal element of titanium (Ti) or tantalum (Ta) is contained in addition to aluminum. be able to. By including a metal element in the hafnium-based oxide film, the effective work function can be controlled, and the pMIS transistor Qp can be configured. By setting the effective work function near the conduction band of silicon (near 5.2 eV), the threshold voltage of the pMIS transistor Qp can be lowered.

  The gate electrode G is made of a conductive material including metal, and a metal film 13 made of a titanium nitride (TiN) film on the gate insulating film (hafnium-based oxide film 5) of the pMIS transistor Qp, and a metal A polysilicon film 14 is provided on the film 13. A silicided silicide film 21 (for example, a nickel silicide film or a cobalt silicide film) is formed on the surface of the gate electrode G (polysilicon film 14).

  The metal film 13 is in direct contact with the gate insulating film, and is mainly used for adjusting the threshold voltage of the pMIS transistor Qp. On the other hand, the polysilicon film 14 is mainly used for reducing the resistance of the gate electrode G. Further, sidewalls 20 are formed on the sidewalls on both sides of the gate electrode G. The sidewall 20 is formed of an insulating film such as a silicon nitride film.

  A p-type semiconductor region (source / drain) 18 provided in alignment with the gate electrode G is formed in the n-well 3 immediately below the sidewall 20. The p-type semiconductor region 18 is an impurity region formed by introducing a p-type impurity such as boron (B) into the substrate 1. A silicide film 21 is formed on the surface of the p-type semiconductor region 18 so as to be aligned with the sidewall 20 in order to improve the connectivity with the contact 24. Thus, the pair of p-type semiconductor regions 18 form the source region and the drain region of the pMIS transistor Qn.

  Next, the configuration of the nMIS transistor Qn in the present embodiment will be described. As shown in FIGS. 2 and 3, a p-well 4 is formed in the nMIS region of the substrate 1 made of, for example, p-type single crystal silicon. The nMIS transistor Qn has a gate electrode G on the p well (substrate 1) through a hafnium-based oxide film 9 constituting a gate insulating film.

The gate insulating film of the nMIS transistor Qn has a dielectric constant higher than that of silicon oxide (SiO ₂ ) provided on the main surface (element formation surface) of the substrate 1, and is an HfMgO film containing a metal element magnesium (Mg) ( It consists of a hafnium-based oxide film 9). In this way, by using a hafnium-based oxide film for the gate insulating film, the leakage current is suppressed and the MIS transistor is miniaturized and integrated as compared with the case where the gate insulating film is composed of only a silicon oxide film. Transistor driving capability such as an increase in on-current can be improved. A silicon oxide (SiO ₂ ) film may be provided as an interface layer between the substrate 1 and the hafnium-based oxide film 9. Further, the HfMgO film constituting the hafnium-based oxide film 9 may be a HfMgON film having a structure containing nitrogen (N).

  In addition, the hafnium-based oxide film 9 containing the metal element may contain any metal element of lanthanum (La), gadolinium (Gd), or yttrium (Y) in addition to magnesium. It can be used as a gate insulating film. By including a metal element in the hafnium-based oxide film, the effective work function can be controlled and the nMIS transistor Qn can be configured. By setting the effective work function in the vicinity of the silicon conduction band (near 4.1 eV), the threshold voltage of the nMIS transistor Qn can be lowered.

  The gate electrode G is made of a conductive material including metal, and a metal film 13 made of a titanium nitride (TiN) film on the gate insulating film (hafnium-based oxide film 9) of the nMIS transistor Qn, and a metal A polysilicon film 14 is provided on the film 13. A silicided silicide film 21 (for example, a nickel silicide film or a cobalt silicide film) is formed on the surface of the gate electrode G (polysilicon film 14).

  The metal film 13 is in direct contact with the gate insulating film, and is mainly used for adjusting the threshold voltage of the nMIS transistor Qn. On the other hand, the polysilicon film 14 is mainly used for reducing the resistance of the gate electrode G. Further, sidewalls 20 are formed on the sidewalls on both sides of the gate electrode G. The sidewall 20 is formed of an insulating film such as a silicon nitride film.

  An n-type semiconductor region (source / drain) 19 provided in alignment with the gate electrode G is formed in the p-well 4 immediately below the sidewall 20. The n-type semiconductor region 19 is an impurity region formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into the substrate 1. A silicide film 21 is formed on the surface of the n-type semiconductor region 19 in alignment with the sidewall 20 in order to improve the connectivity with the contact 24. Thus, the source region and the drain region of the nMIS transistor Qn are formed by the pair of n-type semiconductor regions 19.

  As described above, the semiconductor device in the present embodiment includes the substrate 1, the element isolation region 2 provided on the main surface of the substrate 1, and the main surface of the substrate 1, which are insulated from each other by the element isolation region 2. N well 3 and p well 4 constituting the active region of pMIS transistor Qp and nMIS transistor Qn, respectively, and the gate insulating film (hafnium-based oxide film 5) of pMIS transistor Qp provided on n well 3 And a gate insulating film (hafnium-based oxide film 9) of the nMIS transistor Qn provided on the p-well 4. As shown in FIG. 2, the hafnium-based oxide film 5 and the hafnium-based oxide film 9 are formed of the gate insulating film (hafnium-based oxide film 5) of the pMIS transistor Qp provided on the n-well 3 so as to be related to the element isolation region 2. ) And the gate insulating film (hafnium-based oxide film) of the nMIS transistor Qn that is in contact with the hafnium-based oxide film 5 on the element isolation region 2 and is made of a material different from the hafnium-based oxide film 5 provided on the p-well 4. 9). Furthermore, the gate electrode G of the pMIS transistor provided on the hafnium-based oxide film 5 and the gate electrode G of the nMIS transistor Qn provided on the hafnium-based oxide film 9 are provided.

  As described above, the nMIS transistor Qn is provided in the nMIS region of the substrate 1, and the pMIS transistor Qp is provided in the pMIS region of the substrate 1. Further, by configuring the CMIS transistor from the nMIS transistor Qn and the pMIS transistor Qp each having a hafnium-based oxide film made of a different material as a gate insulating film, high performance of the semiconductor device can be achieved. Specifically, the threshold of the CMIS transistor can be reduced, and a CMIS transistor having a high on-state current and low power consumption can be realized.

  Further, the gate insulating film (hafnium-based oxide film 5) of the pMIS transistor Qp and the gate insulating film (hafnium-based oxide film 9) of the nMIS transistor Qn are in contact with each other on the element isolation region 2, in other words, the element On the isolation region 2, there is a region having the composition of both the hafnium-based oxide film 5 and the hafnium-based oxide film 9. Since at least the hafnium-based oxide film 5 and the hafnium-based oxide film 9 are in contact with each other on the element isolation region 2, a parasitic MIS transistor that has been a problem in the semiconductor device studied by the present inventors can be generated. Can be reduced. Further, for example, even when the hafnium-based oxide film 9 is placed on the hafnium-based oxide film 5, the possibility of generating a parasitic MIS transistor that has been a problem in the semiconductor device studied by the present inventors is reduced. be able to. As will be described later, this prevents the element isolation region 2 from being scraped in the etching process during the manufacturing process by the hafnium-based oxide film 5 and the hafnium-based oxide film 9 that are in contact with each other on the element isolation region 2. Because it can. Accordingly, malfunction due to the parasitic MIS transistor can be suppressed, and the reliability of the semiconductor device can be improved.

  Next, a method for manufacturing the nMIS transistor Qn and the pMIS transistor Qp constituting the semiconductor device in the present embodiment will be described with reference to the drawings.

  First, as shown in FIGS. 5 and 6, a substrate 1 having an n well 3 constituting an active region of a pMIS transistor isolated from each other by an element isolation region 2 and a p well 4 constituting an active region of the nMIS transistor. Prepare.

Specifically, first, surface treatment is performed on the main surface (element formation surface) of the substrate 1 made of, for example, p-type single crystal silicon. Next, an element isolation region 2 composed of STI (Shallow Trench Isolation) is formed by embedding a silicon oxide film in, for example, a CVD method in an element isolation trench having a depth of 120 nm to 150 nm, for example. In the element isolation region 2, the boundary between the pMIS region and the nMIS region is located. Next, an n-well 3 is formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into the substrate 1 in the pMIS region using a photolithography technique and an ion implantation method. Similarly, a p-well 4 is formed by introducing a p-type impurity such as boron (B) or boron fluoride (BF ₂ ) into the substrate 1 in the nMIS region by using a photolithography technique and an ion implantation method.

Subsequently, as shown in FIGS. 7 and 8, a hafnium-based oxide film 5 having a dielectric constant higher than that of silicon oxide (SiO ₂ ) is formed on the main surface of the substrate 1 as a gate insulating film material film of the pMIS transistor. Thereafter, a protective film 6 having a high etching selectivity with respect to the hafnium-based oxide film 5 and a hard mask 7 having a high etching selectivity with respect to the protective film 6 are sequentially stacked on the hafnium-based oxide film 5.

Specifically, first, hafnium aluminum oxide (HfAlO) having a thickness of about 2 to 3 nm is formed as the hafnium-based oxide film 5 by using atomic layer deposition (ALD) method, CVD method or sputtering method. A film is formed. The HfAlO film (hafnium-based oxide film 5) is a high dielectric constant (high-k) film because it has a dielectric constant higher than that of silicon oxide. The HfAlO film may be subjected to nitriding or heat treatment at the end of the manufacturing as needed. A silicon oxide (SiO ₂ ) film having a thickness of about 0.5 nm may be formed as an interface layer between the hafnium-based oxide film 5 and the substrate 1.

Next, a titanium nitride (TiN) film having a thickness of about 10 nm is formed as the protective film 6 by sputtering. The TiN film of the protective film 6 is a film necessary for the manufacturing process, but is not present in the final product. Therefore, it is desirable to use a material that can be easily deposited and removed with a high selectivity. In this embodiment, the TiN film is applied as the protective film 6 because hydrogen peroxide water (H ₂ O ₂ ) is known as a wet etching material that can be easily deposited by sputtering and titanium nitride can be easily removed. This is because the underlying HfAlO film (hafnium-based oxide film 5) is removed without damaging it.

  As the protective film 6, a polysilicon film can also be used. In this case, it can be selectively removed with potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH).

  Next, a silicon nitride (SiN) film having a thickness of about 10 nm is formed as the hard mask 7 using a CVD method at a low temperature of about 450 ° C. using HCD (Hexa-Chloro-Disilane) as a raw material. The HCD-SiN film of the hard mask 7 is a film necessary for the manufacturing process, but is not present in the final product. Therefore, it is desirable to use a material that can be easily deposited and removed with a high selectivity. In the present embodiment, the silicon nitride film is applied as the hard mask 7 because it is easily deposited by CVD, and dilute hydrofluoric acid (dHF) is known as a wet etching material that can easily remove the HCD-SiN film. This is because it is removed without damaging the underlying TiN film (protective film 6). In addition, since the silicon nitride film using DCS (Di-Chloro-Silane) as a raw material cannot be removed by dilute hydrofluoric acid, the etching selectivity is low with respect to the TiN film (protective film 6). Does not apply.

  As the hard mask 7, an amorphous silicon film or a polysilicon film can also be used. In this case, it can be selectively removed with potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH).

  Subsequently, as shown in FIGS. 9 and 10, a resist mask covering the entire active region of the pMIS transistor in the element isolation region 2 that insulates and isolates the active region constituting the pMIS transistor and the active region constituting the nMIS transistor. 8 is formed. Specifically, after forming a resist film on the main surface of the substrate 1 using photolithography technology, a resist mask 8 patterned to expose the p well 4 in the nMIS region including the active region of the nMIS transistor. Form.

  Subsequently, as shown in FIGS. 11 and 12, the hard mask 7 is etched using the resist mask 8 provided in the entire active region of the pMIS transistor in the element isolation region 2. Here, the HCD-SiN film constituting the hard mask 7 is etched using either dry etching or wet etching.

Subsequently, after removing the resist mask 8 by ashing, as shown in FIGS. 13 and 14, the hard mask 7 provided in the entire active region of the pMIS transistor in the element isolation region 2 is used to protect the protective film 6. Etch. Specifically, using the HCD-SiN film as a mask (hard mask 7), the TiN film constituting the protective film 6 exposed in the nMIS region is selectively etched by wet etching with hydrogen peroxide (H ₂ O ₂ ). Remove. At this time, it is important that the HCD-SiN film and the hafnium-based oxide film 5 constituting the hard mask 7 are hardly damaged.

  Subsequently, as shown in FIGS. 15 and 16, the hafnium-based oxide film 5 is etched using the hard mask 7 and the protective film 6 provided in the entire active region of the pMIS transistor in the element isolation region 2. Specifically, using the HCD-SiN film (hard mask 7) and the underlying TiN film (protective film 6) as a mask, the HfAlO film constituting the hafnium-based oxide film 5 exposed in the nMIS region is diluted with dilute hydrofluoric acid ( It is selectively removed by etching with dHF). As a result, the p well 4 constituting the active region of the nMIS transistor is exposed in the nMIS region.

Subsequently, as shown in FIGS. 17 and 18, the gate insulating film material film of the nMIS transistor on the main surface of the substrate 1 has a higher dielectric constant than silicon oxide (SiO ₂ ) and is different from the hafnium-based oxide film 5. After the hafnium-based oxide film 9 made of the material is formed, the protective film 10 having a high etching selectivity with respect to the hafnium-based oxide film 9 is sequentially formed on the hafnium-based oxide film 9, and the protective film 10 is etched. A hard mask 11 having a high selectivity is stacked.

Specifically, first, a hafnium magnesium oxide (HfMgO) having a thickness of about 2 to 3 nm is formed as the hafnium-based oxide film 9 by using an atomic layer controlled deposition (ALD) method, a CVD method, or a sputtering method. A film is formed. The HfMgO film (hafnium-based oxide film 9) is a high dielectric constant (high-k) film because it has a dielectric constant higher than that of silicon oxide. The HfMgO film may be subjected to nitriding or heat treatment at the end of manufacturing or at the end if necessary. A silicon oxide (SiO ₂ ) film having a thickness of about 0.5 nm may be formed as an interface layer between the hafnium-based oxide film 9 and the substrate 1.

Next, a titanium nitride (TiN) film having a thickness of about 10 nm is formed as the protective film 10 by sputtering. The TiN film of the protective film 10 is a film necessary for the manufacturing process, but is not present in the final product. Therefore, it is desirable to use a material that can be easily deposited and removed with a high selectivity. In the present embodiment, the TiN film is applied as the protective film 10 because hydrogen peroxide (H ₂ O ₂ ) is known as a wet etching material that can be easily formed by sputtering and can easily remove titanium nitride. This is because the underlying HfMgO film (hafnium-based oxide film 9) is removed without damaging it.

  As the protective film 10, a polysilicon film can also be used. In this case, it can be selectively removed with potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH).

  Next, a silicon nitride (SiN) film having a thickness of about 10 nm is formed as the hard mask 11 using a CVD method at a low temperature of about 450 ° C. using HCD as a raw material. The HCD-SiN film of the hard mask 11 is a film necessary for the manufacturing process, but is not present in the final product. Therefore, it is desirable to use a material that can be easily deposited and removed with a high selectivity. In this embodiment, the silicon nitride film is applied as the hard mask 11 because it is easily deposited by CVD, and dilute hydrofluoric acid (dHF) is known as a wet etching material that can easily remove the HCD-SiN film. This is because it is removed without damaging the underlying TiN film (protective film 10). In addition, since the silicon nitride film using DCS (Di-Chloro-Silane) as a raw material cannot be removed by dilute hydrofluoric acid, the etching selection ratio is low with respect to the TiN film (protective film 10). Does not apply.

  As the hard mask 11, an amorphous silicon film or a polysilicon film can also be used. In this case, it can be selectively removed with potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH).

  Subsequently, as shown in FIGS. 19, 20, and 4, the entire active region of the nMIS transistor is related to the element isolation region 2 so as to overlap with the resist mask 8 provided as an etching mask in the previous step. A covering resist mask 12 is formed. Specifically, a resist film is formed on the main surface of the substrate 1 using a photolithography technique, and then a resist mask 12 patterned so as to expose the hard mask 11 in the pMIS region is formed.

  In the present embodiment, as shown in FIG. 4, the active region of the pMIS transistor and the nMIS transistor so that the resist mask 8 used as an etching mask in the previous step and the region covered with the resist mask 12 overlap. The active region is overlapped by an element isolation region 2 that isolates and isolates the active region (region V in FIG. 4 where hatching overlaps). That is, the resist mask 8 (first resist pattern) and the resist mask 12 (second resist pattern) are formed so as to cover the common region on the substrate 1 in a plane. As described above, since the resist mask 8 and the resist mask 12 can overlap in the present embodiment, the width W (see FIG. 2) of the element isolation region 2 is set to the width W ′ of the element isolation region 2 in the case where no overlap occurs. (See FIGS. 51 and 52). Thereby, in the semiconductor device manufactured through the subsequent steps, the density of the SRAM cell can be increased and the size can be reduced.

  Subsequently, as shown in FIGS. 21 and 22, the element isolation region 2 is provided over the active region of the nMIS transistor so as to overlap the resist mask 8 provided as an etching mask in the previous step. The hard mask 11 is etched using the resist mask 12. Here, the HCD-SiN film constituting the hard mask 11 is etched using either dry etching or wet etching.

Subsequently, after removing the resist mask 12, as shown in FIGS. 23 and 24, the nMIS transistor is applied to the element isolation region 2 so as to overlap with the hard mask 7 provided as an etching mask in the previous step. The protective film 10 is etched using the hard mask 11 provided in the entire active region. Specifically, using the HCD-SiN film as a mask (hard mask 11), the TiN film constituting the protective film 10 exposed in the pMIS region is selectively etched by wet etching with hydrogen peroxide (H ₂ O ₂ ). Remove. At this time, it is important that the HCD-SiN film and the hafnium-based oxide film 9 constituting the hard mask 11 are hardly damaged.

In the present embodiment, the TiN film constituting the protective film 10 is wet etched so as to recede to the bottom of the hard mask 11. As described above, the resist mask 8 and the resist mask 12 are provided so as to overlap in the element isolation region 2. The protective film 10 in the overlapping region due to the overlap is removed by wet etching. That is, the TiN film (protective film 10) is covered with the hard mask 11 and is not exposed by wet etching of the TiN film constituting the protective film 10 with hydrogen peroxide (H ₂ O ₂ ). It can be selectively removed.

  Like the semiconductor device investigated by the present inventors, there is a possibility that a region where the gate height of the nMIS transistor or the pMIS transistor is locally high is formed by a residue at the time of etching. Therefore, each of the nMIS transistor and the pMIS transistor It has been considered that the resist mask for separating the gate insulating film is not allowed to overlap. However, in the present embodiment, the resist mask 8 and the resist mask 12 are overlapped. This is because by removing the TiN film constituting the protective film 10 by wet etching, the TiN film (protective film 10) can be selectively removed even if it is not covered with the hard mask 11 and exposed. . Finally, the TiN film (protective film 10) is removed at a high selectivity with respect to the hafnium-based oxide film 9, and a TiN film or a TaN film as a gate electrode material is formed again on the main surface of the substrate 1. Since the correction is made, there is no step in the gate.

  Subsequently, when the hard mask 7 and the hard mask 11 are all removed by etching, the result is as shown in FIGS. Specifically, the HCD-SiN film constituting the hard masks 7 and 11 is removed by wet etching with dilute hydrofluoric acid (dHF). At this time, in this embodiment, the hafnium-based oxide film 9 in the active region of the pMIS transistor is also removed. In other words, the HfMgO film, which is the gate insulating film material film of the nMIS transistor, uses the protective film 10 as a mask provided in the entire active region of the nMIS transistor so as to overlap the protective film 6. (Hafnium-based oxide film 9) is etched.

  In the present embodiment, in the element isolation region 2, an HfMgO film (hafnium-based oxide) that is a gate insulating film material film of an nMIS transistor that is in contact with an HfAlO film (hafnium-based oxide film 5) that is a gate insulating film material film of a pMIS transistor. Wet etching is performed to form film 9). Since the hafnium-based oxide film 5 and the hafnium-based oxide film 9 are in contact with each other on the element isolation region 2, the STI constituting the element isolation region 2 is not etched away. When the STI is not removed, the impurity stops at the STI in the subsequent impurity implantation process for forming the source / drain, and can be prevented from diffusing into the substrate 1 below. Thereby, it is possible to reduce the possibility that a parasitic MIS transistor which has been a problem in the semiconductor device studied by the present inventors is generated.

Note that it is considered that the HfAlO film (hafnium-based oxide film 5) and the HfMgO film (hafnium-based oxide film 9) are etched away at the boundary. However, the etching rate with dilute hydrofluoric acid (dHF) is higher in the HCD-SiN films constituting the hard masks 7 and 11 than in the HfAlO film and the HfMgO film, so the amount of scraping is very small. In this embodiment, in order to keep the etching rate of the HCD-SiN film with dilute hydrofluoric acid (dHF) high, the temperature (for example, 450 ° C.) is not exceeded after the formation of the HCD-SiN film. Therefore, a sputtering method that can be formed at a temperature lower than the formation temperature of the HCD-SiN film is used to form the TiN film constituting the protective films 6 and 10. For example, a TiN film can be formed using a CVD method using TiCl ₄ as a raw material, but the formation temperature is, for example, 640 ° C., which is higher than the formation temperature of the HCD-SiN film, and thus is not applied. .

Subsequently, when all of the protective film 6 and the protective film 10 are removed by etching, a state as shown in FIGS. 27 and 28 is obtained. Specifically, the TiN film constituting the protective films 6 and 10 is removed by wet etching with hydrogen peroxide water (H ₂ O ₂ ). As described above, since the hafnium-based oxide film 5 and the hafnium-based oxide film 9 are in contact with each other on the STI constituting the element isolation region 2, the STI is not exposed.

  Subsequently, as shown in FIGS. 29 and 30, a metal film 13 and a polysilicon film 14 are sequentially stacked on the main surface of the substrate 1. The metal film 13 and the polysilicon film 14 constitute a gate electrode material film of an nMIS transistor and a pMIS transistor.

  Specifically, a titanium nitride (TiN) film having a thickness of about 30 nm is formed as the metal film 13 by using, for example, a sputtering method. This metal film 13 is used as a work-function metal (WFM). Therefore, tantalum nitride (TaN) or tantalum silicon nitride (TaSiN) may be used as the metal film 13 of the mid gap material having high heat resistance. In the present embodiment, a TiN film is used as the metal film 13 in consideration of ease of gate processing.

  Further, as the polysilicon film 14, a non-conductive polysilicon film having a thickness of about 50 nm is formed by using, for example, a CVD method. The polysilicon film 14 is made conductive by being implanted with impurities in a later step, and is provided as a low resistance film on the metal film 13. Note that a metal film such as a tungsten (W) film may be formed by using, for example, a sputtering method as the low resistance film as the gate electrode material.

  Subsequently, as shown in FIGS. 31 and 32, after forming a resist mask 15 covering the entire active region (n-well 3) of the pMIS transistor, impurities are implanted into the polysilicon film 14 not covered with the resist mask 15 Thus, the polysilicon film 14 is made conductive. Thereafter, the resist mask 15 is removed by ashing.

  Specifically, after a resist film is formed on the main surface of the substrate 1 by a photolithography technique to which the photomask used for forming the resist mask 8 in the previous step is applied, the active region (p A resist mask 15 patterned so as to expose the well 4) is formed. In order to form the gate electrode of the nMIS transistor, a conductive polysilicon film 14 is formed by ion-implanting phosphorus (P) or arsenic (As) n-type impurities into the polysilicon film 14 in the nMIS region. To do.

  Subsequently, as shown in FIGS. 33 and 34, after forming a resist mask 16 covering the entire active region (p well 4) of the nMIS transistor, impurities are implanted into the polysilicon film 14 not covered with the resist mask 16 Thus, the polysilicon film 14 is made conductive. Thereafter, the resist mask 16 is removed by ashing.

  Specifically, after a resist film is formed on the main surface of the substrate 1 by a photolithography technique to which the photomask used for forming the resist mask 12 in the previous step is applied, an active region (n A resist mask 16 patterned to expose the pMIS region including the well 3) is formed. In order to form the gate electrode of the pMIS transistor, a p-type impurity of boron (B) is ion-implanted into the polysilicon film 14 in the pMIS region, thereby forming the conductive polysilicon film 14.

  The resist mask 15 and the resist mask 16 used for making the polysilicon film 14 conductive are masks covering the same regions as the resist mask 8 and the resist mask 12 described above. In other words, the resist mask 8 and the resist mask 12 in this embodiment are intentionally overlapped in the same manner as a mask for pre-doping a polysilicon film in a conventionally used polysilicon gate. However, as described above, the role of overlapping the resist masks 8 and 12 in the present embodiment is to separate the hafnium-based oxide films 5 and 9, to make the cells finer, and to further parasitize. This is to suppress the generation of the MIS transistor, which is different from the role of the pre-doping mask.

  Subsequently, as shown in FIGS. 35 and 36, the n well 3 constituting the active region of the pMIS transistor and the p well 4 constituting the active region of the nMIS transistor are traversed, and the n well 3, the element isolation region 2, and p A resist mask 17 provided in the well 4 is formed. Specifically, a resist film is formed on the main surface of the substrate 1 using a photolithography technique, and then a patterned resist mask 17 is formed for forming gates of the pMIS transistor and the nMIS transistor.

  Subsequently, as shown in FIGS. 37 and 38, the resist mask 17 is used to etch the polysilicon film 14 which is the gate electrode material of the pMIS transistor and the nMIS transistor and the TiN film constituting the metal film 13 therebelow. . Thereby, a gate electrode G having a laminated structure of the polysilicon film 14 and the metal film 13 is formed. Thereafter, the resist mask 17 is removed by ashing.

  In this embodiment, both the nMIS transistor and the pMIS transistor are made of the same (common) gate electrode material, and the same gate electrode material is etched. Therefore, control is easier than etching different gate electrode materials simultaneously. It is. For example, if the metal elements constituting the metal film 13 on the hafnium-based oxide films 5 and 9 are different, the etching shape is different, or the selectivity with the hafnium-based oxide films 5 and 9 is lowered. When the etching shape is different, the gate length or channel length is different between the pMIS transistor and the nMIS transistor. Further, when the selection ratio is low, there is a problem that the substrate 1 is broken. On the other hand, when the same gate electrode material is used, such a problem is solved. In particular, this merit becomes greater as the gate length becomes shorter with miniaturization.

  Subsequently, as shown in FIGS. 39 and 40, the hafnium-based oxide films 5 and 9 are removed by etching with dilute hydrofluoric acid (dHF) using the polysilicon film 14 as the gate electrode material film as a mask. As a result, the active regions (n well 3 and p well 4) that become the source / drain regions of the pMIS transistor and the nMIS transistor are exposed.

  Subsequently, as shown in FIGS. 41 and 42, a p-type semiconductor region 18 to be a source / drain region is formed in the n-well 3 constituting the active region of the pMIS transistor. In addition, an n-type semiconductor region 19 serving as a source / drain region is formed in the p-well 4 constituting the active region of the nMIS transistor.

  Specifically, after forming a resist film on the main surface of the substrate 1 by photolithography using the photomask used to form the resist mask 8, the active region (p well 4) of the nMIS transistor is formed. After forming a resist mask (not shown) patterned so as to expose the included nMIS region, n-type impurity ions such as phosphorus (P) or arsenic (As) are implanted into the p-well 4. Further, after forming a resist film on the main surface of the substrate 1 by a photolithography technique using a photomask used to form the resist mask 12, a pMIS region including an active region (n well 3) of the pMIS transistor. After a resist mask (not shown) patterned so as to expose is formed, p-type impurity ions such as boron (B) are implanted into the n-well 3. Thereafter, the impurity ions are activated by annealing, and a p-type semiconductor region 18 is formed in the n-well 3 and an n-type semiconductor region 19 is formed in the p-well 4.

  Here, in the present embodiment, as described above, since the STI constituting the element isolation region 2 is not cut, the implanted impurity is only STI, and the impurity is not diffused into the substrate 1 therebelow. For this reason, possibility that a parasitic MIS transistor will be generated can be reduced.

  Subsequently, as shown in FIGS. 2 and 3, a sidewall 20 is formed along the side surface of the gate electrode G, and a silicide film 21 is formed on the surfaces of the polysilicon film 14, the p-type semiconductor region 18, and the n-type semiconductor region 19. Form. Next, after forming an interlayer insulating film 22 on the main surface of the substrate 1, a contact hole 23 is formed at a predetermined position, and a contact 24 is formed by embedding a conductive material therein. Thereafter, a wiring 25 electrically connected to the contact 24 is formed. Further, although not shown, for example, a multilayer wiring is formed on the wiring 25 and a passivation film is formed on the outermost surface, whereby the semiconductor device is completed.

  Specifically, the sidewall 20 is formed by forming a silicon nitride film on the substrate 1 including the nMIS region and the pMIS region by, for example, a CVD method, and anisotropically etching the silicon nitride film. Formed on the side wall of the gate electrode G.

  The silicide film 21 is formed by, for example, forming a nickel film on the main surface of the substrate 1 and reacting (silicidation) with the silicon of the polysilicon film 14 constituting the substrate 1 and the gate electrode G by heat treatment. Unreacted nickel film is removed. As a result, a silicide film 21 is formed on the gate electrode G of the pMIS transistor Qp and the p-type semiconductor region 18 in the pMIS region, and a silicide film on the gate electrode G of the nMIS transistor Qn and the n-type semiconductor region 19 in the nMIS region. 21 is formed. The silicide film 21 can reduce contact resistance with a contact formed in a later process.

  The interlayer insulating film 22 is formed by depositing a silicon oxide film on the main surface of the substrate 1 by using, for example, a CVD method. The contact hole 23 is formed so as to penetrate the interlayer insulating film 22 and reach the gate electrode G, the p-type semiconductor region 18, and the n-type semiconductor region 19 using a photolithography technique and an etching technique.

  Further, the contact 24 is formed on the substrate 1 so that the contact hole 23 is buried after a titanium / titanium nitride film is formed on the interlayer insulating film 22 including the bottom and inner walls of the contact hole 23 by using, for example, a sputtering method. In addition, a tungsten film is formed using, for example, a CVD method. Next, the unnecessary titanium / titanium nitride film and tungsten film formed on the interlayer insulating film 22 are removed by, for example, a CMP method, thereby forming the contact 24. The titanium / titanium nitride film of the contact 24 has a so-called barrier property that prevents tungsten in the tungsten film from diffusing into silicon.

  For the wiring 25, a titanium / titanium nitride film, an aluminum film containing copper, and a titanium / titanium nitride film are sequentially formed on the interlayer insulating film 22 and the contact 24. These films can be formed by using, for example, a sputtering method. Next, these films are patterned using a photolithography technique and an etching technique to form the wiring 25.

  In this way, an integrated circuit including an SRAM can be formed on the substrate 1. In this embodiment, the manufacturing process of the semiconductor device constituting the SRAM has been described. However, other MIS transistors constituting the SRAM are basically formed by the same process. As described above, the semiconductor device in this embodiment can be manufactured. Note that the order of the steps for manufacturing the pMIS transistor Qp and the nMIS transistor Qn may be reversed.

(Embodiment 2)
In the first embodiment, the case where the HfAlO film included in the gate insulating film of the pMIS transistor and the HfMgO film included in the gate insulating film of the nMIS transistor are each formed from a single layer has been described. In this embodiment, the hafnium oxide (HfO ₂₎ film as the base insulating film, laminating an _Al 2 _{O 3} film and the MgO film as a cap film, diffusing an _Al 2 _{O 3} film and MgO film HfO ₂ film A case of forming a gate insulating film (HfAlO film, HfMgO film) will be described. In addition, the description similar to the said Embodiment 1 may be abbreviate | omitted.

  First, as shown in FIG. 43, a substrate 1 having an n well 3 and a p well 4 constituting an active region of a pMIS transistor and an active region of an nMIS transistor, respectively, isolated from each other by an STI constituting an element isolation region 2 is formed. prepare.

  Next, a base insulating film 31, a cap film 32 for forming a gate insulating film of a pMIS transistor, a protective film 6 and a hard mask 7 are sequentially stacked on the main surface of the substrate 1, and then a patterned resist mask 8 is formed. .

The base insulating film 31 is composed of a hafnium oxide (HfO ₂ ) film having a thickness of about 2 to ₃ nm formed by using an ALD method, a CVD method, or a sputtering method. Since this HfO ₂ film has a higher dielectric constant than silicon oxide, it is a high dielectric constant film. The HfO ₂ film may be subjected to nitriding or heat treatment at the end of manufacturing or at the end if necessary. Note that a silicon oxide (SiO ₂ ) film having a thickness of about 0.5 nm may be formed as an interface layer between the base insulating film 31 and the substrate 1.

The cap film 32 is composed of an aluminum oxide (Al ₂ O ₃ ) film having a thickness of about 1 nm formed by using an ALD method, a CVD method, or a sputtering method. This Al ₂ O ₃ film is a high dielectric constant film because it has a higher dielectric constant than silicon oxide. Note that the Al ₂ O ₃ film may be subjected to nitriding or heat treatment at the end of the manufacturing as needed.

As the protective film 6, a TiN film is applied on the assumption that the etching selectivity is higher than that of the underlying high dielectric constant film. The protective film 6 is a film necessary for the manufacturing process, but is not present in the final product. Therefore, it is desirable to use a material that can be easily deposited and removed with a high selectivity. In this embodiment, the TiN film is applied as the protective film 6 because hydrogen peroxide water (H ₂ O ₂ ) is known as a wet etching material that can be easily deposited by sputtering and titanium nitride can be easily removed. This is because it is removed without damaging the high dielectric constant film as the base. In the present embodiment, a TiN film having a thickness of about 10 nm is formed as the protective film 6 by sputtering.

  As the hard mask 7, an HCD-SiN film is applied on the assumption that the etching selectivity is high with respect to the TiN film of the protective film 6. In the present embodiment, an HCD-SiN film having a thickness of about 10 nm is formed as the hard mask 7 using a CVD method.

  The resist mask 8 relates to the element isolation region 2 that insulates and isolates the active region of the pMIS transistor and the active region of the nMIS transistor, and is used as a mask that covers the entire active region of the pMIS transistor. The resist mask 8 is formed by forming a resist film on the main surface of the substrate 1 using a photolithography technique and then patterning so as to expose the hard mask 7 in the active region of the nMIS transistor.

  Next, after the hard mask 7 is etched using the resist mask 8, the resist mask 8 is removed by ashing. Next, when the protective film 6 and the cap film 32 are etched using this hard mask 7, as shown in FIG. 44, the patterned cap film 32, protective film 6 and hard mask 7 are formed on the base insulating film 31 in the pMIS region. Is provided.

  Subsequently, as shown in FIG. 44, the cap film 33 for forming the gate insulating film of the nMIS transistor, the protective film 10 and the hard mask 11 are sequentially formed on the main surface of the substrate 1, and then the patterned resist mask 12 is formed. Form.

  The cap film 33 is composed of a magnesium oxide (MgO) film having a thickness of about 1 nm formed by using an ALD method, a CVD method, or a sputtering method. This MgO film is a high dielectric constant film because it has a higher dielectric constant than silicon oxide. Note that the MgO film may be subjected to nitridation or heat treatment at the end during the production as needed. Further, since the cap film 33 and the cap film 32 are optimized for the nMIS transistor and the pMIS transistor, their thicknesses may be different.

As the protective film 10, a TiN film is applied on the assumption that the etching selectivity is higher than that of the underlying high dielectric constant film. Further, the protective film 10 is a film necessary for the manufacturing process, but is not present in the final product. Therefore, it is desirable to use a material that can be easily deposited and removed with a high selectivity. In the present embodiment, the TiN film is applied as the protective film 10 because hydrogen peroxide (H ₂ O ₂ ) is known as a wet etching material that can be easily formed by sputtering and can easily remove titanium nitride. This is because it is removed without damaging the high dielectric constant film as the base. In the present embodiment, a TiN film having a thickness of about 10 nm is formed as the protective film 10 by sputtering.

  As the hard mask 11, an HCD-SiN film is applied on the assumption that the etching selectivity is high with respect to the TiN film of the protective film 10. In the present embodiment, an HCD-SiN film having a thickness of about 10 nm is formed as the hard mask 10 using a CVD method.

  The resist mask 12 relates to the element isolation region 2 that insulates and isolates the active region of the pMIS transistor and the active region of the nMIS transistor, and is used as a mask that covers the entire active region of the nMIS transistor. This resist mask 12 is patterned so as to expose the hard mask 11 in the active region of the pMIS transistor after a resist film is formed on the main surface of the substrate 1 using a photolithography technique.

  Similarly to the first embodiment, the present embodiment also has the resist mask 8 used as an etching mask in the previous step and the region covered by the resist mask 12 overlapped as shown in FIG. The active region of the pMIS transistor and the active region of the nMIS transistor are overlapped with each other in an element isolation region 2 that isolates and isolates them (region V in which hatching overlaps in FIG. 4). In this embodiment, since the resist mask 8 and the resist mask 12 can overlap, the width W (see FIG. 2) of the element isolation region 2 is set to the width W ′ of the element isolation region 2 in the case where no overlap occurs (FIG. 51). , See FIG. 52). Thereby, in the semiconductor device manufactured through the subsequent steps, the density of the SRAM cell can be increased and the size can be reduced.

  Subsequently, as shown in FIG. 45, the hard mask 11 is etched using the resist mask 12. Here, the HCD-SiN film constituting the hard mask 11 is etched using either dry etching or wet etching.

Subsequently, after removing the resist mask 12 by ashing, as shown in FIG. 46, the element masking region 2 is overlapped with the element isolation region 2 so as to overlap with the hard mask 7 provided as an etching mask in the previous step. The protective film 10 is etched using the hard mask 11 provided in the entire active region. Specifically, using the HCD-SiN film as a mask (hard mask 11), the TiN film constituting the protective film 10 exposed in the pMIS region is selectively etched by wet etching with hydrogen peroxide (H ₂ O ₂ ). Remove.

In the present embodiment, the TiN film constituting the protective film 10 is wet-etched so as to recede to the bottom of the hard mask 11. As described above, the resist mask 8 and the resist mask 12 are provided so as to overlap in the element isolation region 2. The protective film 10 in the overlapping region due to the overlap is removed by wet etching. That is, the TiN film (protective film 10) is covered with the hard mask 11 and is not exposed by wet etching of the TiN film constituting the protective film 10 with hydrogen peroxide (H ₂ O ₂ ). It can be selectively removed.

  Subsequently, when the hard mask 7 and the hard mask 11 are all removed by etching, the protective films 6 and 10 are exposed as shown in FIG. Specifically, the HCD-SiN film constituting the hard masks 7 and 11 is removed by wet etching with dilute hydrofluoric acid (dHF). At this time, in this embodiment, the cap film 33 in the active region of the pMIS transistor is also removed. In other words, the MgO film that forms the gate insulating film of the nMIS transistor using the protective film 10 as a mask provided in the entire active region of the nMIS transistor in the element isolation region 2 so as to overlap the protective film 6. The cap film 33) is etched.

In the present embodiment, in the element isolation region 2, the MgO film (cap film 33) that constitutes the gate insulating film of the nMIS transistor that contacts the Al ₂ O ₃ film (cap film 32) that constitutes the gate insulating film of the pMIS transistor. Wet etching is performed so as to form. Since the cap film 32 and the cap film 33 are in contact with each other on the element isolation region 2, the STI constituting the element isolation region 2 is not scraped by etching. When the STI is not removed, the impurity stops at the STI in the subsequent impurity implantation process for forming the source / drain, and can be prevented from diffusing into the substrate 1 below. Thereby, it is possible to reduce the possibility that a parasitic MIS transistor which has been a problem in the semiconductor device studied by the present inventors is generated.

Next, an annealing process is performed to diffuse the constituent elements of the Al ₂ O ₃ film of the cap film 32 into the HfO ₂ film of the base insulating film 31 in the pMIS region, thereby forming an HfAlO film as the hafnium-based oxide film 34. In the nMIS region, the constituent elements of the MgO film of the cap film 33 are diffused into the HfO ₂ film of the base insulating film 32 to form an HfMgO film as the hafnium-based oxide film 35 (see FIG. 48). Next, when the protective films 6 and 10 are all removed by etching and the metal film 13 and the polysilicon film 14 are sequentially formed on the main surface of the substrate 1, a state as shown in FIG. 48 is obtained.

  Thereafter, as described in the first embodiment, a reduced semiconductor device is completed through a patterning process for forming a gate electrode.

(Embodiment 3)
In the first embodiment, the case where a silicon substrate is used as the substrate has been described, but in this embodiment, the case where an SOI (Silicon On Insulator) substrate is used will be described. The description similar to that of the first embodiment may be omitted.

  49 and 50 are cross-sectional views schematically showing main parts of the semiconductor device according to the present embodiment, and are plan views schematically showing main parts of the semiconductor device including the SRAM shown in FIG. Corresponds to the AA ′ line and BB ′ line. As shown in FIGS. 49 and 50, the SOI substrate 51 has a buried insulating film 52 on a base silicon substrate and a silicon layer 53 on the buried insulating film 52.

  In the first embodiment, the element isolation region 2 is formed by forming STI on the main surface of the silicon substrate constituting the substrate 1. This element isolation region 2 is provided to insulate and isolate the active region of the nMIS transistor and the active region of the pMIS transistor. In the present embodiment, the element isolation region 2 is a region where the silicon layer of the SOI substrate is removed. Therefore, the semiconductor device can be completed by making the process after forming the element isolation region 2 on the SOI substrate 51 the same process as in the first embodiment. For example, the n well 3 is formed in the silicon layer 53 of the pMIS region, and the p-type semiconductor region 18 forming the source / drain region of the pMIS transistor is formed in the n well 3. Further, the p well 4 is formed in the silicon layer 53 of the nMIS region, and the n-type semiconductor region 19 forming the source / drain region of the nMIS transistor is formed in the p well 4.

  Similarly to the first embodiment, the present embodiment also has the resist mask 8 used as an etching mask in the previous step and the region covered by the resist mask 12 overlapped as shown in FIG. The active region of the pMIS transistor and the active region of the nMIS transistor are overlapped with each other in an element isolation region 2 that isolates and isolates them (region V in which hatching overlaps in FIG. 4). In this embodiment, since the resist mask 8 and the resist mask 12 can overlap with each other, the width W (see FIG. 49) of the element isolation region 2 is set to the width W ′ of the element isolation region 2 when not overlapping (FIG. 51). , See FIG. 52). Thereby, in the semiconductor device manufactured through the subsequent steps, the density of the SRAM cell can be increased and the size can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the gate electrode material of the pMIS transistor and the nMIS transistor is applied to the same semiconductor device has been described. However, the semiconductor device having a different gate electrode material (dual metal) is used. Can also be applied.

  The present invention is effective for a semiconductor device, in particular, a MIS transistor in which a high dielectric constant film is applied to a gate insulating film, and is particularly widely used in the manufacturing industry of a semiconductor device having a built-in SRAM.

It is a top view which shows typically the principal part of the semiconductor device in one embodiment of this invention. FIG. 2 is a cross-sectional view schematically showing a semiconductor device taken along line A-A ′ of FIG. 1. FIG. 2 is a cross-sectional view schematically showing the semiconductor device taken along line B-B ′ of FIG. 1. In relation to the element isolation region, the first mask provided in the entire active region of the pMIS transistor and the second mask provided in the entire active region of the nMIS transistor over the element isolation region provided with the first mask are over. It is a figure for demonstrating being wrapped. It is a top view which shows typically the principal part of the semiconductor device in the manufacturing process in one embodiment of this invention. FIG. 6 is a cross-sectional view schematically showing a semiconductor device taken along line A-A ′ of FIG. 5. FIG. 6 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 5. FIG. 8 is a cross-sectional view schematically showing a semiconductor device taken along line A-A ′ of FIG. 7. FIG. 8 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 7. FIG. 10 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 9. FIG. 10 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 9. FIG. 12 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 11. FIG. 12 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 11. It is sectional drawing which shows typically the semiconductor device in the A-A 'line | wire of FIG. FIG. 14 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 13. FIG. 16 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 15. FIG. 16 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 15. FIG. 18 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 17. FIG. 18 is a plan view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 17. FIG. 20 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 19. FIG. 20 is a plan view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 19. FIG. 22 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 21. FIG. 22 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 21. FIG. 24 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 23. FIG. 24 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 23. FIG. 26 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 25. FIG. 26 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 25. FIG. 28 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 27. FIG. 28 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 27. FIG. 30 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 29. FIG. 30 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 29. FIG. 32 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 31. FIG. 32 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 31. FIG. 34 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 33. FIG. 34 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 33. FIG. 36 is a cross-sectional view schematically showing the semiconductor device taken along line A-A ′ of FIG. 35. FIG. 36 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 35. FIG. 38 is a cross-sectional view schematically showing the semiconductor device taken along line B-B ′ of FIG. 37. FIG. 38 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 37. FIG. 40 is a cross-sectional view schematically showing the semiconductor device taken along line B-B ′ of FIG. 39. FIG. 40 is a plan view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 39. FIG. 42 is a cross-sectional view schematically showing the semiconductor device taken along line B-B ′ of FIG. 41. It is sectional drawing which shows typically the principal part of the semiconductor device in the manufacturing process in other embodiment of this invention. FIG. 44 is a cross-sectional view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 43. FIG. 45 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 44. FIG. 46 is a cross-sectional view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 45. FIG. 47 is a cross-sectional view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 46. FIG. 48 is a cross-sectional view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 47. It is sectional drawing which shows typically the principal part of the semiconductor device in other embodiment of this invention. FIG. 50 is a cross sectional view schematically showing a main part of a semiconductor device in a cross section different from the cross section shown in FIG. 49. It is sectional drawing which shows typically the principal part of the semiconductor device in the manufacturing process which the present inventors examined. FIG. 52 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 51. FIG. 53 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 52. FIG. 54 is a cross-sectional view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 53. It is a perspective view which shows typically the principal part of the semiconductor device with which scraping generate | occur | produced in the element isolation region. FIG. 56 is a plan view schematically showing main parts of the semiconductor device of FIG. 55.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Element isolation region 3 N well 4 P well 5 Hafnium-based oxide film 6 Protective film 7 Hard mask 8 Resist mask 9 Hafnium-based oxide film 10 Protective film 11 Hard mask 12 Resist mask 13 Metal film 14 Polysilicon films 15 and 16 , 17 Resist mask 18 p-type semiconductor region (source / drain)
19 n-type semiconductor region (source / drain)
20 Sidewall 21 Silicide film 22 Interlayer insulating film 23 Contact hole 24 Contact 25 Wiring 31 Base insulating film 32, 33 Cap film 34, 35 Hafnium-based oxide film 51 SOI substrate 52 Embedded insulating film 53 Silicon layer 101 Scraped 102 Semiconductor region G Gate Electrode Qp pMIS transistor Qn nMIS transistor

Claims (11)

A semiconductor substrate;
An element isolation region provided on a main surface of the semiconductor substrate;
A first active region and a second active region provided on a main surface of the semiconductor substrate and insulated from each other by the element isolation region;
A first gate insulating film of a first MIS transistor provided on the first active region so as to relate to the element isolation region;
A second gate insulating film made of a material different from that of the first gate insulating film, in contact with the first gate insulating film on the element isolation region, and provided on the second active region;
A first gate electrode of the first MIS transistor provided on the first gate insulating film;
A semiconductor device comprising: a second gate electrode of the second MIS transistor provided on the second gate insulating film.   2. The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are made of the same gate electrode material.   2. The semiconductor device according to claim 1, wherein the semiconductor substrate is an SOI substrate, and the element isolation region is a region where the silicon layer of the SOI substrate is removed. The first gate insulating film is a hafnium-based oxide film having a higher dielectric constant than silicon oxide and containing any of aluminum, titanium, or tantalum,
2. The semiconductor device according to claim 1, wherein the second gate insulating film is a hafnium-based oxide film having a dielectric constant higher than that of silicon oxide and containing any of magnesium, lanthanum, gadolinium, and yttrium. A semiconductor device manufacturing method including the following steps:
(A) preparing a semiconductor substrate having a first active region of a first MIS transistor and a second active region of a second MIS transistor that are insulated and isolated from each other by an element isolation region;
(B) forming a first gate insulating film material film on the main surface of the semiconductor substrate;
(C) etching the first gate insulating film material film using a first mask provided on the entire first active region so as to relate to the element isolation region;
(D) After the step (c), forming a second gate insulating film material film made of a material different from the first gate insulating film material film on the main surface of the semiconductor substrate;
(E) The second gate insulating film material film is etched using a second mask provided over the entire second active region so as to overlap with the element isolation region provided with the first mask. Process;
(F) a step of forming a gate electrode material film on the main surface of the semiconductor substrate after the step (e);
(G) Crossing the first active region and the second active region, and using the third mask provided in the first active region, the element isolation region, and the second active region, the gate electrode material film is formed Patterning.   6. The method of manufacturing a semiconductor device according to claim 5, wherein, in the step (e), the second gate insulating film material film in contact with the first gate insulating film material film is formed in the element isolation region. . A semiconductor device manufacturing method including the following steps:
(A) preparing a semiconductor substrate having a first active region of a first MIS transistor and a second active region of a second MIS transistor that are insulated and isolated from each other by an element isolation region;
(B) forming a first hafnium-based oxide film having a dielectric constant higher than that of silicon oxide on the main surface of the semiconductor substrate;
(C) A first protective film having a high etching selectivity with respect to the first hafnium-based oxide film in order on the first hafnium-based oxide film, and a first etching film having a high etching selectivity with respect to the first protective film. A step of laminating a hard mask;
(D) After the step (c), a step of etching the first hard mask using a first resist mask provided in the entire first active region so as to be related to the element isolation region;
(E) a step of etching the first protective film using the first hard mask after the step (d);
(F) After the step (e), using the first hard mask, etching the first hafnium-based oxide film;
(G) After the step (f), a second hafnium-based oxide film having a dielectric constant higher than that of silicon oxide and made of a material different from that of the first hafnium-based oxide film is formed on the main surface of the semiconductor substrate. The step of:
(H) A second protective film having a higher etching selectivity with respect to the second hafnium-based oxide film in order on the second hafnium-based oxide film, and a second with a higher etching selectivity with respect to the second protective film. A step of laminating a hard mask;
(I) After the step (h), using the second resist mask provided over the entire second active region so as to overlap with the element isolation region provided with the first resist mask, Etching the second hard mask;
(J) a step of etching the second protective film using the second hard mask after the step (i);
(K) After the step (j), removing all of the first hard mask and the second hard mask by etching;
(L) After the step (k), a step of removing all of the first protective film and the second protective film by etching;
(M) a step of forming a gate electrode material film on the main surface of the semiconductor substrate after the step (l);
(N) The gate electrode material using a third resist mask provided in the first active region, the element isolation region, and the second active region across the first active region and the second active region Patterning the film;   8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step (j), the second protective film is etched so as to recede to a position below the second hard mask.   8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step (j), the second protective film is wet-etched.   8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step (k), the second hafnium oxide film in contact with the first hafnium oxide film is formed in the element isolation region.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the first resist mask and the second resist mask are formed so as to cover a common region on the semiconductor substrate in a planar manner.

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