JP2013051250A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce Schottky resistance caused by contact with a polycrystalline silicon film.SOLUTION: A semiconductor device comprises a transistor. The transistor has: a first gate insulating film covering a part of a surface in a first active region and made of a first insulation material having a dielectric constant higher than that of silicon dioxide; a first metal gate electrode formed on the first gate insulating film and made of a first metal material; and a first polycrystalline silicon film of a p-type conductivity type formed on the first metal gate electrode.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Conventionally, a silicon dioxide film having a dielectric constant of about 3.9 has been used as a gate insulating film used in a transistor. However, when the gate insulating film is thinned with the miniaturization of the transistor, the leakage current increases, resulting in a device with high power consumption and standby power. Therefore, by using an insulating film (high dielectric constant insulating film) having a dielectric constant higher than that of the silicon oxide film as a gate insulating film (hereinafter sometimes referred to as “high dielectric constant gate insulating film”), Development of a transistor having an effective film thickness (EOT) thin is progressing even though the film thickness is larger than that of a silicon oxide film.

  However, a combination of a conventional polycrystalline silicon gate electrode and a high dielectric constant gate insulating film causes a phenomenon called depletion of the gate electrode. This is a phenomenon in which a depletion layer capacitance is formed between the high dielectric constant gate insulating film and the polycrystalline silicon gate electrode, and the advantage of the high dielectric constant gate insulating film that the EOT is thin is lost. Therefore, in order to prevent depletion of the gate electrode, the portion of the gate electrode in contact with the high dielectric constant gate insulating film is replaced with a metal layer instead of the polycrystalline silicon layer.

  On the other hand, when the gate electrode is composed only of the metal layer, (1) since the threshold voltage control by the gate electrode has a film thickness dependency, it is possible to realize a thickness satisfying the desired threshold value and the resistance value only by the metal layer. There are problems that (2) it is difficult to make all the gate electrodes into metal layers in terms of workability. For this reason, a transistor having a gate electrode in which a polycrystalline silicon layer is stacked on a metal layer has been proposed.

  Patent Document 1 (Japanese Patent Laid-Open No. 2011-14689) discloses an HKMG transistor in which TiN as a metal gate electrode and polycrystalline silicon are stacked on a high dielectric constant gate insulating film. In this transistor formation process, the polysilicon layers 112 and 118 are arranged on the uppermost layer of the gate electrode, and the extension layers 108 and 114 and the diffusion layers 107 and 113 (which serve as a source and a drain) are formed using this as a mask. Ion implantation for forming is performed. Therefore, the polycrystalline silicon electrode of each transistor is doped with an impurity having the same conductivity type as the channel conductivity type. In other words, the polycrystalline silicon electrode 118 of the n-channel transistor is doped n-type, and the polycrystalline silicon electrode 112 of the p-channel transistor is doped p-type.

  As described above, in the process of forming a transistor having polycrystalline silicon as a gate electrode, impurities may be introduced into the polycrystalline silicon gate electrode by implantation of impurities for forming an extension layer and a source and drain. The polycrystalline silicon gate electrode thus formed has a structure containing an impurity having the same polarity as the channel conductivity type of the transistor.

  Patent Document 2 (Japanese Patent Laid-Open No. 2009-267180) discloses an HKMG transistor in which a metal gate electrode (TiAlN, TiN, etc.) and polycrystalline silicon are stacked on a high dielectric constant gate insulating film. In this transistor manufacturing method, the gate insulating film 5, the first metal film 30, or the laminated film of the first metal film 30 and the second metal film 31 is made of n-type conductivity type polycrystalline silicon deposited with phosphorus as an impurity. A conductive film 32 is deposited. Then, the gate electrodes 6 and 7 are formed by processing these laminated films. Therefore, in both the p-type transistor Qp and the n-type transistor Qn, the polycrystalline silicon of the conductor film 32 constituting the gate electrodes 6 and 7 is of the n-type conductivity type.

  As described above, in the process of forming a transistor having polycrystalline silicon as a gate electrode, impurities may be doped in advance when the polycrystalline silicon film is deposited. In particular, comparing the resistivity of the polycrystalline silicon itself, it has been found that the n-type conductivity type polysilicon has a lower resistance than the p-type conductivity type. Therefore, normally, the impurity species previously doped in the polycrystalline silicon is a donor impurity as in Patent Document 2. The polycrystalline silicon gate electrode thus formed has an n-type conductivity type regardless of the channel conductivity type of the transistor, and has a structure including donor impurities.

JP 2011-14689 A JP 2009-267180 A

  However, when the inventors examined a HKMG type gate stack in which a metal gate electrode and a polycrystalline silicon film are typified by the technique of Patent Document 1 above, the gate interface resistance of an n-channel transistor is It was found to be higher than the gate interface resistance of the p-channel transistor.

One embodiment is:
A p-type conductivity type first active region formed on the main surface of the semiconductor substrate;
A first gate insulating film covering a part of the surface of the first active region and including a first insulating material having a dielectric constant higher than that of silicon dioxide;
A first metal gate electrode formed on the first active region via the first gate insulating film and made of a first metal material;
A first polycrystalline silicon gate electrode formed on the first metal gate electrode and made of a p-type conductivity type first polycrystalline silicon film;
The present invention relates to a semiconductor device.

Other embodiments are:
A semiconductor device having an n-channel transistor and a p-channel transistor,
The n-channel transistor and the p-channel transistor are respectively
A gate insulating film provided on a semiconductor substrate and including an insulating film having a dielectric constant higher than that of silicon dioxide;
A gate electrode provided on the gate insulating film and having a metal gate electrode made of a metal material in order from the gate insulating film side; and a p-type conductivity type polycrystalline silicon film;
The present invention relates to a semiconductor device.

Other embodiments are:
Forming a p-type conductivity type first active region on a main surface of a semiconductor substrate;
Forming an insulating film having a dielectric constant higher than that of silicon dioxide, a first metal film, and a laminated film having a p-type conductivity type polycrystalline silicon film in order so as to cover the main surface of the semiconductor substrate; ,
The laminated film is processed so as to cover a part of the surface of the first active region, and a first gate insulating film made of the insulating film, a first metal gate electrode made of the first metal film, And forming a first stacked body having a first polycrystalline silicon gate electrode made of the p-type conductivity type polycrystalline silicon film,
The present invention relates to a method for manufacturing a semiconductor device.

  In the claims and the specification, an insulating film having a dielectric constant higher than that of silicon dioxide is referred to as a “high dielectric constant insulating film” or a “High-K film”.

  An n-channel transistor including a gate electrode made of a laminated film of a metal gate electrode and a p-type conductivity type polycrystalline silicon film is used. Since the metal constituting the metal gate electrode has a large work function and the Fermi level is close to the valence band edge of silicon, Schottky resistance caused by contact with the p-type conductivity type polycrystalline silicon film should be reduced. Can do.

It is a figure explaining the effect of the semiconductor device of the present invention. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing the semiconductor device of 2nd Example.

  The semiconductor device includes an n-channel transistor. The n-channel transistor includes a first metal gate electrode made of a first metal material and a first polysilicon film made of a p-type conductivity type, which are sequentially formed on the first gate insulating film. A first gate electrode having one polycrystalline silicon gate electrode is provided.

  FIG. 1 is a diagram for explaining the function and effect of the semiconductor device. Generally, when a conductive polycrystalline silicon film is formed on a metal gate electrode, a Schottky junction is formed. Here, the band discontinuity from the Fermi level (Ef) on the metal side to the band edge (Ec or Ev) of the majority carrier on the silicon side appears as an energy barrier (Schottky barrier) of the majority carrier, and the interface resistance Give rise to Also, the higher the Schottky barrier, the larger the depletion layer width that spreads from the interface toward the silicon side, and the resistance value increases in silicon having a finite thickness.

  For example, when using a high dielectric constant gate insulating film having a higher dielectric constant than silicon dioxide such as hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, etc., titanium nitride, nitride, which is a metal material applied as a metal gate electrode Tantalum, hafnium nitride, titanium carbide, etc. have a relatively large work function Φm, which is larger than that of silicon in the intrinsic semiconductor state. In other words, the Fermi level Ef of the metal material applied to the metal gate electrode is closer to the valence band edge Ev than the conduction band edge Ec of silicon (hereinafter, a metal gate made of such a metal material). The electrode is described as a “p-type metal gate electrode”). Therefore, when n-type polycrystalline silicon is bonded to such a p-type metal gate electrode, the energy barrier from the metal Fermi level Ef near the p-type to the conduction band edge Ec is high. Since the depletion layer extends into the n-type polycrystalline silicon, the interface resistance increases.

  On the other hand, by joining polycrystalline silicon of p-type conductivity to the metal gate electrode near the p-type, the energy barrier from the metal Fermi level Ef near the p-type to the valence band edge Ev is lowered. Thus, the spread of the depletion layer into the p-type polycrystalline silicon is also reduced, and the resistance value can be reduced.

  For example, an n-channel transistor and a p-channel transistor that form a CMOS are desired to have highly targeted characteristics. For this purpose, the gate electrode of the n-channel transistor is made to be n-type conductive as in Patent Document 1 described above. The gate electrode of a p-channel transistor is usually made p-type conductive. In addition, the resistivity of the polycrystalline silicon itself is lower in the polycrystalline silicon of the n-type conductivity type than in the p-type conductivity type. For the purpose of reducing the resistance of the polycrystalline silicon itself, those skilled in the art will be able to It is usual to do n-type conductivity by doping a donor impurity as in 2.

  On the other hand, the present inventor has applied the interface between the metal material and the polycrystalline silicon in the laminated structure of the metal material and polycrystalline silicon, which is applied as the gate electrode of the field effect transistor using the high dielectric constant gate insulating film. We focused on the fact that the above phenomenon near the interface due to Schottky junction prevents the low resistance. The present invention is characterized in that the polycrystalline silicon gate electrode in contact with the metal gate electrode close to the p-type is made p-type conductivity type. Thereby, the interface resistance between the metal gate electrode near the p-type and the polycrystalline silicon can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings. The following examples are specific examples shown for a deeper understanding of the present invention, and the present invention is not limited to these specific examples.

(First embodiment)
This embodiment relates to a semiconductor device provided with n-channel and p-channel transistors. FIG. 4 is a cross-sectional view showing the semiconductor device of this embodiment, which includes an n-channel transistor Tr1 and a p-channel transistor Tr2.

  The transistor Tr1 includes a p-well 3 (corresponding to the first active region) provided in the silicon semiconductor substrate 1, an LDD region 51a and an n-type source / drain 52a provided in the p-well 3, 1 gate insulating film and a first gate electrode. The first gate insulating film includes a silicon oxide film or a silicon nitride film 5a in order from the semiconductor substrate side, and a high dielectric constant insulating film (High-K film) having a dielectric constant higher than that of silicon dioxide (from the first insulating material). 6a (corresponding to the film). With this silicon oxide film or silicon nitride film 5a, the interface characteristics of the semiconductor substrate 1 can be stabilized. Further, since the high dielectric constant insulating film 6a has a high dielectric constant, EOT (equivalent oxide film thickness) can be improved.

  The first gate electrode of the transistor Tr1 is, in order from the first gate insulating film side, a first metal gate electrode 7a made of a first metal material, and a p-type conductive type first polycrystalline silicon film. A first conductive type first polycrystalline silicon gate electrode 8a, a barrier metal film (corresponding to a conductive film) 9a made of a second metal material, and a gate wiring 10a. By using the first metal gate electrode 7a, a desired work function can be set in order to adjust the threshold voltage. Further, since the first metal gate electrode 7a cannot have a desired thickness due to the variability of the threshold voltage and the difficulty in processing, the gate electrode can be formed by using the first polycrystalline silicon gate electrode 8a that can be easily processed. A desired thickness can be obtained. By using the barrier metal film 9a, it is possible to prevent the first polycrystalline silicon gate electrode 8a and the gate wiring 10a from reacting and the metal constituting the gate wiring 10a from being silicided. Further, the gate wirings 10a can electrically connect the gate electrodes of a plurality of transistors.

  A cap insulating film 11a made of a silicon nitride film is provided on the gate wiring 10a of the transistor Tr1. This cap insulating film 11a is a hard mask for etching the first metal film, the polycrystalline silicon film, the second metal film, and the metal film for gate wiring into the shape of the gate electrode in a later step, It can be used as a mask at the time of impurity implantation for forming the LDD region and the source and drain. On both side surfaces of the gate electrode facing each other, offset spacers 12 made of a silicon nitride film are provided. A sidewall spacer 13 made of a silicon oxide film is further provided on the offset spacer 12.

  The transistor Tr2 includes an n-well 2 (corresponding to a second active region) provided in the semiconductor substrate 1, an LDD region 51b and a p-type source and drain 52b provided in the n-well 2, high dielectric constant insulation A second gate insulating film including a film (corresponding to a film made of a second insulating material) and a second gate electrode are formed. The second gate electrode is, in order from the second gate insulating film side, a second metal gate electrode 7b made of a third metal material, and a second multi-layer made of a p-type conductivity type second polycrystalline silicon film. It is composed of a crystalline silicon gate electrode 8b, a barrier metal film 9b, and a gate wiring 10b. Since the functions and configurations of the second gate insulating film and the second gate electrode are the same as those of the transistor Tr1, description thereof is omitted here.

  On the semiconductor substrate 1, an interlayer insulating film 14 is provided so as to cover the transistors Tr1 and Tr2. An upper layer wiring 16 is provided on the interlayer insulating film 14, and the upper layer wiring 16 is electrically connected to the source and drain 52 a and 52 b through a contact plug 15 provided so as to penetrate through the interlayer insulating film 14. Has been.

  In this embodiment, the first and second gate electrodes are respectively formed on the first and second metal gate electrodes 7a and 7b, respectively, and the p-type conductivity type first and second polycrystalline silicon gate electrodes 8a and 8a, respectively. 8b. The first and second gate insulating films have high dielectric constant insulating films 6a and 6b so as to be in contact with the first and second metal gate electrodes 7a and 7b, respectively. In this way, by joining the p-type conductive polysilicon to the p-type metal gate electrode, the energy barrier from the p-type metal Fermi level Ef to the valence band edge Ev is reduced. . As a result, since the spread of the depletion layer into the p-type polycrystalline silicon is also reduced, the resistance value can be reduced. Further, titanium nitride, tantalum nitride, or the like is formed on the polycrystalline silicon film as a barrier metal film that prevents combination with tungsten wiring. Similar to the metal gate electrode, these barrier metal films have a Fermi level near the valence band edge of silicon and are closer to the p-type. Therefore, as in this embodiment, by making polycrystalline silicon p-type conductivity, not only the Schottky junction with the metal gate electrode but also the interface caused by the Schottky junction with the barrier metal film. Resistance can also be reduced.

The high dielectric constant insulating films of the transistors Tr1 and Tr2 may be a single layer film or a stacked film of a plurality of films. Examples of the high dielectric constant insulating film include HfSiON, ZrO ₂ , Ta ₂ O ₅ , Nb ₂ O ₅ , Al ₂ O ₃ , HfO ₂ , ScO ₃ , Y ₂ O ₃ , La ₂ O ₃ , CeO ₃ , Pr _2. O ₃ , Nd ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O _3, and can be used at least one film selected from the group consisting of Lu ₂ O _3.

  The first and second metal gate electrodes may be a single layer film or a laminated film of a plurality of films, and at least selected from the group consisting of titanium nitride, tantalum nitride, hafnium nitride, and titanium carbide. A kind of membrane can be used.

  As the barrier metal film of the transistors Tr1 and Tr2, at least one film selected from the group consisting of titanium nitride, tantalum nitride, hafnium nitride, and titanium carbide can be used. A tungsten film can be used as the gate wiring.

Below, the manufacturing method of the semiconductor device of a present Example is demonstrated using FIGS.
As shown in FIG. 2, an element isolation region 4 is formed in a silicon semiconductor substrate 1 by an STI method or the like. Thereafter, the p well 3 and the n well 2 are formed by implanting impurities into the semiconductor substrate 1 in two stages. The surface of the semiconductor substrate 1 is thermally oxidized to form a silicon oxide film 5. The film thickness is 1 nm, for example. Note that a silicon oxynitride film may be formed instead of the silicon oxide film. Next, a high dielectric constant insulating film 6 is formed on the silicon oxide film 5. The film thickness is 3 nm, for example. A first metal film 7 for a metal gate electrode is formed on the high dielectric constant insulating film 6. The film thickness is 10 nm, for example. The first metal film 7 may be a stacked film of a plurality of metal layers. Next, an amorphous silicon film 8 is formed on the first metal film 7. The film thickness is, for example, 100 nm. The p-type conductivity impurity implanted in the silicon film in a later process tends to be localized at the grain boundary in the silicon. For this reason, in the process of FIG. 2, by forming an amorphous silicon film having a small grain size, the p-type conductivity type impurities can be easily distributed uniformly in the subsequent process. A p-type conductivity impurity is implanted into the amorphous silicon film 8. According to this method, since the dose amount and the implantation energy can be easily adjusted, the amorphous silicon film 8 can be doped with a high concentration impurity. B is used as the impurity element, and the dose is 5 × 10 ¹⁵ / cm ² and 5 keV. As the p-type conductivity impurity, for example, at least one element selected from the group consisting of B, In, and Ga can be used. The dose amount can be 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² . When the dose amount is 1 × 10 ¹⁵ / cm ² or more, the silicon film can have a desired low resistance value. When the dose amount is 1 × 10 ¹⁶ / cm ² or less, abnormal diffusion of p-type conductivity impurities can be prevented. The impurity implantation energy is selected so that the impurities are not mixed into the metal film or the high dielectric constant insulating film. Next, a p-type conductivity type polycrystalline silicon film 8 is formed by heat treatment using the amorphous silicon film as a polycrystalline silicon film. Also, annealing (annealing) for activating the implanted impurities can be performed during this heat treatment. As a result of implanting impurities under the above implantation conditions and activating them, the impurity concentration of the p-type conductivity in the polycrystalline silicon film 8 becomes 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Note that a polycrystalline silicon film may be formed in advance when the silicon film is formed, and the heat treatment for forming the polycrystalline silicon may be omitted in a later process.

  As shown in FIG. 3, a second metal film (conductor film) such as a titanium nitride film or a tantalum nitride film is formed on the p-type conductivity type polycrystalline silicon film 8. The film thickness is 10 nm, for example. Next, a fourth metal film such as a tungsten film is formed on the second metal film (conductor film). The film thickness is, for example, 80 nm. Further, a silicon nitride film is formed on the fourth metal film. The film thickness is, for example, 150 nm. Cap insulating films 11a and 11b functioning as hard masks are formed by patterning the silicon nitride film using a lithography technique. Using this hard mask, the silicon oxide film 5, the high dielectric constant insulating film 6, the first metal film 7, the p-type conductivity type polycrystalline silicon film 8, the second metal film, and the fourth metal film are formed. The laminate is patterned. Thereby, on the p-well 3, the first gate insulating film made of the silicon oxide film 5a and the high dielectric constant insulating film 6a, the first metal gate electrode 7a, the first polycrystalline silicon gate of the p-type conductivity type. A first gate electrode including the electrode 8a, the barrier metal film 9a, and the gate wiring 10a is formed. The silicon oxide film 5a, the high dielectric constant insulating film 6a, the first metal gate electrode 7a, the first polycrystalline silicon gate electrode 8a, the barrier metal film 9a, and the gate wiring 10a constitute the first stacked body. At the same time, on the n-well 2, a second gate insulating film made of the silicon oxide film 5 b and the high dielectric constant insulating film 6 b, a second metal gate electrode 7 b, a p-type conductivity type second multi-layer A second gate electrode including the crystalline silicon gate electrode 8b, the barrier metal film 9b, and the gate wiring 10b is formed. The silicon oxide film 5b, the high dielectric constant insulating film 6b, the second metal gate electrode 7b, the second polycrystalline silicon gate electrode 8b, the barrier metal film 9b, and the gate wiring 10b constitute a second stacked body. Next, after a silicon nitride film is formed on the semiconductor substrate 1, an offset spacer 12 is formed on the side walls of the first and second gate insulating films and the first and second gate electrodes by performing etch back. Form. The offset spacer 12 also has a function of preventing an oxidant and a reducing agent that cause an increase in EOT from entering the high dielectric constant insulating films 6a and 6b.

  As shown in FIG. 4, an LDD region 51a is formed by implanting n-type conductivity type impurities into the p-well 3. Next, an LDD region 51b is formed by implanting p-type conductivity impurities into the n-well 2. Further, after forming a silicon oxide film on the semiconductor substrate 1, etch back is performed to form sidewall spacers 13 via offset spacers 12 on the sidewalls of the first and second gate electrodes. Thereafter, an n-type conductivity impurity is implanted into the p-well 3 to form the source and drain 52a. Next, a source and drain 52b are formed by implanting a p-type conductivity impurity into the n-well 2. Thus, an n-channel transistor Tr1 and a p-channel transistor Tr2 are completed. An interlayer insulating film 14 is formed on the semiconductor substrate 1. Next, contact holes are formed in the interlayer insulating film 14 so as to expose the sources and drains 52a and 52b of the transistors Tr1 and Tr2. A conductive material is embedded in the contact hole. Thereafter, the contact plug 15 is formed by planarizing the conductive material by CMP treatment or the like. An upper wiring 16 is formed on the interlayer insulating film 14 so as to be electrically connected to the contact plug 15.

  In this embodiment, after the amorphous silicon film 8 is formed in the step of FIG. 2, a p-type conductivity type impurity is ion-implanted into the amorphous silicon film 8 to obtain a p-type conductivity type amorphous silicon film and did. However, instead of this step, an amorphous silicon film may be formed using a process gas containing p-type conductivity type impurities. According to this method, the step of implanting p-type conductivity impurities can be reduced. As another method, after the amorphous silicon film is formed, a p-type conductivity type impurity may be implanted into the amorphous silicon film by plasma doping. According to this method, the processing time can be shortened, and high-concentration impurities can be doped near the surface of the amorphous silicon film.

  In this embodiment, an amorphous silicon film is formed, a p-type conductivity impurity is introduced, and then the amorphous silicon film is converted into a polycrystalline silicon film by heat treatment. However, the method for forming the polycrystalline silicon film is not limited to this, and p-type conductivity impurities may be introduced after the polycrystalline silicon film is formed. According to this method, it is possible to reduce the heat treatment step for forming polycrystalline silicon.

(Second embodiment)
The present embodiment relates to an example in which the structure of the first embodiment is used as a peripheral transistor of a DRAM (Dynamic Random Access Memory). FIG. 16 is a cross-sectional view illustrating the semiconductor device of this example. As shown in FIG. 16, the semiconductor device of this embodiment is composed of a memory cell region X and a peripheral circuit region Y. Since the structure of the peripheral circuit region Y is the same as that of the first embodiment, the description thereof is omitted.

  In the memory cell region X, a trench-type gate electrode 21 provided in a semiconductor substrate, a gate insulating film 22, and a memory cell transistor Tr 3 including a source and a drain 23 are provided. A first interlayer insulating film 42, a second interlayer insulating film 49, and a third interlayer insulating film 50 are sequentially provided on the semiconductor substrate. A bit line 34 is provided in the first interlayer insulating film 42 so as to be connected to one of the source and drain 23. In the bit line 34, an n-type conductivity type polycrystalline silicon film 30b, a barrier metal film 33, and a fourth metal film 32 are stacked in this order from one side of the source and drain. A cap insulating film 31 is provided on the bit line 34.

  A capacitive contact plug 60 is provided in the first interlayer insulating film 42 so as to be connected to the other of the source and the drain 23. The capacitor contact plug 60 is provided with a polycrystalline silicon (DOPOS) film 45 doped with impurities, a cobalt silicide film 46, and a tungsten film 47 in order from the other side of the source and drain. The bit line 34 and the capacitor contact plug 60 are electrically insulated by the offset spacer insulating film 35 and the capacitor contact sidewall 43. A capacitor contact pad 48 is provided in the second interlayer insulating film 49 so as to be connected to the capacitor contact plug. A capacitor Cap including a lower electrode 53, a capacitor insulating film 58, and an upper electrode 55 is provided so as to be connected to the capacitor contact pad 48.

  A memory cell is composed of the capacitor and the transistor, and a DRAM is composed of a plurality of memory cells.

  In the present embodiment, the contact (interface) resistance of the polycrystalline silicon film / metal interface can be reduced in the first and second gate electrodes in the peripheral circuit region Y. Further, titanium nitride, tantalum nitride or the like is formed on the polycrystalline silicon film as a barrier metal film for preventing reaction with the tungsten wiring. For this reason, the resistance value resulting from the Schottky junction between the polycrystalline silicon film and the barrier metal film can also be reduced. As a result, the overall performance of the semiconductor device including the DRAM can be improved.

  Below, with reference to FIGS. 5-16, the manufacturing method of the semiconductor device of a present Example is demonstrated. In the following, a region for forming a memory cell before completion and a region for forming a peripheral circuit are referred to as a “memory cell formation region A” and a “peripheral circuit formation region B”, respectively. X and “peripheral circuit region Y” will be described separately.

  As shown in FIG. 5, the element isolation region 4 is formed in the semiconductor substrate 1 by STI method or the like. Next, the p well 3 and the n well 2 are formed in the peripheral circuit formation region B, and a p-type conductivity impurity is implanted into the memory cell formation region A. A trench is formed in the memory cell formation region by using a lithography technique. A gate insulating film 22 made of a silicon oxide film is formed on the inner wall of the trench by heat treatment or the like. Thereafter, a cap insulating film 31 made of a gate electrode 21 and a silicon nitride film is formed so as to fill the trench. Thereafter, an n-type conductivity impurity is implanted into the memory cell formation region A, thereby forming the source and drain 23. Thereby, the memory cell transistor Tr3 is completed. After forming an insulating film on the semiconductor substrate 1 by CVD or the like, the bit contact interlayer insulating film 24 is formed by removing the insulating film on the peripheral circuit forming region B by lithography. Next, a silicon oxide film 25, a high dielectric constant insulating film 26, and a first metal film 27 are formed on the semiconductor substrate 1.

  As shown in FIG. 6, after the first mask 28a is formed on the peripheral circuit formation region B, the silicon oxide film 25 on the memory cell formation region A and the high dielectric constant are formed by etching using the first mask 28a. The insulating film 26 and the first metal film 27 are removed.

  As shown in FIG. 7, after removing the first mask 28a, a second mask 28b having an opening 29 exposing the bit contact interlayer insulating film 24 in the memory cell formation region A is formed on the semiconductor substrate 1. To do. Using the second mask 28b, the exposed bit contact interlayer insulating film 24 is removed.

  As shown in FIG. 8, after removing the second mask 28 b, a polycrystalline silicon film 30 is formed on the semiconductor substrate 1. After the third mask 28c is provided on the memory cell formation region A, a p-type conductivity type impurity is ion-implanted into the polycrystalline silicon film 30 on the peripheral circuit formation region B, thereby forming a p-type conductivity type. A polycrystalline silicon film 30a is formed.

  As shown in FIG. 9, after removing the third mask 28c, a fourth mask 28d is formed so as to cover the polycrystalline silicon film 30a on the peripheral circuit formation region B. An n-type conductivity type polycrystalline silicon film 30b is formed by ion-implanting n-type conductivity type impurities into the polycrystalline silicon film 30 on the memory cell formation region A.

  As shown in FIG. 10, a second metal film 33 made of tungsten nitride, a fourth metal film 32 made of tungsten, and a silicon nitride film 31 are sequentially formed on the polycrystalline silicon films 30a and 30b. By patterning the silicon nitride film 31 using the fifth mask 28e, a hard mask made of the cap insulating film 31 is formed.

  As shown in FIG. 11, by removing the fifth mask 28e and then performing etching using a hard mask, the fourth metal film 32, the second metal film 33, and the p-type are formed in the peripheral circuit formation region B. The conductive type polycrystalline silicon film 30a, the first metal film 27, the high dielectric constant insulating film 26, and the silicon oxide film 25 are patterned. At the same time, in the memory cell formation region A, the fourth metal film 32, the second metal film 33, and the n-type conductivity type polycrystalline silicon film 30b are patterned. As a result, in the peripheral circuit formation region B, the first gate insulating film and the first gate electrode provided on the p well 3, and the second gate insulating film and the second gate electrode provided on the n well 2. In the memory cell formation region A, a bit line is formed.

  As shown in FIG. 12, a silicon nitride film 35 is formed as an offset spacer insulating film on the semiconductor substrate 1 by a CVD method or the like. After a sixth mask (not shown) is formed on the memory cell formation region A, the silicon nitride film 35 is etched back. Thus, offset spacers 36 made of a silicon nitride film are formed on the side walls of the first and second gate insulating films and the first and second gate electrodes. Next, after removing the sixth mask, an LDD region 37a is formed in the p-well 3 and an LDD region 37b is formed in the n-well 2 by a known ion implantation method.

  As shown in FIG. 13, after the silicon oxide film 38 is formed on the semiconductor substrate 1, a seventh mask (not shown) is formed on the memory cell formation region A. Thereafter, the silicon oxide film 38 is etched back to form an offset spacer 39 made of a silicon nitride film on the side walls of the first and second gate insulating films and the first and second gate electrodes. Next, after removing the seventh mask, the source and drain 40a are formed in the p-well 3 and the source and drain 40b are formed in the n-well 2 by a known ion implantation method.

  As shown in FIG. 14, after the silicon oxide film is formed on the semiconductor substrate 1, the first interlayer insulating film 42 is formed by performing a CMP process on the silicon oxide film using the cap insulating film as a stopper. Thereafter, a contact hole 41 is formed in the first interlayer insulating film 42 so as to expose the source and drain 40a and 40b in the peripheral circuit formation region B by lithography. Next, a capacitor contact hole 44 is formed in the first interlayer insulating film 42 so as to expose the source and drain 23 in the memory cell formation region A by lithography. Next, after forming a silicon nitride film on the memory cell formation region A, etch back is performed to form the capacitor contact sidewall 43 on the inner wall side surface of the capacitor contact hole 44.

  As shown in FIG. 15, after providing a mask (not shown) on the peripheral circuit formation region B, a polycrystalline silicon film (DOPOS) 45 doped with impurities is formed below the capacitor contact hole 44. After removing the mask, a cobalt film is formed on the polycrystalline silicon film 45 and the source and drains 40a and 40b by sputtering or the like. The cobalt film is silicided by heat treatment to form a cobalt silicide film 46. Next, after a tungsten film is formed so as to fill the capacitor contact hole 44 and the contact hole 41, the tungsten film on the first interlayer insulating film 42 is removed by planarization treatment. Thereby, in the memory cell formation region A, the capacitor contact plug 60 composed of the polycrystalline silicon film 45, the cobalt silicide film 46, and the tungsten film 47 is formed. In the peripheral circuit formation region B, a contact plug 43 composed of a cobalt silicide film 46 and a tungsten film 43 is formed. A tungsten film is formed on the first interlayer insulating film 42 and then patterned. As a result, the capacitor contact pad 48 connected to the capacitor contact plug 60 in the memory cell formation region A and the wiring 62 connected to the contact plug 43 in the peripheral circuit formation region B are formed.

  As shown in FIG. 16, a silicon nitride film is formed on the first interlayer insulating film 42. Thereafter, the second interlayer insulating film 49 is formed by planarizing the silicon nitride film by CMP. A third interlayer insulating film 50 made of a silicon oxide film is formed on the second interlayer insulating film 49. Thereafter, capacitor holes are formed in the second and third interlayer insulating films 49 and 50. A lower electrode 53 is formed on the inner wall of the capacitor hole. Thereafter, the third interlayer insulating film 50 in the memory cell formation region A is removed by a lithography technique. A capacitive insulating film 58 is formed on the surface of the lower electrode 53. Thereafter, the upper electrode 55 is formed so as to fill the capacitor holes and between the capacitor holes. Thus, a capacitor having the lower electrode 53, the capacitor insulating film 58, and the upper electrode 55 is formed. The capacitor is electrically connected to one of the source and the drain 23 via the capacitive contact pad 48 and the capacitive contact plug 60. Thereby, the semiconductor device of this embodiment including a DRAM (Dynamic Random Access Memory) having a capacitor, a transistor, and a bit line is completed.

  In the above embodiment, the bit line 34 is made of an n-type conductivity type polycrystalline silicon film, a barrier metal film, and a fourth metal film. However, the structure of the bit line is not limited to this, and the polycrystalline silicon film may be omitted and a bit line made of a barrier metal film and a fourth metal film may be used. In this case, the step of FIG. 16 for injecting an n-type conductivity type impurity into the polycrystalline silicon film for the bit line can be eliminated.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 N well 3 P well 4 Element isolation region 5, 5a, 5b Silicon oxide film or silicon nitride film 6, 6a, 6b High dielectric constant insulating film (High-K film)
7 first metal film 7a first metal gate electrode 7b second metal gate electrode 8 amorphous silicon film 8a p-type conductivity type first polycrystalline silicon film 8b p-type conductivity type second polycrystalline silicon film 9, 9a, 9b Barrier metal film 10 Fourth metal film 10a, 10b Gate wiring 11 Silicon nitride film 11a, 11b Cap insulating film 12 Offset spacer 13 Side wall spacer 14 Interlayer insulating film 15 Contact plug 16 Upper wiring 21 Gate electrode 22 Gate insulating film 23 Source and drain 24 Bit contact interlayer insulating film 25 Silicon oxide film 26 High dielectric constant insulating film 27 First metal film 28a First mask 28b Second mask 28c Third mask 28d Fourth mask 28e Fifth mask 29 contact hole 30 polycrystalline silicon film 30a p-type conductive Electrically-type polycrystalline silicon film 30b n-type conductive-type polycrystalline silicon film 31 Cap insulating film 32 Fourth metal film 33 Second metal film 34 Bit line 35 Insulating film for offset spacer 36 Offset spacers 37a and 37b LDD region 38 Silicon oxide film 39 Offset spacers 40a, 40b Source and drain 41 Contact hole 42 First interlayer insulating film 43 Capacitor contact sidewall 44 Capacitor contact hole 45 Polycrystalline silicon (DOPOS) film 46 Cobalt silicide film 47 Tungsten film 48 Capacitor contact Pad 49 Second interlayer insulating film 50 Third interlayer insulating film 51a, 51b LDD regions 52a, 52b Source and drain 53 Lower electrode 55 Upper electrode 58 Capacitor insulating film 60 Capacitor contact plug 62 Wiring A Memory cell formation region B peripheral circuit formation region Cap capacitor Tr1 n-channel transistor Tr2 p-channel type transistor Tr3 memory cell transistor X memory cell region Y surrounding the path area of the

Claims (20)

A p-type conductivity type first active region formed on the main surface of the semiconductor substrate;
A first gate insulating film covering a part of the surface of the first active region and including a first insulating material having a dielectric constant higher than that of silicon dioxide;
A first metal gate electrode formed on the first active region via the first gate insulating film and made of a first metal material;
A first polycrystalline silicon gate electrode formed on the first metal gate electrode and made of a p-type conductivity type first polycrystalline silicon film;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein a work function of the first metal material is larger than a work function of silicon in an intrinsic semiconductor state.   3. The semiconductor device according to claim 1, wherein the first metal material is made of at least one film selected from the group consisting of titanium nitride, tantalum nitride, hafnium nitride, and titanium carbide.   4. The method according to claim 1, further comprising a conductive film made of a second metal material formed on the first polycrystalline silicon film and having a work function larger than that of intrinsic semiconductor silicon. 2. A semiconductor device according to item 1.   The semiconductor device according to claim 4, wherein the second metal material is made of at least one film selected from the group consisting of titanium nitride, tantalum nitride, hafnium nitride, and titanium carbide. The first insulating material is HfSiON, ZrO ₂ , Ta ₂ O ₅ , Nb ₂ O ₅ , Al ₂ O ₃ , HfO ₂ , ScO ₃ , Y ₂ O ₃ , La ₂ O ₃ , CeO ₃ , Pr ₂ O. ₃ , Nd ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O _3, and the semiconductor device according to any one of claims 1 to 5, characterized in that it consists of at least one film selected from the group consisting of Lu ₂ O _3. 7. The p-type conductivity impurity concentration in the first polycrystalline silicon film is 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ^3. 7. Semiconductor device.   The semiconductor device according to claim 1, wherein the first polycrystalline silicon film contains at least one element selected from the group consisting of B, In, and Ga. An n-type conductivity type second active region formed at a position different from the first active region on the main surface of the semiconductor substrate;
A second gate insulating film covering a part of the surface of the second active region and including a second insulating material having a dielectric constant higher than that of silicon dioxide;
A second metal gate electrode formed on the second active region via the second gate insulating film and made of a third metal material;
A second polycrystalline silicon gate electrode formed on the second metal gate electrode and made of a p-type conductivity type second polycrystalline silicon film;
The semiconductor device according to claim 1, comprising: The first insulating material and the second insulating material are made of the same material,
The first metal material and the third metal material are made of the same material,
The semiconductor device according to claim 9, wherein the first polycrystalline silicon film and the second polycrystalline silicon film have the same impurity concentration. Furthermore, it has a peripheral circuit and a DRAM,
The first gate insulating film, the first metal gate electrode, and the first polycrystalline silicon gate electrode constitute an n-channel transistor disposed in the first active region,
The second gate insulating film, the second metal gate electrode, and the second polycrystalline silicon gate electrode constitute a p-channel transistor disposed in the second active region,
The peripheral circuit includes the n-channel transistor and the p-channel transistor,
The DRAM is electrically connected to the memory cell transistor, a capacitor electrically connected to one of the source and drain of the memory cell transistor, and the other of the source and drain of the memory cell transistor. 11. The semiconductor device according to claim 9, comprising a bit line having an n-type conductivity type polycrystalline silicon film. A semiconductor device having an n-channel transistor and a p-channel transistor,
The n-channel transistor and the p-channel transistor are respectively
A gate insulating film provided on a semiconductor substrate and including an insulating film having a dielectric constant higher than that of silicon dioxide;
A gate electrode provided on the gate insulating film and having a metal gate electrode made of a metal material in order from the gate insulating film side; and a p-type conductivity type polycrystalline silicon film;
A semiconductor device comprising: Forming a p-type conductivity type first active region on a main surface of a semiconductor substrate;
Forming an insulating film having a dielectric constant higher than that of silicon dioxide, a first metal film, and a laminated film having a p-type conductivity type polycrystalline silicon film in order so as to cover the main surface of the semiconductor substrate; ,
The laminated film is processed so as to cover a part of the surface of the first active region, and a first gate insulating film made of the insulating film, a first metal gate electrode made of the first metal film, And forming a first stacked body having a first polycrystalline silicon gate electrode made of the p-type conductivity type polycrystalline silicon film,
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 13, wherein a metal material having a work function larger than that of intrinsic semiconductor silicon is used as the first metal film.   15. The semiconductor device according to claim 13, wherein at least one metal material selected from the group consisting of titanium nitride, tantalum nitride, hafnium nitride, and titanium carbide is used as the first metal film. Production method. Before the step of forming the first stacked body, a second metal film made of a second metal material having a work function larger than that of silicon in an intrinsic semiconductor state is formed on the p-type conductivity type polycrystalline silicon film. Further comprising the step of forming
In the step of forming the first stacked body, the second metal film is also processed so as to cover a part of the surface of the first active region, and the first gate insulating film, the first The first stacked body having a conductive film made of the second metal film in addition to the metal gate electrode and the first polycrystalline silicon gate electrode is formed. 2. A method for manufacturing a semiconductor device according to item 1.   The method for manufacturing a semiconductor device according to claim 16, wherein at least one film selected from the group consisting of titanium nitride, tantalum nitride, hafnium nitride, and titanium carbide is used as the second metal material. Forming a second active region of n-type conductivity at a position different from the first active region of the main surface of the semiconductor substrate;
In the step of forming the first laminate,
Processing the laminated film so as to cover a part of the surface of the second active region in addition to a part of the surface of the first active region, and a second gate insulating film made of the insulating film; A second stacked body having a second metal gate electrode made of the first metal film and a second polycrystalline silicon gate electrode made of the p-type conductivity type polycrystalline silicon film; The method for manufacturing a semiconductor device according to claim 13, wherein the semiconductor device is formed simultaneously with the stacked body. Before the step of forming the laminated film,
Forming a memory cell transistor in a memory cell forming region different from the first and second active regions on the main surface of the semiconductor substrate;
The step of forming the laminated film includes
Forming an insulating film having a dielectric constant higher than that of silicon dioxide, a first metal film, and a polycrystalline silicon film in order so as to cover the main surface of the semiconductor substrate;
Forming the polycrystalline silicon film of the p-type conductivity by converting the polycrystalline silicon film of the first and second active regions to a p-type conductivity,
Forming an n-type conductivity type polycrystalline silicon film by converting the polycrystalline silicon film in the memory cell formation region to an n-type conductivity type;
Have
In the step of forming the first laminate and the second laminate,
Processing the n-type conductivity type polycrystalline silicon film in the memory cell formation region of the stacked film to form a bit line made of the n-type conductivity type polycrystalline silicon film;
The bit line is formed to be connected to one of a source and a drain of the memory cell transistor,
19. The method for manufacturing a semiconductor device according to claim 18, further comprising a step of forming a capacitor so as to be connected to the other of the source and the drain of the memory cell transistor. The p-type conductivity type polycrystalline silicon film is formed by any one of the following steps (1) to (6). A method for manufacturing a semiconductor device.
(1) forming a p-type conductivity type polycrystalline silicon film;
(2) A step of forming a polycrystalline silicon film by performing a heat treatment on the amorphous silicon film after forming a p-type conductivity type amorphous silicon film,
(3) a step of ion-implanting a p-type conductivity type impurity into the polycrystalline silicon film after forming the polycrystalline silicon film;
(4) A step of performing plasma doping of a p-type conductivity type impurity in the polycrystalline silicon film after forming the polycrystalline silicon film;
(5) A step of forming a polycrystalline silicon film by forming an amorphous silicon film, then ion-implanting p-type conductivity type impurities into the amorphous silicon film, and further heat-treating the amorphous silicon film,
(6) A step of forming a polycrystalline silicon film by forming an amorphous silicon film, plasma doping with an impurity of p-type conductivity in the amorphous silicon film, and further performing a heat treatment on the amorphous silicon film.

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