JP5550286B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP5550286B2
JP5550286B2 JP2009195360A JP2009195360A JP5550286B2 JP 5550286 B2 JP5550286 B2 JP 5550286B2 JP 2009195360 A JP2009195360 A JP 2009195360A JP 2009195360 A JP2009195360 A JP 2009195360A JP 5550286 B2 JP5550286 B2 JP 5550286B2
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film
region
insulating film
formed
gate electrode
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JP2011049282A (en
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和治 山部
泰弘 谷口
省史 吉田
史朗 蒲原
孝生 組橋
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ルネサスエレクトロニクス株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11573Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MONOS (Metal Oxide Nitride Oxide Semiconductor) type nonvolatile memory and a technique effective when applied to a manufacturing method thereof.

  A non-volatile memory having a MONOS structure is an FET composed of an ONO (Oxide Nitride Oxide) film in which a silicon nitride film is formed between two silicon oxide films, for example, a non-volatile memory such as a flash memory. It is widely used as a memory cell of a volatile memory.

  In recent years, there has been a strong demand for miniaturization of MISFETs (Metal insulator Semiconductor Field Effect Transistors) used in logic circuits, and has a high dielectric constant as one of the structures for miniaturizing MISFETs. A MISFET using a high-k film using hafnium dioxide or the like as a gate insulating film has attracted attention.

  Therefore, with the miniaturization of semiconductor elements, legacy polysilicon that does not require much speed compared to logic MISFETs, such as MONOS type non-volatile memories and high voltage MISFETs, for the purpose of further reducing element area and cost. It was examined that a gate MISFET region and a logic MISFET region including a high-k film + metal gate MISFET and required to have high performance were simultaneously formed.

  In Patent Document 1 (Japanese Patent Laid-Open No. 2002-110824), a non-volatile structure in which a metal film (control gate electrode) is formed through a high dielectric constant gate insulating film formed on a conductive film (floating gate electrode). Technology for realizing a nonvolatile semiconductor memory device having a memory cell portion and a peripheral transistor having a metal film (gate electrode) formed on the same substrate through a high dielectric constant gate insulating film formed on the surface of the semiconductor substrate Is disclosed.

  Patent Document 2 (Japanese Patent Application Laid-Open No. 2004-266203) discloses that in a MONOS type nonvolatile memory element, a decrease in drain current (decrease in current driving capability) accompanying the number of rewrites is suppressed, and long-term reliability of a semiconductor element is improved. A technique that can be secured and highly integrated is disclosed.

  Patent Document 3 (Japanese Patent Laid-Open No. 2006-19351) discloses a MISFET having a relatively high ON current and a relatively low threshold voltage in a MISFET using a high dielectric constant film as a gate insulating film. A technique for forming and preventing a reaction layer from being formed by annealing on a part of the high dielectric constant film is disclosed. Further, by forming a protective film made of an insulating film on the upper part of the dummy gate, it is possible to prevent silicide from being formed on the dummy gate and to facilitate the process of removing the dummy gate.

  In Patent Document 4 (Japanese Patent Application Laid-Open No. 2007-12922), a dummy gate is formed, a source / drain region is formed, then the dummy gate is removed, and a gate electrode having a damascene structure is formed to reduce the gate electrode. A technique for realizing a semiconductor device that is resistant, improves reliability, and is advantageous for manufacturing cost and miniaturization is disclosed. In this document, an insulating film is formed between the high dielectric constant film below the gate electrode and the silicon substrate.

JP 2002-110824 A JP 2004-266203 A JP 2006-19351 A JP 2007-12922 A

  As miniaturization of conventional MISFETs having a gate electrode made of polysilicon proceeds, the gate resistance increases, the polysilicon gate is depleted, B (boron) leakage from the P-type gate electrode to the channel, gate edge roughness and There is a problem that variations in the threshold voltage Vth become obvious and reliability is lowered. As a method for solving this problem, the use of a high-k film having a high dielectric constant as the gate insulating film of the MISFET has been studied.

  The process of forming a high-k film as a gate insulating film and forming a metal gate electrode using a metal material on the high-k film improves the performance of the device in a region where the gate length is 0.1 μm or less and the gate oxide film is 3 nm or less. Aim. However, in the gate first process in which the source / drain regions are formed after the gate electrode is formed, the device is easily deteriorated by a process of heating at about 1000 ° C. such as source / drain activation annealing.

On the other hand, in the gate last process in which the gate insulating film and the gate electrode are formed after the formation of the source / drain region, the gate electrode and the high-k film are formed after the activation annealing step of the source / drain region. And the high-k film is not exposed to high heat. As an example of the gate last process, in a damascene process in which a groove is formed after an interlayer insulating film is formed, and a gate insulating film and a gate electrode are formed inside the groove, the gate electrode material includes Ti (titanium) or the like. There is a method using metal. This prevents impurities (for example, B (boron) or BF 2 (boron fluoride)) from leaking into the gate insulating film from the conventional gate electrode made of polysilicon or the like, and prevents the metal gate electrode and the high-k film from It is possible to prevent the formation of reactants between the two.

  However, the damascene metal gate process has a problem that the cost increases due to an increase in the number of processes, and an RIE (Reactive Ion Etching) process for removing the dummy gate formed in the gate electrode formation region before forming the metal gate electrode. As a result, there is a problem that the gate insulating film or the semiconductor substrate under the dummy gate is damaged. In addition, there is a problem that a malfunction of the circuit occurs due to the etching residue of the metal film that is the material of the metal gate.

  Therefore, when simultaneously forming a low voltage MIS, a MONOS memory and a high voltage MISFET used for a logic MIS or the like, they are not simply formed on the same semiconductor substrate, but the deterioration of each element is reduced, and the number of processes is reduced. It is necessary to form so as not to increase as much as possible.

  An object of the present invention is to provide a technique for forming a high-performance low-voltage MIS, a MONOS memory, and a highly reliable high-voltage MISFET on the same semiconductor substrate.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A semiconductor device according to an invention of the present application is:
A non-volatile memory formed in the first region of the main surface of the semiconductor substrate; a first MISFET formed in the second region of the main surface of the semiconductor substrate; and a third region of the main surface of the semiconductor substrate; And a second MISFET that operates at a lower voltage than the first MISFET,
The nonvolatile memory is
A first gate electrode formed on a main surface of the semiconductor substrate in the first region via a first gate insulating film including at least a potential barrier film and a charge retention film stacked on the potential barrier film; ,
A first source region and a first drain region formed in the semiconductor substrate of the first region;
Have
The first MISFET is
A second gate electrode formed on a main surface of the semiconductor substrate in the second region via a second gate insulating film;
A second source region and a second drain region formed in the semiconductor substrate of the second region;
Have
The second MISFET is
A third gate electrode formed on a main surface of the semiconductor substrate in the third region via a third gate insulating film thinner than the second gate insulating film;
A first high dielectric constant film having a dielectric constant higher than that of the second gate insulating film, formed in contact with a side surface and a bottom surface of the third gate electrode;
A third source region and a third drain region formed in the semiconductor substrate of the third region;
An interlayer insulating film formed on a main surface of the semiconductor substrate and on a side of the third gate electrode;
The height of the upper surface of the interlayer insulating film in the third region is lower than the height of the upper surface of the interlayer insulating film formed on the second gate electrode, and the height of the upper surface of the third gate electrode. It is characterized by having substantially the same height.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A semiconductor device having each of a high-performance low-voltage MIS, a MONOS memory, and a highly reliable high-voltage MISFET can be provided on the same semiconductor substrate.

It is principal part sectional drawing which shows the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 3 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 2; FIG. 4 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 3; FIG. 5 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 4; FIG. 6 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 5; FIG. 7 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 6; FIG. 8 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 7; FIG. 9 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 8; FIG. 10 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 9; FIG. 11 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 10; FIG. 12 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 11; FIG. 13 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 12; FIG. 14 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 13; FIG. 15 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 14; FIG. 16 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 15; FIG. 17 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 16; FIG. 18 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 17; FIG. 19 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 18; It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. FIG. 21 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 20; FIG. 22 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 21; FIG. 23 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 22; FIG. 24 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 23; FIG. 25 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 24; FIG. 26 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 25; It is principal part sectional drawing which shows the semiconductor device which is Embodiment 3 of this invention. It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 3 of this invention. FIG. 29 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 28; FIG. 30 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 29; FIG. 31 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 30; FIG. 32 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 31; It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 4 of this invention. FIG. 34 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 33; FIG. 35 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 34; FIG. 36 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 35; FIG. 37 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 36; FIG. 38 is an essential part cross sectional view showing the method of manufacturing the semiconductor device following FIG. 37; FIG. 39 is an essential part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 38; FIG. 40 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 39; FIG. 41 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 40; FIG. 42 is an essential part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 41; FIG. 43 is a main part cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 42;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. In addition, in the embodiment, etc., when “consisting of A” or “consisting of A” is used to exclude other elements, unless specifically stated that only those elements are stated. It goes without saying that it is not.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In addition, when referring to materials, etc., unless specified otherwise, or in principle or not in principle, the specified material is the main material, and includes secondary elements, additives It does not exclude additional elements. For example, unless otherwise specified, the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (for example, SiGe) having silicon as a main element.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

(Embodiment 1)
The semiconductor device of this embodiment has a MONOS type nonvolatile memory (hereinafter simply referred to as a MONOS memory), a high voltage MISFET, and a low voltage MISFET on the same substrate. A MONOS type nonvolatile memory has an FET (Field Effect) having a three-layered gate insulating film in which a silicon nitride film as a charge storage film is formed between a bottom oxide film as a potential barrier film and a top oxide film. Transistor). The high voltage MISFET is a MIS type transistor used for a protection element in the I / O region or a booster circuit for a power supply. The low voltage MISFET is a MIS type transistor that is used in a logic circuit or the like, operates at a voltage lower than that of the high voltage MISFET, and requires high performance such as fast operation. In addition, the film thickness of the gate insulating film of the low voltage MISFET is smaller than the film thickness of the gate insulating film of the high voltage MISFET, and the high voltage MISFET has a higher breakdown voltage than the low voltage MISFET.

  FIG. 1 shows a semiconductor device of the present embodiment. The left region of FIG. 1 shows the MONOS memory formation region (ie, the MONOS memory formation region), the central region shows the high voltage MISFET formation region (ie, the high voltage MISFET formation region), and the right region is low. A voltage MISFET formation region (that is, a low voltage MISFET formation region) is shown.

  In FIG. 1, reference numeral 1 denotes a silicon substrate, 1a denotes a p-well formed on the main surface of the silicon substrate 1, and 2 denotes a MONOS memory formed on the main surface of the silicon substrate 1 on which the p-well 1a is formed. The element isolation layer formed in each boundary of a formation area, a high voltage MISFET formation area, and a low voltage MISFET formation area is shown.

  Reference numeral 4 denotes a thick gate oxide film formed in contact with the upper surface of the p well 1a in the high voltage MISFET formation region, and reference numeral 8 denotes an ONO film formed in contact with the upper surface of the p well 1a in the MONOS memory formation region. , 9 indicates a gate electrode of the MONOS memory formed on the ONO film 8, and 10 indicates a gate electrode of the high voltage MISFET formed on the thick gate oxide film 4.

  Here, the ONO film 8 includes three layers of a bottom oxide film that is a potential barrier film, a silicon nitride film that is a charge holding film formed on the bottom oxide film, and a top oxide film that is formed on the silicon nitride film. A gate insulating film containing

  Reference numeral 17 denotes a gate oxide film that is formed in contact with the upper surface of the p-well 1a in the low-voltage MISFET formation region and is thinner than the thick-film gate oxide film 4. Reference numeral 18 denotes a high-k film formed on the gate oxide film 17, which is an insulating film having a dielectric constant higher than that of the thick gate oxide film 4, and 20 is formed on the high-k film 18. A metal gate electrode made of a metal material is shown. The high-k film 18 is formed in contact with the lower surface and the side wall of the metal gate electrode 20.

  Reference numeral 13 denotes side wall spacers made of insulating films formed on the side walls of the gate electrodes 9, 10 and the high-k film 18 on the side opposite to the side wall in contact with the metal gate electrode 20.

  Reference numeral 12 denotes extension regions of the MONOS memory, the high voltage MISFET, and the low voltage MISFET, which are formed below the sidewall spacer 13 and shallowly on the upper surface of the p well 1a.

  Reference numeral 14 is formed deeper than the extension region 12, and is an end portion of the extension region 12 from the end opposite to the end portion of the gate electrode of each of the MONOS memory, the high voltage MISFET, and the low voltage MISFET. The source / drain regions of the MONOS memory, the high voltage MISFET, and the low voltage MISFET formed on the upper surface of the p well 1a over the isolation layer 2 are shown.

  Reference numeral 15 denotes silicide formed on the upper surfaces of the source / drain regions 14 and the gate electrodes 9, 10. Reference numeral 16 denotes a main surface of the silicon substrate 1 so as to cover the MONOS memory, the high voltage MISFET, and the low voltage MISFET. The formed interlayer insulating film is shown.

  The height of the upper surface of the interlayer insulating film 16 in the low voltage MISFET forming region is lower than the height of the upper surface of the interlayer insulating film 16 formed in the MONOS memory forming region and the high voltage MISFET forming region. The height is substantially the same as the height of the upper surface. The silicide 15 on the upper surfaces of the gate electrode 9 of the MONOS memory and the gate electrode 10 of the high voltage MISFET is covered with the interlayer insulating film 16 and is not exposed. Further, the upper surface of the metal gate electrode 20 of the low voltage MISFET is not covered with the interlayer insulating film 16 and is exposed to the main surface side of the silicon substrate 1. That is, the interlayer insulating film 16 is formed only on the side of the metal gate electrode 20 in the low voltage MISFET formation region.

  Note that the thickness of the thick gate oxide film 4 which is the gate insulating film of the high voltage MISFET is thicker than the thickness of the gate oxide film 17 of the low voltage MISFET. Further, the gate length of the gate electrode 10 of the high voltage MISFET is formed longer than the gate length of the metal gate electrode 20 of the low voltage MISFET.

  Hereinafter, the manufacturing method of the MONOS memory, the high voltage MISFET, and the low voltage MISFET of this embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 2, a trench having a depth of about 200 to 400 nm is dug in the main surface of a silicon substrate (semiconductor substrate) 1 by dry etching, and silicon oxide is buried in the trench, and then CMP (Chemical Mechanical Polishing) is performed. ) To flatten the main surface of the silicon substrate 1 and form an element isolation layer 2 having a so-called STI (Shallow Trench Isolation) structure. Thereafter, an oxide film 3 is formed on the entire main surface of the silicon substrate 1 by thermal oxidation, and then p-type impurities (for example, B or BF 2 ) are ion-implanted into the main surface of the silicon substrate 1 using the oxide film 3 as a through film. As a result, a p-well 1 a is formed on the main surface of the silicon substrate 1. Here, FIG. 2 shows the formation regions of the MONOS memory, the high voltage MISFET, and the low voltage MISFET in order from the left as in FIG.

  Next, as shown in FIG. 3, the oxide film 3 on the p-well 1a is removed by dry etching or wet etching, and a thick gate oxide film 4 is formed in the high voltage MISFET formation region by a well-known two-type gate oxidation process. Thereafter, a thin gate oxide film 5 is formed in the MONOS memory formation region and the low voltage MISFET formation region.

  That is, after a thick silicon oxide film is deposited on the entire main surface of the silicon substrate 1 from which the oxide film 3 has been removed by a CVD (Chemical Vapor Deposition) method, the high voltage MISFET formation region is covered with a photoresist. Thereafter, using the photoresist as a mask, the silicon oxide film in the MONOS memory formation region and the low voltage MISFET formation region is selectively removed by dry etching or wet etching, and the thick gate gate made of the thick silicon oxide film is formed in the high voltage MISFET formation region. After the oxide film 4 is formed, the photoresist is removed by ashing. Thereafter, the silicon substrate 1 is thermally oxidized to form a thin gate oxide film 5 in the MONOS memory formation region and the low voltage MISFET formation region, thereby performing two-type gate oxidation. At this time, the upper surface of the p well 1a under the thick gate oxide film 4 in the high voltage MISFET formation region is also slightly oxidized.

  Thereby, a relatively thick thick gate oxide film 4 is formed in the high voltage MISFET formation region, and a relatively thin thin gate oxide film 5 is formed in the MONOS memory formation region and the low voltage MISFET formation region. Is formed. Thereafter, a polysilicon film 6 as a conductor film is deposited on the entire main surface side of the silicon substrate 1 by CVD. Thereafter, the thin gate oxide film 5 and the thick gate oxide film 4 may be heat treated in a nitrogen and oxygen atmosphere to form a silicon oxynitride film. Further, the manufacturing method of the thin gate oxide film 5 and the oxide film 3 is not limited to the thermal oxidation method, and may be formed by ISSG (In-Situ Steam Generation) oxidation treatment or CVD method.

  Next, as shown in FIG. 4, a silicon oxide film is deposited on the polysilicon film 6 by the CVD method, and a photoresist 50 selectively formed on the silicon oxide film in the low voltage MISFET formation region is used as a mask. By the dry etching, the silicon oxide film in the region other than the low voltage MISFET formation region is removed, and a cap oxide film 7 made of the silicon oxide film is formed on the polysilicon film 6 in the low voltage MISFET formation region.

  Next, as shown in FIG. 5, after removing the photoresist 50 by ashing, a photoresist 51 covering the high voltage MISFET formation region and the low voltage MISFET formation region is formed, and polysilicon in the MONOS memory formation region is formed by dry etching. The film 6 and the thin gate oxide film 5 are removed. As a result, the upper surface of the p well 1a is exposed in the MONOS memory formation region.

  Next, as shown in FIG. 6, after removing the photoresist 51 by ashing, an ONO film 8 is formed on the exposed upper surfaces of the p-well 1 a, the polysilicon film 6, and the cap oxide film 7. The ONO film is formed by sequentially depositing three layers of a bottom oxide film serving as a potential barrier film, a silicon nitride film serving as a charge storage film, and a top oxide film serving as a potential barrier film by a CVD method. Each member of the bottom oxide film and the top oxide film is silicon oxide. Each of the bottom oxide film and the top oxide film is not limited to the CVD method, and may be formed by a thermal oxidation method or an ISSG oxidation treatment.

  Next, as shown in FIG. 7, after depositing a polysilicon film on the ONO film 8 by the CVD method, dry etching is performed using the selectively formed photoresist 52 as a mask, and the above-described polysilicon film and ONO are then formed. By patterning the film 8, the gate electrode 9 made of the above polysilicon film is formed on the p-well 1 a in the MONOS memory formation region via the ONO film 8.

  Next, as shown in FIG. 8, after removing the photoresist 52 by ashing, dry etching is performed using the photoresist 53 and the cap oxide film 7 formed in a part of the MONOS memory formation region and the high-voltage MISFET formation region as a mask. To do. Thereby, a part of each of the polysilicon film 6 and the thick gate oxide film 4 is removed, and the gate electrode 10 of the high voltage MISFET made of the polysilicon film 6 is thickened on the p well 1a in the high voltage MISFET formation region. A film is formed via a gate oxide film 4.

  Next, as shown in FIG. 9, after the photoresist 53 is removed by ashing, the photoresist 54 formed in a part of the MONOS memory formation region, the high-voltage MISFET formation region, and the low-voltage MISFET formation region is used as a mask. The cap oxide film 7, the polysilicon film 6, and the thin gate oxide film 5 are selectively removed by etching. Thus, a dummy gate electrode 11 made of the polysilicon film 6 is formed on the p-well 1a via the thin gate oxide film 5 in the low voltage MISFET formation region.

  Next, as shown in FIG. 10, after the photoresist 54 is removed by ashing to clean the silicon substrate 1, n-type impurities are formed on the upper surface of the p-well 1a using the gate electrodes 9, 10 and the cap oxide film 7 as a mask. The extension region 12 is formed by ion implantation of (for example, As (arsenic) or P (phosphorus)). The extension region 12 forms part of the source region or drain region of each of the MONOS memory, the high voltage MISFET, and the low voltage MISFET, and is formed to make the impurity diffusion layer have an LDD structure.

  Next, as shown in FIG. 11, after a silicon nitride film is deposited on the entire main surface side of the silicon substrate 1 by the CVD method, a part of the silicon nitride film is removed by dry etching, and the gate electrodes 9, 10 and Sidewall spacers 13 made of a silicon nitride film in contact with the side walls of the dummy gate electrode 11 are formed. As a member of the sidewall spacer 13, silicon oxide or the like may be used, or a laminated film of a silicon oxide film and a silicon nitride film may be used.

  Next, as shown in FIG. 12, n-type impurities (for example, As or P) are introduced into the upper surface of the p-well 1 a from the extension region 12 using the gate electrodes 9 and 10, the cap oxide film 7 and the sidewall spacer 13 as a mask. Source / drain regions 14 are formed on the upper surface of the p-well 1a by ion implantation at a high concentration and annealing for activating the implanted impurities. The source / drain region 14 constitutes a part of the source region or drain region of each of the MONOS memory, the high voltage MISFET, and the low voltage MISFET.

  The extension regions 12 of the MONOS memory, the high voltage MISFET, and the low voltage MISFET are formed on the surface of the p well 1a below the sidewall spacer 13 formed in each region. Further, the source / drain region 14 is a region having a junction depth deeper than that of the extension region 12, and a region having an impurity concentration higher than that of the extension region 12. The source / drain region 14 is formed on the side surface of the element isolation layer 2 from the end of the extension region 12 opposite to the gate side on the upper surface of the p well 1a in each region of the MONOS memory, the high voltage MISFET, and the low voltage MISFET. It is formed over.

  Next, as shown in FIG. 13, silicide 15 is formed on the surfaces of the gate electrodes 9 and 10 and the source / drain regions 14 by a known salicide process. As a silicidation procedure, first, a metal film is deposited on the main surface of the silicon substrate 1 by sputtering, and then the silicon substrate 1 is heat treated, and then the unreacted metal film is removed by wet etching to remove the silicide 15. Complete. As a member of the silicide 15, nickel silicide, cobalt silicide, titanium silicide, or platinum silicide may be formed. At this time, no silicide is formed on the surface of the cap oxide film 7 on the dummy gate electrode 11.

  In the present embodiment, in the step of forming the dummy gate electrode 11, a cap oxide film is formed on the dummy gate electrode 11 to prevent silicide from being formed on the dummy gate electrode 11. This enables a damascene process when removing the dummy gate electrode 11 in a later step and forming the high-k film 18 and the metal gate electrode 20.

  Next, as shown in FIG. 14, an etching stopper film (not shown) made of a thin silicon nitride film is deposited on the main surface of the silicon substrate 1 by the CVD method. Thereafter, an interlayer insulating film 16 made of a thick silicon oxide film is deposited on the main surface of the silicon substrate 1 by the CVD method so as to cover the upper portions of the gate electrodes 9, 10 and the dummy gate electrode 11, and then the interlayer is formed by CMP. The surface of the insulating film 16 is polished and planarized.

  Next, as shown in FIG. 15, using the photoresist 55 formed on the interlayer insulating film 16 so as to cover the MONOS memory formation region and the high voltage MISFET formation region as a mask, the interlayer is exposed until the surface of the dummy gate electrode 11 is exposed. The insulating film 16 and the cap oxide film 7 are etched back. Thereby, the interlayer insulating film 16 and the cap oxide film 7 in the low voltage MISFET formation region are removed. Thereby, in the low voltage MISFET formation region, the interlayer insulating film 16 is not formed on the upper portion of the dummy gate electrode 11, and the height of the upper surface thereof is substantially the same as the height of the upper surface of the dummy gate electrode 11. The gate electrode 11 is formed only on the p well 1a on the side.

  By this etch back, a step is formed on the upper surface of the interlayer insulating film 16 at the end of the low voltage MISFET formation region. That is, the height of the upper surface of the interlayer insulating film 16 in the low voltage MISFET forming region is etched back lower than the height of the upper surface of the interlayer insulating film 16 in the MONOS memory forming region and the high voltage MISFET forming region. Note that the interlayer insulating film 16 in the MONOS memory forming region and the high voltage MISFET forming region is not etched back because it is covered with the photoresist 55, and the gate electrodes 9 and 10 are still covered with the interlayer insulating film 16.

  Next, as shown in FIG. 16, after removing the photoresist 55 by ashing, the dummy gate electrode 11 made of a polysilicon film is removed by dry etching or wet etching, and then the thin gate oxide film 5 is removed.

Next, as shown in FIG. 17, the silicon substrate 1 is thermally oxidized to form a gate oxide film 17 on the upper surface of the p-well 1a exposed in the low-voltage MISFET formation region. A high-k film 18 and a metal film 19 are sequentially deposited on the inner wall and upper surface of the wall spacer 13 and on the interlayer insulating film 16. The high-k film 18 is a film having a higher dielectric constant than silicon nitride, which is one of the members used for the gate insulating film such as the thick gate oxide film 4 of the present embodiment. As such a film, a hafnium-based oxide film can be used. For example, it can be formed by depositing a substance having a high dielectric constant such as HfO 2 , HfON, or HFSiON by a CVD method or an ALD (Atomic Layer Deposition) method. The metal film 19 can be formed by depositing W, TiN or the like by sputtering.

  The reason why the gate oxide film 17 is formed again in the step of FIG. 17 after the thin gate oxide film 5 is removed in the step of FIG. 16 is that the thin film gate is formed by RIE for removing the dummy gate electrode 11 in the step of FIG. This is because the oxide film 5 receives plasma damage. Since the characteristics of the MISFET including the damaged gate insulating film are deteriorated, the characteristics of the MISFET are deteriorated by removing the damaged oxide film by, for example, wet etching and newly forming the gate oxide film 17. Can be prevented.

  Next, as shown in FIG. 18, the metal film 19 and the high-k film 18 on the interlayer insulating film 16 are formed on the interlayer insulating film 16 in each of the MONOS memory forming region, the high voltage MISFET forming region, and the low voltage MISFET forming region. The metal gate electrode 20 made of the metal film 19 is formed by polishing by CMP until the upper surface of the metal is exposed. As a result, a high-k film 18 is formed on the side and bottom surfaces of the metal gate electrode 20, and a gate oxide film 17 is formed below the high-k film 18 between the surface of the p-well 1a. The high-k film 18 and the gate oxide film 17 serve as a gate insulating film of the low voltage MISFET.

  At this time, the upper surface height of the interlayer insulating film 16 in the MONOS memory formation region and the high voltage MISFET formation region is higher than the upper surface height of the interlayer insulating film 16 in the low voltage MISFET formation region, and the high voltage MISFET formation region and the low voltage MISFET There is a step on the upper surface of the interlayer insulating film 16 at the boundary with the formation region. The polishing process by CMP here does not eliminate the level difference of the upper surface of the interlayer insulating film 16 and uniformly flatten the entire surface of the interlayer insulating film 16 on the main surface side of the silicon substrate 1. Polishing is performed until the upper surface of each interlayer insulating film 16 of the high voltage MISFET formation region and the low voltage MISFET is exposed, and the shape of the upper surface of the interlayer insulating film 16 having a difference in height is maintained. For this reason, the gate electrodes 9 and 10 and the silicide 15 thereabove are still covered with the interlayer insulating film 16.

  When the upper surface of the interlayer insulating film 16 is uniformly planarized when forming the metal gate electrode 20, the silicide 15 formed on the upper portions of the gate electrodes 9 and 10 is removed. By forming a height difference on the upper surface of the interlayer insulating film 16, the silicide 15 is prevented from being removed, and the increase in resistance at the connection portion between the contact plug and the silicide 15 formed later is suppressed.

  Since the interlayer insulating film 16 in the low-voltage MISFET formation region has a step at the end of the upper surface thereof, the polishing residue of the high-k film 18 and the metal film 19 (shown in the drawing) near the side wall of the stepped portion of the interlayer insulating film 16. May not occur).

  In the present embodiment, in order to prevent a polishing residue from occurring at the stepped portion on the upper surface of the interlayer insulating film 16, polishing is performed by replacing the CMP polishing pad with a softer one than usual. Thereby, while maintaining the shape of the upper surface of the interlayer insulating film 16 with a height difference, it is possible to prevent the occurrence of polishing residue and polish the surface of the interlayer insulating film 16 with no problem even if a small amount of polishing residue occurs, It is possible to prevent the malfunction of the circuit due to the etching residue of the metal film 19.

  Next, as shown in FIG. 19, wiring is performed by a known wiring process. That is, after further depositing an interlayer insulating film 30 on the interlayer insulating film 16 and polishing the upper surface thereof by CMP, the contacts reaching the gate electrodes 9, 10, the metal gate electrode 20 and the silicide 15 from the surface of the interlayer insulating film 30. Hole 31 is formed. Subsequently, after filling the contact hole 31 with a conductor to form a contact plug 32, a damascene wiring 33 and an interlayer insulating film 34 are formed on the interlayer insulating film 30 and the contact plug 32 by a damascene process which is a well-known technique. Thus, the semiconductor device of this embodiment is completed. Here, the contact plug 32 is composed of a barrier metal film such as titanium and titanium nitride, and a tungsten film. The damascene wiring 33 is composed of a barrier metal film such as tantalum or tantalum nitride and a conductor film containing copper as a main component.

  In the present embodiment, since the high-k film 18 and the metal gate electrode 20 are formed using the damascene process, the high-k film 18 and the metal gate electrode 20 are exposed to annealing for activating the source / drain regions. Therefore, a high-performance and highly reliable low-voltage MISFET is formed.

  Further, since conventional polysilicon gates are used in the MONOS memory formation region and the high voltage MISFET formation region, plasma damage due to RIE for removing the dummy gate electrode does not occur in the gate insulating films of the MONOS memory and the high voltage MISFET.

  In the damascene metal gate process in this embodiment, a cap oxide film is formed on the dummy gate electrode, and the silicide on the gate electrode is not removed in the cap oxide film removal process, thereby suppressing an increase in the number of processes. ing. Further, by performing CMP polishing using a pad softer than usual, the occurrence of contamination of the substrate due to the remaining etching of the metal film is prevented.

  As described above, the present embodiment can form a high-reliability MONOS memory and a high-voltage MISFET on the same semiconductor substrate simultaneously with a high-performance low-voltage MISFET while suppressing the number of steps. The cost for manufacturing the device can be reduced.

(Embodiment 2)
In the first embodiment, the manufacturing process of the semiconductor device using polysilicon for the gate electrodes of the MONOS memory and the high voltage MISFET is described. As shown in FIG. 25, the semiconductor device according to the present embodiment is configured such that the gate electrode of the MONOS memory is the metal gate electrode 20 and the top oxide film of the ONO film is the high-k film 18. Here, reference numeral 21 in FIG. 25 denotes a bottom oxide film, and 22 denotes a silicon nitride film. The bottom surface of the bottom oxide film 21 is in contact with the p-well 1a in the MONOS memory formation region, and both ends are connected to the sidewall spacers 13. It touches. The silicon nitride film 22 is formed on and in contact with the bottom oxide film 21, and the metal gate electrode 20 with the high-k film 18 formed on the lower surface and side surfaces is formed on the silicon nitride film 22.

  Hereinafter, the manufacturing method of the MONOS memory, the high voltage MISFET, and the low voltage MISFET of this embodiment will be described in the order of steps with reference to FIGS.

  First, the steps up to the step of FIG. 6 in the first embodiment are performed in the same manner as in the first embodiment. That is, the element isolation layer 2, the p well 1a, the thin gate oxide film 5, and the thick gate oxide film 4 are formed on the main surface of the silicon substrate 1. Subsequently, after depositing a polysilicon film 6 on the main surface of the silicon substrate 1 on which the thick gate oxide film 4 and the thin gate oxide film 5 are formed, cap oxidation is performed on the polysilicon film 6 in the low voltage MISFET formation region. A film 7 is selectively formed, and the polysilicon film 6 in the MONOS memory formation region is patterned and removed. Subsequently, an ONO film 8 is deposited on the p-well 1a exposed in the MONOS memory formation region, the polysilicon film 6 in the high-voltage MISFET formation region, and the cap oxide film 7 in the low-voltage MISFET formation region.

  Next, as shown in FIG. 20, a dummy gate electrode 23 having a cap oxide film 24 formed thereon is formed on the p-well 1a in the MONOS memory formation region. Here, after the step of FIG. 6 of the first embodiment, a polysilicon film and a silicon oxide film are sequentially deposited on the ONO film 8 by the CVD method, and dry etching is performed using the photoresist 56 as a mask. Thus, by selectively removing the silicon oxide film, the polysilicon film, and the ONO film 8, a dummy gate electrode 23 made of a polysilicon film and a cap oxide film 24 made of a silicon oxide film on the dummy gate electrode 23 are formed. To do.

  Next, as shown in FIG. 21, after removing the photoresist 56 by ashing, the polysilicon film 6, the cap oxide film 7, the thick gate oxide film 4 and the thin film in the high voltage MISFET formation region and the low voltage MISFET formation region. The gate oxide film 5 is patterned. As a result, in each of the high voltage MISFET formation region and the low voltage MISFET formation region, the gate electrode 10 and the dummy gate electrode 11 are formed on the p well 1a via the thick gate oxide film 4 and the thin gate oxide film 5, respectively. .

  Next, as shown in FIG. 22, n-type impurities (for example, As or P) are ion-implanted into the upper surface of the p-well 1a using the cap oxide films 7 and 24 and the gate electrode 10 as a mask, whereby the upper surface of the well 1a. The extension region 12 is formed on the substrate. Thereafter, a silicon nitride film is deposited on the entire main surface side of the silicon substrate 1 by a CVD method, and then the silicon nitride film is etched by dry etching to nitride each side wall of the gate electrode 10 and the dummy gate electrodes 11 and 23. Sidewall spacers 13 made of a silicon film are formed.

  Next, as shown in FIG. 23, an n-type impurity (for example, As or P) is applied to the upper surface of the p well 1a from the extension region 12 using the gate electrode 10, the cap oxide films 7 and 24, and the sidewall spacer 13 as a mask. Source / drain regions 14 are formed on the upper surface of the p-well 1a by ion implantation at a high concentration and annealing for activating the implanted impurities. Thereafter, silicide 15 is formed on the respective surfaces of the gate electrode 10 and the source / drain regions 14 by a known salicide process. At this time, no silicide is formed on the surfaces of the cap oxide films 7 and 24.

  In the present embodiment, silicide is formed on the dummy gate electrodes 11 and 23 by forming a cap oxide film on each of the dummy gate electrodes 11 and 23 in the step of forming the dummy gate electrodes 11 and 23. It prevents that. As a result, the dummy gate electrodes 11 and 23 are removed in a later process, thereby enabling a damascene process.

  Next, as shown in FIG. 24, a moisture prevention film (not shown) made of a thin silicon nitride film is deposited on the entire main surface side of the silicon substrate 1 by the CVD method, and then the main surface side of the silicon substrate 1. Then, an interlayer insulating film 16 made of a thick silicon oxide film is deposited on the entire surface by CVD, and then the surface of the interlayer insulating film 16 is polished and planarized by CMP. Thereafter, using the photoresist formed on the interlayer insulating film 16 so as to cover the high voltage MISFET formation region as a mask, the interlayer insulating film 16 and the cap oxide films 7 and 24 are etched until the upper surfaces of the dummy gate electrodes 11 and 23 are exposed. Back. By this etch back, a step is formed on the upper surface of the interlayer insulating film 16 at the end portions of the MONOS memory formation region and the low voltage MISFET formation region. The height of the upper surface of the insulating film 16 is lower than the height of the upper surface of the interlayer insulating film 16 in the high voltage MISFET formation region. At this time, since the interlayer insulating film 16 in the high voltage MISFET formation region is covered with the photoresist and is not etched back, the upper surface of the gate electrode 10 and the silicide 15 formed on the gate electrode 10 are covered with the interlayer insulating film 16. It remains.

  Subsequently, after removing the photoresist, the top oxide film on the upper surfaces of the dummy gate electrodes 11 and 23, the thin gate oxide film 5 and the ONO film 8 made of a polysilicon film is removed by dry etching or wet etching, and the ONO film The silicon nitride film 22 and the bottom oxide film 21 constituting 8 are left.

Subsequent steps are performed in the same manner as the low voltage MISFET formation region of the first embodiment. That is, by thermally oxidizing the silicon substrate 1, a gate oxide film 17 is formed on the upper surface of the p-well 1a exposed in the low voltage MISFET formation region, and then on the interlayer insulating film 16 and the inner wall and upper surface of the sidewall spacer 13. Then, a high-k film 18 and a metal film are deposited on the silicon nitride film 22 and the gate oxide film 17. The high-k film 18 can be formed by depositing HfO 2 , HfON, HfSiON, or the like by a CVD method or an ALD method. The metal film can be formed by depositing W, TiN or the like by sputtering.

  Here, by removing the thin gate oxide film 5 and then forming the gate oxide film 17 again, the use of the thin gate oxide film 5 damaged by RIE for removing the dummy gate electrode 11 is avoided. Degradation of the characteristics of the MISFET can be prevented.

  Further, in the step of removing the dummy gate electrode 11 and the thin gate oxide film 5, the top oxide film on the silicon nitride film 22 constituting the dummy gate electrode 23 and the ONO film 8 in the MONOS memory forming region is removed at the same time. Here, the top oxide film is removed because when the dummy gate electrode 23 on the ONO film 8 is removed by RIE, the top oxide film is damaged by the plasma, so that the damaged top oxide film is left as it is. This is because use as part of 8 leads to a decrease in device reliability. Therefore, in this embodiment, since the MONOS memory is configured by removing the top oxide film and forming the high-k film 18 on the silicon nitride film 22 instead of the top oxide film, the reliability of the device is increased. Can be secured.

  Next, as shown in FIG. 25, the metal film on the interlayer insulating film 16 and the high-k film 18 are subjected to CMP to form the interlayer insulating film 16 in each of the MONOS memory forming region, the high voltage MISFET forming region, and the low voltage MISFET forming region. The metal gate electrode 20 made of a metal film is formed in the MONOS memory formation region and the low-voltage MISFET formation region, respectively, by polishing until the upper surface is exposed. At this time, the silicide 15 formed on the upper surface of the gate electrode 10 and on the gate electrode 10 remains covered with the interlayer insulating film 16.

  Here, in the present embodiment, unlike the first embodiment, a metal gate electrode 20 is formed as a gate electrode of the MONOS memory, and a high-k film 18 is formed in contact with the bottom and side surfaces of the gate electrode 20. Yes. This enables high performance and low power consumption of the MONOS memory. Specifically, it is possible to realize a high-speed operation, a low write / erase voltage by suppressing gate depletion, and an improvement in retention (charge retention characteristics).

  At this time, polishing by CMP is performed until the upper surface of the interlayer insulating film 16 in each of the MONOS memory formation region, the high voltage MISFET formation region, and the low voltage MISFET formation region is exposed, but is formed at the end of the high voltage MISFET formation region. Do not remove any step. That is, the polishing process by CMP is finished while maintaining a height difference between the upper surface of the interlayer insulating film 16 in the high voltage MISFET formation region and the upper surface of the interlayer insulating film 16 in the MONOS memory formation region and the low voltage MISFET formation region. For this reason, the height of the upper surface of each interlayer insulating film 16 in the MONOS memory forming region and the low voltage MISFET forming region after the polishing process is lower than the height of the upper surface of the interlayer insulating film 16 in the high voltage MISFET forming region. is there.

  In the present embodiment, as in the first embodiment, in order to prevent polishing residue from occurring at the stepped portion on the upper surface of the interlayer insulating film 16, polishing is performed by changing the CMP polishing pad to a softer one than usual. Do. Thereby, while maintaining the shape of the upper surface of the interlayer insulating film 16 with a height difference, it is possible to prevent the occurrence of polishing residue and polish the surface of the interlayer insulating film 16 with no problem even if a small amount of polishing residue occurs, It is possible to prevent the malfunction of the circuit due to the etching residue of the metal film 19.

  Further, as described in the first embodiment, when the upper surface of the interlayer insulating film 16 is uniformly planarized when the metal gate electrode 20 is formed, the silicide 15 formed on the upper portion of the gate electrode 10 is formed. In this embodiment, the height difference is formed on the upper surface of the interlayer insulating film 16 to prevent the silicide 15 from being removed, and the resistance at the connection portion between the contact plug and the silicide 15 to be formed later is increased. Is suppressed.

  The height of the upper surface of the metal gate electrode 20 is polished substantially the same as the height of the upper surface of the interlayer insulating film 16 in the MONOS memory formation region. A high-k film 18 is formed on the side and bottom surfaces of the metal gate electrode 20, and a gate oxide film is formed between the lower surface of the high-k film 18 and the upper surface of the p-well 1a in the low voltage MISFET formation region. 17 is formed, and a bottom oxide film 21 and a silicon nitride film 22 formed thereon are formed in the MONOS memory formation region.

  Next, as shown in FIG. 26, an interlayer insulating film 30 is further deposited on the interlayer insulating film 16, and contacts reaching the gate electrodes 9, 10, the metal gate electrode 20, and the silicide 15 from the surface of the interlayer insulating film 30. Hole 31 is formed. Subsequently, after filling the contact hole 31 with a conductor to form a contact plug 32, a damascene wiring 33 and an interlayer insulating film 34 are formed on the interlayer insulating film 30 and the contact plug 32 by a damascene process which is a well-known technique. Thus, the semiconductor device of this embodiment is completed.

  In the semiconductor device of the present embodiment, the gate insulating films of the MONOS memory and the low voltage MISFET are prevented from being damaged by high temperature annealing or RIE, and the device characteristics are prevented from being deteriorated. Therefore, the highly reliable low voltage MISFET and It is possible to form a MONOS memory. By forming the MONOS memory and the low-voltage MISFET having the metal gate electrode 20 and the high-k film 18, the MONOS memory and the low-voltage MISFET can have high performance and low power consumption.

  Further, in the present embodiment, a cap oxide film is formed on the dummy gate electrode in the step of forming the MONOS memory and the low voltage MISFET, and a height difference is provided on the upper surface of the interlayer insulating film 16 so as to be on the gate electrode 10. The silicide 15 is protected.

  As described above, the high-reliability MONOS memory and the high-voltage MISFET can be formed on the same semiconductor substrate simultaneously with the high-performance low-voltage MISFET, so that the cost for manufacturing the semiconductor device can be reduced.

(Embodiment 3)
In the second embodiment, the manufacturing process of the semiconductor device using the gate electrode in the low voltage MISFET formation region and the MONOS memory formation region as a metal gate and using a high-k film as the gate insulating film has been described. In the present embodiment, as shown in FIG. 27, a semiconductor device having a metal gate electrode 20 and a high-k film 18 at all gates in the low voltage MISFET formation region, the MONOS memory formation region, and the high voltage MISFET formation region. The process will be described.

  A method for manufacturing the MONOS memory, the high voltage MISFET, and the low voltage MISFET according to the present embodiment will be described below in the order of steps with reference to FIGS.

  In order to complete the semiconductor device according to the present embodiment, the cap oxide film on the polysilicon film 6 is used not only in the low voltage MISFET formation region but also in the high voltage MISFET formation region in the step of FIG. 4 in the first embodiment. The subsequent steps may be performed in substantially the same manner as in the second embodiment.

  That is, first, the steps up to the step of FIG. 3 in the first embodiment are performed in the same manner as in the first embodiment. A p-well 1a and an element isolation layer 2 are formed, and a polysilicon film is formed on the entire main surface of the silicon substrate 1 on which a thick gate oxide film 4 and a thin gate oxide film 5 are formed by a well-known two-type gate oxidation process. A silicon film 6 is deposited. Thereafter, as shown in FIG. 28, a cap oxide film 7 is deposited on the polysilicon film 6 by the CVD method, and the cap oxide film 7 in the MONOS memory forming region is removed by dry etching using a photoresist as a mask. The cap oxide film 7 is selectively left in the voltage MISFET formation region and the low voltage MISFET formation region. Further, the polysilicon film 6 in the MONOS memory formation region is selectively removed by dry etching.

  Next, as shown in FIG. 29, as in the second embodiment, a dummy gate electrode 23 having a cap oxide film 24 formed thereon is formed by sequentially depositing a bottom oxide film, a silicon nitride film, and a top oxide film. The MONOS memory formation region is formed through the ONO film 8. Thereafter, the cap oxide film 7, the polysilicon film 6 and the gate oxide film are patterned, and the dummy gate electrode 11 having the cap oxide film 7 thereon is formed in each of the high voltage MISFET formation region and the low voltage MISFET formation region.

  Next, as shown in FIG. 30, after the extension region 12 is formed on the upper surface of the p-well 1a by ion implantation, as in the second embodiment, the sidewall spacer 13 in contact with the sidewall of each gate is formed. Subsequently, source / drain regions 14 are formed on the upper surface of the p-well 1a by ion implantation. Thereafter, silicide 15 is formed on each surface of the source / drain region 14 by a known salicide process. At this time, no silicide is formed on the surfaces of the cap oxide films 7 and 24.

  Next, as shown in FIG. 31, a moisture prevention film (not shown) made of a thin silicon nitride film is deposited on the entire main surface of the silicon substrate 1 by the CVD method. Thereafter, an interlayer insulating film 16 made of a thick silicon oxide film is deposited on the entire main surface of the silicon substrate 1 so as to cover the dummy gate electrodes 11 and 23 by CVD, and then the surface of the interlayer insulating film 16 is formed by CMP. Polish and flatten. Thereafter, the upper surface of the interlayer insulating film 16 and the cap oxide films 7 and 24 are etched back until the upper surfaces of the dummy gate electrodes 11 and 23 are exposed. Subsequently, the dummy gate electrodes 11 and 23 made of a polysilicon film, the thin gate oxide film 5 and the top oxide film on the upper surface of the ONO film 8 in the MONOS memory formation region are removed by dry etching or wet etching to form the ONO film 8. The previously formed silicon nitride film 22 and bottom oxide film 21 are left on the p-well 1a.

  The high-voltage MISFET is formed by almost the same process as the low-voltage MISFET. However, when the thin gate oxide film 5 is removed after the dummy gate electrode removal process, the thick gate oxide film 4 is completely removed. Instead, only a part of the upper surface is removed.

Next, as shown in FIG. 27, the subsequent steps are performed in the same manner as the low voltage MISFET formation region of the first embodiment. That is, by thermally oxidizing the silicon substrate 1, a gate oxide film 17 is formed on the upper surface of the p-well 1a exposed in the low voltage MISFET formation region, and then on the interlayer insulating film 16 and the inner wall and upper surface of the sidewall spacer 13. Then, a high-k film 18 and a metal film are sequentially deposited on the gate insulating film 17, the thick gate oxide film 4 and the silicon nitride film 22. The high-k film 18 can be formed by depositing a substance having a high dielectric constant such as HfO 2 , HfON, or HfSiON by a CVD method or an ALD method. The metal film can be formed by depositing W, TiN or the like by sputtering.

  Thereafter, the metal film and the high-k film 18 deposited on the interlayer insulating film 16 are polished by CMP until the upper surface of the interlayer insulating film 16 is exposed. As a result, the metal gate electrode 20 made of a metal film whose upper surface height is substantially the same as the upper surface height of the interlayer insulating film 16 is formed in each of the MONOS memory formation region, the high voltage MISFET formation region, and the low voltage MISFET formation region.

  Here, similarly to the low voltage MISFET in the first embodiment, the high-k film 18 is formed on the side surface and the bottom surface of the metal gate electrode 20 of each of the MONOS memory, the high voltage MISFET, and the low voltage MISFET of the present embodiment. Is formed. Further, a thick gate oxide film 4 is formed between the lower surface of the high-k film 18 of the high voltage MISFET and the upper surface of the p-well 1a, and the high-k film 18 and the thick gate oxide film 4 are formed. It works as a gate insulating film of high voltage MISFET.

  Next, as shown in FIG. 32, an interlayer insulating film 30 is further deposited on the interlayer insulating film 16, and contacts reaching the gate electrodes 9, 10, the metal gate electrode 20, and the silicide 15 from the surface of the interlayer insulating film 30. Hole 31 is formed. Subsequently, after filling the contact hole 31 with a conductor to form a contact plug 32, a damascene wiring 33 and an interlayer insulating film 34 are formed on the interlayer insulating film 30 and the contact plug 32 by a damascene process which is a well-known technique. Thus, the semiconductor device of this embodiment is completed.

  In the semiconductor device of the present embodiment, like the MONOS memory and the low voltage MISFET in the second embodiment, all the gate electrodes of the MONOS memory, the high voltage MISFET, and the low voltage MISFET are metal gate electrodes in the same process. There is no need to form silicide on the gate electrode. Therefore, according to the semiconductor device of the present embodiment, in addition to the same effects as those of the second embodiment, there is no need for a difference in height of the upper surface of the interlayer insulating film 16, and the upper surface of the interlayer insulating film 16 is polished by CMP. In this case, since it is not necessary to use a soft pad for polishing, there is an advantage that flattening is easy. In addition, since there is no step on the surface of the interlayer insulating film 16, it is possible to prevent the occurrence of polishing residue and to easily form the subsequent wiring.

  Since the thick gate oxide film 4 remains without being removed in the high voltage MISFET formation region, the thick gate oxide film 4 causes plasma damage due to RIE when the dummy gate electrode 11 in the high voltage MISFET formation region is removed. I'm still receiving it.

(Embodiment 4)
In the first and second embodiments, a step is formed on the upper surface of the interlayer insulating film in the step of mounting a MISFET having a polysilicon gate on a semiconductor substrate and a MISFET having a metal gate formed by a damascene process. It was. In the present embodiment, a manufacturing process of a semiconductor device in which a MONOS memory and a high voltage MISFET having a polysilicon gate on a semiconductor substrate and a low voltage MISFET having a metal gate are mixedly mounted and a step is not formed in an interlayer insulating film will be described. To do.

  Hereinafter, a method of manufacturing the MONOS memory, the high voltage MISFET, and the low voltage MISFET according to the present embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 33, the silicon substrate 1 on which the element isolation layer 2 is formed is thermally oxidized in the same process as in the first embodiment to form an oxide film on the main surface of the silicon substrate 1, and then silicon A p-type impurity (for example, B or BF 2 ) is ion-implanted into the main surface of the substrate 1 to form a p-well 1a in the main surface of the silicon substrate 1, and the oxide film is removed. Thereafter, a thick gate oxide film 4 and a thin gate oxide film 5 are formed on the upper surface of the p well 1a by a well-known two-type gate oxidation process, and on the main surface of the silicon substrate 1 on which these gate oxide films are formed. A polysilicon film 6, a silicon oxide film 25, a polysilicon film 26, and a cap oxide film 7 are sequentially deposited by the CVD method.

  Next, as shown in FIG. 34, the cap oxide film 7, the polysilicon film 26, and the silicon oxide film 25 in regions other than the low voltage MISFET formation region are removed by dry etching using a patterned photoresist as a mask, and the MONOS is removed. After exposing the upper surface of the polysilicon film 6 in the memory formation region and the high voltage MISFET formation region, the photoresist is removed.

  Next, as shown in FIG. 35, the polysilicon film 6 and the thin gate oxide film 5 in the MONOS memory formation region are removed by dry etching using a photoresist as a mask, and the upper surface of the p well 1a is exposed. Thereafter, the photoresist is removed, and a bottom oxide film and a silicon nitride film are formed on the exposed p-well 1a in the MONOS memory formation region, the polysilicon film 6 in the high voltage MISFET formation region, and the cap oxide film 7 in the low voltage MISFET formation region. And the ONO film 8 consisting of three layers of the top oxide film is deposited by the CVD method.

  Next, as shown in FIG. 36, a polysilicon film is deposited on the ONO film 8 by the CVD method. Thereafter, dry etching is performed using the photoresist as a mask, and the polysilicon film and the ONO film 8 are patterned. Thus, after the gate electrode 9 made of a polysilicon film is formed on the ONO film 8 on the p well 1a in the MONOS memory formation region, the photoresist is removed.

  Next, as shown in FIG. 37, a photoresist is formed in the gate electrode formation region of the MONOS memory formation region and the high voltage MISFET formation region. Thereafter, a part of the polysilicon film 6 and the thick gate oxide film 4 in the high voltage MISFET formation region is selectively removed by dry etching using the photoresist and the cap oxide film 7 as a mask, and the thickness on the p well 1a is selectively removed. A gate electrode 10 made of a polysilicon film 6 is formed on the film gate oxide film 4. Thereafter, the photoresist is removed by ashing.

  Next, as shown in FIG. 38, the MONOS memory formation region and the high voltage MISFET formation region are covered with a photoresist, and the gate electrode formation region of the low voltage MISFET formation region is covered with a photoresist. Thereafter, the cap oxide film 7, the polysilicon film 26, the silicon oxide film 25, the polysilicon film 6 and a part of the thin gate oxide film 5 are selectively removed by dry etching using a photoresist as a mask. As a result, a dummy gate electrode 11 comprising the polysilicon film 26, the silicon oxide film 25, the polysilicon film 6 and the thin gate oxide film 5 and having the cap oxide film 7 formed thereon is formed. Thereafter, the photoresist is removed.

  Next, as shown in FIG. 39, the extension region 12 is formed by ion-implanting n-type impurities (for example, As or P) into the upper surface of the p-well 1a using the gate electrodes 9, 10 and the cap oxide film 7 as a mask. Form. Thereafter, after a silicon nitride film is deposited on the entire main surface side of the silicon substrate 1 by the CVD method, the silicon nitride film is etched by dry etching, and a silicon nitride film is formed on the side walls of the gate electrodes 9, 10 and the dummy gate electrode 11. A side wall spacer 13 is formed.

  Next, as shown in FIG. 40, n-type impurities (for example, As or P) are applied to the upper surface of p well 1a from the extension region using gate electrodes 9, 10, cap oxide film 7 and sidewall spacer 13 as a mask. Ion implantation at high concentration. Thereafter, annealing for activating the implanted impurities is performed to form source / drain regions 14 on the upper surfaces of the p wells 1a in the MONOS memory formation region, the high voltage MISFET formation region, and the low voltage MISFET formation region. . Subsequently, silicide 15 is formed on the surfaces of the gate electrodes 9 and 10 and the source / drain regions 14 by a known salicide process. At this time, no silicide is formed on the surface of the cap oxide film 7.

  Next, as shown in FIG. 41, an interlayer insulating film 16 made of silicon oxide is formed on the entire main surface side of the silicon substrate 1 by CVD so as to cover each of the gate electrodes 9, 10 and the dummy gate electrode 11. accumulate. Thereafter, the surface of the interlayer insulating film 16 and the cap oxide film 7 are polished and planarized by CMP until the upper surface of the polysilicon film 26 that is a part of the dummy gate electrode 11 is exposed. Thereafter, the dummy gate electrode 11 and the thin gate oxide film 5 made of the polysilicon film 26, the silicon oxide film 25 and the polysilicon film 6 are removed by dry etching or wet etching.

Next, as shown in FIG. 42, the silicon substrate 1 is thermally oxidized to form a gate oxide film 17 on the upper surface of the p-well 1a exposed in the low voltage MISFET formation region, and then on the interlayer insulating film 16 and the gate. A high-k film 18 and a metal film are sequentially deposited on the oxide film 17 and on the inner wall and upper surface of the sidewall spacer 13 by the CVD method. The high-k film 18 can be formed by depositing a material having a high dielectric constant such as HfO 2 , HfON, or HfSiON by a CVD method or an ALD method. The metal film can be formed by depositing W, TiN or the like by sputtering. Thereafter, the metal film and the high-k film 18 are polished by CMP until the upper surface of the interlayer insulating film 16 is exposed, whereby the metal gate electrode 20 made of the metal film is formed in the low-voltage MISFET formation region.

  Next, as shown in FIG. 43, wiring is performed by a known wiring process. That is, an interlayer insulating film 30 is further deposited on the interlayer insulating film 16, and contact holes 31 reaching the gate electrodes 9, 10, the metal gate electrode 20, and the silicide 15 from the surface of the interlayer insulating film 30 are formed. Thereafter, a contact plug 32 is formed by filling the contact hole 31 with a conductor such as W, and then a damascene wiring 33 and an interlayer insulating film 34 are formed on the interlayer insulating film 30 and the contact plug 32 by a damascene process. Thereby, the semiconductor device of the present embodiment is completed.

  In the semiconductor device of the present embodiment, as in the first embodiment, the high-k film 18 and the metal gate electrode 20 are formed using the damascene process, so that the high-k film 18 and the metal gate electrode 20 are the source. -It is not exposed to annealing for drain region activation. Further, the thin film gate oxide film 5 damaged by the plasma is removed, and the gate oxide film 17 is formed, so that the low voltage MISFET having high performance and high reliability is left without causing plasma damage to the low voltage MISFET of the completed semiconductor device. It is possible to form.

  Further, in the semiconductor device of the present embodiment, unlike the first embodiment, no step is formed on the upper surface of the interlayer insulating film 16. Therefore, when polishing the upper surface of the interlayer insulating film 16 by CMP, it is not necessary to use a soft pad for polishing, flattening is facilitated, and the metal gate electrode 20 can be formed easily and accurately. Further, since there is no step on the upper surface of the interlayer insulating film 16, later wiring can be easily formed.

  Unlike the third embodiment, in this embodiment, no dummy gate electrode is formed in the MONOS memory formation region and the high voltage MISFET formation region, and the dummy gate electrode is not formed in the MONOS memory formation region and the high voltage MISFET formation region. There is no RIE process for removing. For this reason, the gate insulating film damaged by plasma does not remain in the MONOS memory and the high voltage MISFET of the present embodiment.

  In the damascene metal gate process in the present embodiment, the cap oxide film 7 is formed on the dummy gate electrode 11 to prevent silicide from being formed on the dummy gate electrode 11 and to suppress the increase in the number of processes. It is possible.

  As a result, it is possible to form a high-reliability MONOS memory and a high-voltage MISFET on the same semiconductor substrate simultaneously with a high-performance and high-reliability low-voltage MISFET while suppressing the number of processes. Costs for manufacturing can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is widely used in semiconductor devices in which a MONOS type nonvolatile memory is formed on a semiconductor substrate.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1a p well 2 Element isolation layer 3 Oxide film 4 Thick film gate oxide film 5 Thin film gate oxide film 6, 26 Polysilicon film 7, 24 Cap oxide film 8 ONO film 9, 10 Gate electrode 11, 23 Dummy gate electrode DESCRIPTION OF SYMBOLS 12 Extension area | region 13 Side wall spacer 14 Source / drain area | region 15 Silicide 16, 30, 34 Interlayer insulation film 17 Gate oxide film 18 high-k film 19 Metal film 20 Metal gate electrode 21 Bottom oxide film 22 Silicon nitride film 25 Silicon oxide film 31 Contact hole 32 Contact plug 33 Damascene wiring 50-56 Photoresist

Claims (11)

  1. A non-volatile memory formed in the first region of the main surface of the semiconductor substrate; a first MISFET formed in the second region of the main surface of the semiconductor substrate; and a third region of the main surface of the semiconductor substrate; And a method of manufacturing a semiconductor device having a second MISFET that operates at a lower voltage than the first MISFET,
    (A) forming a first gate electrode on a main surface of the semiconductor substrate in the first region via a first gate insulating film including a potential barrier film and a charge retention film formed on the potential barrier film; Forming a first source region and a first drain region on a main surface of the semiconductor substrate in the first region;
    (B) forming a second gate electrode on a main surface of the semiconductor substrate in the second region via a second gate insulating film, and forming a second source region and a second gate electrode on the main surface of the semiconductor substrate in the second region; Forming two drain regions;
    (C) forming a dummy gate electrode having a first cap film on the main surface of the semiconductor substrate in the third region via a third gate insulating film, and forming a main gate electrode of the semiconductor substrate in the third region; Forming a third source region and a third drain region on the surface;
    (D) After the steps (a), (b), and (c), on the main surface of the semiconductor substrate in the respective formation regions of the nonvolatile memory, the first MISFET, and the second MISFET, the first, Forming an interlayer insulating film so as to cover the second gate electrode and the dummy gate electrode;
    (E) After the step (d), etching back the upper surface of the interlayer insulating film and the first cap film in the third region until the upper surface of the dummy gate electrode is exposed;
    (F) After the step (e), removing the dummy gate electrode and the third gate insulating film ;
    (G) After the step (f), a fourth gate insulating film, a high dielectric constant film having a higher dielectric constant than the second gate insulating film and the fourth gate insulating film on the main surface of the semiconductor substrate ; Sequentially depositing a metal electrode material layer on the high dielectric constant film;
    (H) After the step (g), the high dielectric constant film and the metal electrode material layer are polished until an upper surface of the interlayer insulating film formed in the third region is exposed, and the third region is Forming a first metal gate electrode including a metal electrode material layer;
    Have
    In the etch back in the step (e) and the polishing in the step (h), the upper surfaces of the first and second gate electrodes are not exposed from the interlayer insulating film, and the upper surface of the interlayer insulating film in the third region is not exposed. A method of manufacturing a semiconductor device, wherein the height is formed lower than the height of the upper surface of the interlayer insulating film in the second region.
  2. In the step (a), the first gate insulating film in which the potential barrier film, the charge holding film, and the top insulating film are stacked in order is formed, and the second gate film is provided on the first gate electrode. Form the
    In the step (e), the upper surface of the interlayer insulating film and the second cap film in the first region are etched back until the upper surface of the first gate electrode is exposed,
    In the step (f), the first gate electrode and the top insulating film are removed,
    In the step (h), the high dielectric constant film and the metal electrode material layer are polished until the upper surface of the interlayer insulating film formed in the first region is exposed, and the metal electrode material layer is formed in the first region. Forming a second metal gate electrode containing
    In the etch back in the step (e) and the polishing in the step (h), the upper surface of the second gate electrode is not exposed from the interlayer insulating film, and the height of the upper surface of the interlayer insulating film in the first region is increased. the method of manufacturing a semiconductor device according to claim 1, characterized in that the formed lower than the height of the upper surface of the interlayer insulating film in the forming region of the first MIS F ET.
  3. Wherein prior to said even after the step (f) (g) step, removing the third gate insulating film, the fourth gate insulating film on the main surface of said semiconductor substrate exposed in said third region The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed.
  4.   After the steps (a), (b) and (c) and before the step (d), the first gate electrode, the first, second and third source regions, the first, second and 2. The semiconductor device according to claim 1, wherein silicide is formed on an upper surface of the third drain region, and silicide is formed on the upper surface of the second gate electrode or on the upper surfaces of the first and second gate electrodes. Production method.
  5. A non-volatile memory formed in the first region of the main surface of the semiconductor substrate; a first MISFET formed in the second region of the main surface of the semiconductor substrate; and a third region of the main surface of the semiconductor substrate; And a method of manufacturing a semiconductor device having a second MISFET that operates at a lower voltage than the first MISFET,
    (A) First dummy gate insulation including a potential barrier film , a charge holding film, and a top insulating film in which a first gate electrode having a first cap film on the top is sequentially laminated on the main surface of the semiconductor substrate in the first region. Forming a first source region and a first drain region on a main surface of the semiconductor substrate in the first region;
    (B) forming a second dummy gate electrode having a second cap film on the main surface of the semiconductor substrate in the second region with a second gate insulating film interposed therebetween, and the semiconductor substrate in the second region; Forming a second source region and a second drain region on the main surface of
    (C) forming a third dummy gate electrode having a third cap film on the main surface of the semiconductor substrate in the third region with a third gate insulating film interposed therebetween, and the semiconductor substrate in the third region; Forming a third source region and a third drain region on the main surface of
    (D) After the steps (a), (b), and (c), on the main surface of the semiconductor substrate in the respective formation regions of the nonvolatile memory, the first MISFET, and the second MISFET, the first, Forming an interlayer insulating film so as to cover the second and third dummy gate electrodes;
    (E) After the step (d), the upper surface of the interlayer insulating film, the first, second, and third cap films are exposed until the upper surfaces of the first, second, and third dummy gate electrodes are exposed. Etch back, and
    (F) After the step (e), removing the first, second and third dummy gate electrodes , the top insulating film and the third gate insulating film ;
    (G) After the step (f), a fourth gate insulating film, a high dielectric constant film having a higher dielectric constant than the second gate insulating film and the fourth gate insulating film on the main surface of the semiconductor substrate ; Sequentially depositing a metal electrode material layer on the high dielectric constant film;
    (H) After the step (g), the high dielectric constant film and the metal electrode material layer are polished until the upper surface of the interlayer insulating film is exposed, and each of the nonvolatile memory, the first and third regions is polished. Forming a first, second and third metal gate electrode including the metal electrode material layer.
  6. Wherein prior to said even after the step (f) (g) step, removing the third gate insulating film, the fourth gate insulating film on the main surface of said semiconductor substrate exposed in said third region 6. The method of manufacturing a semiconductor device according to claim 5 , wherein the semiconductor device is formed.
  7. After the steps (a), (b) and (c) and before the step (d), the first gate electrode, the first, second and third source regions, the first, second and 6. The method of manufacturing a semiconductor device according to claim 5 , wherein silicide is formed on an upper surface of the third drain region.
  8. A non-volatile memory formed in the first region of the main surface of the semiconductor substrate; a first MISFET formed in the second region of the main surface of the semiconductor substrate; and a third region of the main surface of the semiconductor substrate; And a method of manufacturing a semiconductor device having a second MISFET that operates at a lower voltage than the first MISFET,
    (A) forming a first gate electrode on a main surface of the semiconductor substrate in the first region via a first gate insulating film including a potential barrier film and a charge retention film formed on the potential barrier film; Forming a first source region and a first drain region on a main surface of the semiconductor substrate in the first region;
    (B) forming a second gate electrode on a main surface of the semiconductor substrate in the second region via a second gate insulating film, and forming a second source region and a second gate electrode on the main surface of the semiconductor substrate in the second region; Forming two drain regions;
    (C) forming a dummy gate electrode having an upper cap film and including at least two conductive films on a main surface of the semiconductor substrate in the third region via a third gate insulating film; Forming a third source region and a third drain region on the main surface of the three regions of the semiconductor substrate;
    (D) After the steps (a), (b), and (c), on the main surface of the semiconductor substrate in the respective formation regions of the nonvolatile memory, the first MISFET, and the second MISFET, the first, Forming an interlayer insulating film so as to cover the second MISFET and the dummy gate electrode;
    (E) after the step (d), polishing the upper surface of the interlayer insulating film and the cap film until the upper surface of the dummy gate electrode is exposed;
    (F) After the step (e), removing the dummy gate electrode and the third gate insulating film ;
    (G) After the step (f), a fourth gate insulating film, a high dielectric constant film having a higher dielectric constant than the second gate insulating film and the fourth gate insulating film on the main surface of the semiconductor substrate ; Sequentially depositing a metal electrode material layer on the high dielectric constant film;
    (H) After the step (g), the high dielectric constant film and the metal electrode material layer are polished until the upper surface of the interlayer insulating film is exposed, and the metal gate including the metal electrode material layer in the third region Forming an electrode;
    A method for manufacturing a semiconductor device, comprising:
  9. Wherein prior to said even after the step (f) (g) step, removing the third gate insulating film, the fourth gate insulating film on the main surface of said semiconductor substrate exposed in said third region The method of manufacturing a semiconductor device according to claim 8 , wherein the semiconductor device is formed.
  10. After the steps (a), (b) and (c) and before the step (d), the first and second gate electrodes, the first, second and third source regions, the first 9. The method of manufacturing a semiconductor device according to claim 8 , wherein silicide is formed on the upper surface of each of the second and third drain regions.
  11. In the step (c), a silicon oxide film is formed between the two conductive films, and in the step (f), the dummy gate electrode composed of the two conductive films and the silicon oxide film is removed. The method for manufacturing a semiconductor device according to claim 8 .
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