KR100447982B1 - Method for forming metal interconnection of semiconductor device using buffer layer - Google Patents
Method for forming metal interconnection of semiconductor device using buffer layer Download PDFInfo
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- KR100447982B1 KR100447982B1 KR1019960072790A KR19960072790A KR100447982B1 KR 100447982 B1 KR100447982 B1 KR 100447982B1 KR 1019960072790 A KR1019960072790 A KR 1019960072790A KR 19960072790 A KR19960072790 A KR 19960072790A KR 100447982 B1 KR100447982 B1 KR 100447982B1
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- forming
- interlayer insulating
- film
- metal wiring
- via hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 보다 구체적으로는, 비아홀의 오정렬시 브리지 현상을 방지할 수 있는 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a method for forming metal wirings in a semiconductor device capable of preventing a bridge phenomenon during misalignment of via holes.
일반적으로 다층 금속 배선은, 반도체 소자의 칩 면적을 개선하기 위하여 형성된다.Generally, multilayer metal wiring is formed in order to improve the chip area of a semiconductor element.
이러한 종래의 다층 금속 배선의 형성방법은 도 1에 도시된 바와 같이, 집적회로가 구비된 반도체 기판(1) 상부에 제 1 층간 절연막(2)이 형성되고, 제 1 층간 절연막(2)은 소정 부분이 노출되도록 식각되어, 콘택홀(도시되지 않음)이 형성된다. 이어서, 노출된 반도체 기판(1)과 콘택되도록 제 1 금속막 및 난반사 방지막(4)이 적층된다음, 소정 부분 패터닝하여 제 1 금속 배선(3)이 형성된다. 그후, 제 2 층간 절연막이 증착된다음, 제 1 금속 배선(4)이 소정 부분 노출되도록 식각되어, 비아홀이 형성된다. 그후, 노출된 제 1 금속 배선(4)과 콘택되도록 제 2 금속 배선(6)이 공지의 방식에 의하여 형성된다. 여기서, 미설명 부호 7은 제 2 금속 배선(6) 상부에 형성된 난 반사 방지막이다.In the conventional method of forming a multilayer metal wiring, as shown in FIG. 1, a first interlayer insulating film 2 is formed on a semiconductor substrate 1 having an integrated circuit, and the first interlayer insulating film 2 is formed in a predetermined manner. The portions are etched to expose, forming contact holes (not shown). Subsequently, the first metal film and the diffuse reflection prevention film 4 are laminated so as to be in contact with the exposed semiconductor substrate 1, and then the first metal wiring 3 is formed by predetermined patterning. Thereafter, the second interlayer insulating film is deposited, and then the first metal wiring 4 is etched to expose a predetermined portion to form a via hole. Thereafter, the second metal wiring 6 is formed in a known manner so as to contact the exposed first metal wiring 4. Here, reference numeral 7 denotes an egg reflection prevention film formed on the second metal wiring 6.
그러나, 상기와 같은, 종래의 방법에 의하면, 비아홀 형성시, 제 1 금속 배선 폭 및 비아홀의 직경이 미세하여, 오정렬이 발생하기쉽다.However, according to the conventional method as described above, when the via hole is formed, the first metal wiring width and the diameter of the via hole are minute, and misalignment is likely to occur.
이로 인하여, 반도체 기판 상에 형성된 도전체(도시되지 않음)들과 브리지(bridge) 현상이 발생되었다.As a result, conductors (not shown) formed on the semiconductor substrate and a bridge phenomenon have occurred.
또한, 초 미세화된 반도체 소자에 있어서, 비아홀의 크기가 매우 작아, 그내에 제 2 금속 배선을 형성하기 어려운 문제점이 발생되었다.In addition, in the ultra miniaturized semiconductor device, the size of the via hole is very small, which makes it difficult to form the second metal wiring therein.
따라서, 본 발명은, 반도체 소자의 비아홀 형성시, 오정렬이 발생되어도, 브리지 현상이 발생되지 않도록 하는 한편, 비아홀내에 제 2 금속 배선을 효과적으로 형성할 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention provides a method for forming a metal wiring of a semiconductor device capable of effectively forming a second metal wiring in a via hole while preventing a bridge phenomenon from occurring even when misalignment occurs in forming a via hole of a semiconductor device. The purpose.
도 1은 종래의 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device.
도 2A 내지 2C는 본 발명의 반도체 소자의 금속 배선 형성방법을 설명하기 위한 각 제조 공정별 단면도.2A to 2C are cross-sectional views of respective manufacturing processes for explaining a method for forming metal wirings of a semiconductor device of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11: 반도체 기판 12: 제 1 층간 절연막11: semiconductor substrate 12: first interlayer insulating film
13: 완충막 14 : 제 1 금속막13: buffer film 14: first metal film
15,18:난 반사 방지막 16: 제 2 층간 절연막15,18: Anti-reflection film 16: Second interlayer insulating film
17: 제 2 금속막17: second metal film
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 집적회로가 구비된 반도체 기판 상부에 제 1 층간 절연막을 형성하는 단계; 상기 제 1 층간 절연막 상부에 소정 부분 패터닝된 오정렬 방지용 완충막을 형성하는 단계; 상기 반도체 기판의 소정 부분이 노출되도록 완충막 및 제 1 층간 절연막을 소정 부분 식각하여, 콘택홀을 형성하는 단계; 상기 노출된 반도체 기판 및 완충막과 소정 부분 콘택되도록 콘택홀내에 제 1 금속 배선을 형성하는 단계; 상기 제 1 금속 배선이 형성된 반도체 기판 상부에 제 2 층간 절연막을 형성하는 단계; 상기 제 2 층간 절연막을 소정 부분 식각하여, 비아홀을 형성하는 단계; 및 제 1 금속 배선과 콘택되도록 제 2 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention comprises the steps of: forming a first interlayer insulating film on a semiconductor substrate provided with an integrated circuit; Forming a buffer layer for preventing misalignment, wherein the predetermined portion is patterned on the first interlayer insulating layer; Etching a predetermined portion of the buffer layer and the first interlayer insulating layer to expose a predetermined portion of the semiconductor substrate to form a contact hole; Forming a first metal wire in the contact hole so as to be in partial contact with the exposed semiconductor substrate and the buffer film; Forming a second interlayer insulating layer on the semiconductor substrate on which the first metal wiring is formed; Etching a portion of the second interlayer insulating layer to form a via hole; And forming a second metal wire to be in contact with the first metal wire.
본 발명에 의하면, 제 1 금속 배선의 일측에 소정 길이를 갖는 완충막을 형성하여, 오정렬이 발생되어도, 하부 배선에 영향을 미치지 않게 하여, 브리지 현상을 방지한다. 또한, 완충막을 형성하므로서, 비아홀의 폭을 소정 부분 연장하여 형성할 수 있어, 비아홀내에 제 2 금속 배선을 효과적으로 형성할 수 있다.According to the present invention, a buffer film having a predetermined length is formed on one side of the first metal wiring to prevent the bridge phenomenon from affecting the lower wiring even when misalignment occurs. In addition, by forming the buffer film, the width of the via hole can be extended by a predetermined portion, so that the second metal wiring can be effectively formed in the via hole.
[실시예]EXAMPLE
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2A 내지 2C는 본 발명의 반도체 소자의 금속 배선 형성방법을 설명하기 위한 각 제조 공정별 단면도이다.2A to 2C are cross-sectional views of respective manufacturing processes for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
먼저, 도 2A를 참조하여, 집적 회로 예를들어, 디램 소자가 형성된 반도체기판(11) 상부에 층간 절연막(12) 예를들어, BPSG막과 같은 층간 평탄화막을 포함하는 막이 소정 두께로 증착된다. 이어서, 층간 절연막(12) 상부에 완충막(13)이 형성된다. 이 완충막(13)은 불순물이 도핑되지 않은 폴리실리콘막으로 형성함이 바람직하고, 소정 부분 패터닝된다.First, referring to FIG. 2A, a film including an interlayer insulating film 12, for example, an interlayer planarization film such as a BPSG film, is deposited to a predetermined thickness on an integrated circuit, for example, on a semiconductor substrate 11 on which a DRAM element is formed. Subsequently, a buffer film 13 is formed on the interlayer insulating film 12. The buffer film 13 is preferably formed of a polysilicon film which is not doped with impurities, and is patterned at a predetermined portion.
이어서, 도 2B에 도시된 바와 같이, 패터닝된 완충막(13)과 층간 절연막(12)은 소정 부분 식각되어, 콘택홀(도시되지 않음)이 형성된다. 그후, 제 1 금속막(14)과 난반사 방지막(15)을 순차적으로 형성한다음, 소정 부분 식각하여, 제 1 금속 배선을 형성한다. 이때, 제 1 금속 배선은 완충막의 소정 부분 상에 형성되고, 제 1 금속 배선이 상부에 형성되지 않은 부분의 길이(L)은 약 1.5 내지 2.5㎛가 되도록 한다.Subsequently, as shown in FIG. 2B, the patterned buffer film 13 and the interlayer insulating film 12 are partially etched to form contact holes (not shown). Thereafter, the first metal film 14 and the diffuse reflection prevention film 15 are sequentially formed, and then a predetermined partial etching is performed to form the first metal wiring. At this time, the first metal wiring is formed on a predetermined portion of the buffer film, and the length L of the portion where the first metal wiring is not formed on the upper portion is about 1.5 to 2.5 μm.
그리고 나서, 도 2C에 도시된 바와 같이, 결과물 상부에 제 2 층간 절연막(16)을 형성한다음, 제 1 금속 배선이 노출되도록 소정 부분 식각하여, 비아홀(도시되지 않음)이 형성된다. 그후, 제 2 금속막(17) 및 난반사 방지막(18)을 순차적으로 형성한다음, 소정 부분 패터닝하여, 제 2 금속 배선이 형성된다.Then, as shown in FIG. 2C, a second interlayer insulating film 16 is formed on the resultant, and then a predetermined portion is etched to expose the first metal wiring, so that a via hole (not shown) is formed. Thereafter, the second metal film 17 and the diffuse reflection prevention film 18 are sequentially formed, and then predetermined portions are patterned to form second metal wirings.
이때, 상기 비아홀은 약간의 오정렬이 발생하여도, 제 1 금속 배선의 일측에 구비된 완충막이 형성되어 있어, 하부에 형성된 배선(도시되지 않음)들과 브리지 현상이 발생되지 않는다.In this case, even if a slight misalignment occurs in the via hole, a buffer film provided on one side of the first metal wire is formed, so that the wires (not shown) formed below and the bridge phenomenon do not occur.
또한, 제 1 금속 배선의 일측에 완충막이 구비되어, 상기 비아홀의 폭을 종래에 비하여, 보다 넓은 폭을 갖도록 형성할 수 있으며, 이로써, 제 2 금속 배선을 효과적으로 형성하게 된다.In addition, a buffer film is provided on one side of the first metal wire, so that the width of the via hole can be formed to have a wider width than in the related art, thereby effectively forming the second metal wire.
이상에서 자세히 설명되어진 바와 같이, 본 발명에 의하면, 제 1 금속 배선의 일측에 완충막을 형성하여, 오정렬이 발생되어도, 하부 배선에 영향을 미치지 않게 되어, 브리지 현상이 발생되지 않는다.As described in detail above, according to the present invention, if a buffer film is formed on one side of the first metal wiring, even if misalignment occurs, the lower wiring is not influenced and no bridge phenomenon occurs.
또한, 완충막을 형성하므로서 비아홀의 폭을 소정 부분 연장할 수 있어, 비아홀내에 제 2 금속 배선을 효과적으로 형성할 수 있다.In addition, the width of the via hole can be extended by a predetermined portion by forming the buffer film, so that the second metal wiring can be effectively formed in the via hole.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960072790A KR100447982B1 (en) | 1996-12-27 | 1996-12-27 | Method for forming metal interconnection of semiconductor device using buffer layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960072790A KR100447982B1 (en) | 1996-12-27 | 1996-12-27 | Method for forming metal interconnection of semiconductor device using buffer layer |
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| Publication Number | Publication Date |
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| KR19980053662A KR19980053662A (en) | 1998-09-25 |
| KR100447982B1 true KR100447982B1 (en) | 2004-11-06 |
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| Application Number | Title | Priority Date | Filing Date |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60206151A (en) * | 1984-03-30 | 1985-10-17 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0379070A (en) * | 1989-08-22 | 1991-04-04 | Nec Corp | Semiconductor device |
| US5506434A (en) * | 1993-03-11 | 1996-04-09 | Sony Corporation | Solid-state imaging device having contact buffer layer interconnecting gate and vertical scan line |
| KR0122516B1 (en) * | 1994-03-03 | 1997-11-26 | 김주용 | Method for manufacturing metal wiring contact |
-
1996
- 1996-12-27 KR KR1019960072790A patent/KR100447982B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60206151A (en) * | 1984-03-30 | 1985-10-17 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0379070A (en) * | 1989-08-22 | 1991-04-04 | Nec Corp | Semiconductor device |
| US5506434A (en) * | 1993-03-11 | 1996-04-09 | Sony Corporation | Solid-state imaging device having contact buffer layer interconnecting gate and vertical scan line |
| KR0122516B1 (en) * | 1994-03-03 | 1997-11-26 | 김주용 | Method for manufacturing metal wiring contact |
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|---|---|
| KR19980053662A (en) | 1998-09-25 |
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