KR20030001908A - Metal line in semiconductor device and method for fabricating the same - Google Patents
Metal line in semiconductor device and method for fabricating the same Download PDFInfo
- Publication number
- KR20030001908A KR20030001908A KR1020010037775A KR20010037775A KR20030001908A KR 20030001908 A KR20030001908 A KR 20030001908A KR 1020010037775 A KR1020010037775 A KR 1020010037775A KR 20010037775 A KR20010037775 A KR 20010037775A KR 20030001908 A KR20030001908 A KR 20030001908A
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- wiring
- contact
- contact plug
- semiconductor device
- forming
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자에 대한 것으로, 특히 콘택플러그와 배선의 접촉저항을 감소시키기에 알맞은 반도체소자의 배선 및 그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device wiring and a method of forming the semiconductor device suitable for reducing contact resistance between a contact plug and a wiring.
종래 반도체소자의 배선 형성방법은 실리콘기판상에 일라인 방향으로 제1금속배선을 형성하고, 제1금속배선을 포함한 전면에 층간절연막을 형성하고, 제1금속배선의 일영역이 드러나도록 콘택홀을 형성하고, 콘택홀내에 콘택플러그를 형성하고, 콘택플러그의 상부와 접하며 상기 층간절연막상에 제2금속배선을 형성하는 단계를 통하여 진행된다.In the conventional method of forming a wiring of a semiconductor device, a first metal wiring is formed on a silicon substrate in one line direction, an interlayer insulating film is formed on the entire surface including the first metal wiring, and a contact hole is exposed so that one region of the first metal wiring is exposed. And forming a contact plug in the contact hole, contacting an upper portion of the contact plug, and forming a second metal wiring on the interlayer insulating film.
상기와 같이 제2금속배선은 콘택플러그의 상부면에만 접하고 있다.As described above, the second metal wiring contacts only the upper surface of the contact plug.
상기와 같은 종래 반도체소자의 배선 및 그 형성방법은 다음과 같은 문제가 있다.The wiring of the conventional semiconductor device as described above and a method of forming the same have the following problems.
콘택플러그의 상부면에만 제2금속배선이 접촉하고 있으므로 접촉저항을 감소시키는데 한계가 있다.Since the second metal wire contacts only the upper surface of the contact plug, there is a limit to reducing the contact resistance.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 콘택플러그와 배선의 접촉면적을 늘려서 접촉저항을 감소시키기에 알맞은 반도체소자의 배선 및 그 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor device wiring and a method of forming the semiconductor device suitable for reducing contact resistance by increasing the contact area between the contact plug and the wiring.
도 1은 본 발명의 실시예에 따른 배선의 레이아웃도1 is a layout diagram of wiring according to an embodiment of the present invention;
도 2는 도 1의 A-A'부분을 자른 구조 단면도FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1;
도 3은 도 1의 B-B'부분을 자른 구조 단면도3 is a cross-sectional view taken along the line B-B 'of FIG.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
10 : 실리콘기판 11 : 제1금속배선10 silicon substrate 11: first metal wiring
12 : 층간절연막 13 : 콘택플러그12: interlayer insulating film 13: contact plug
14 : 제2금속배선14: second metal wiring
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 배선은 기판상에 일라인 방향을 갖고 형성된 제1배선, 상기 제1배선의 일영역상이 드러나도록 콘택홀을 구비한 층간절연막, 상기 콘택홀 및 그 상부에 돌출되도록 형성된 콘택플러그, 상기 돌출된 콘택플러그의 상부 및 그 측면과 접하며 상기 제1배선과 직교하는 방향으로 형성된 제2배선을 포함함을 특징으로 한다.In order to achieve the above object, a wiring of a semiconductor device according to the present invention may include a first wiring formed on a substrate in one line direction, an interlayer insulating film having contact holes to expose a region of the first wiring, the contact hole, and the like. And a second plug formed to protrude on the upper portion of the contact plug, and a second wire formed in a direction orthogonal to the first wiring and in contact with the upper side and the side surface of the protruding contact plug.
상기와 같은 구성을 갖는 본 발명 반도체소자의 배선 형성방법은 기판상에 일라인 방향을 갖는 제1배선을 형성하는 단계, 상기 제1배선의 일영역상이 드러나도록 콘택홀을 구비한 층간절연막을 형성하는 단계, 상기 콘택홀내에 콘택플러그를형성하는 단계, 상기 콘택플러그가 돌출되도록 상기 층간절연막을 식각하는 단계, 상기 돌출된 콘택플러그의 상부 및 그 측면과 접하며 상기 제1배선과 직교하는 방향을 갖도록 제2배선을 형성하는 단계를 포함함을 특징으로 한다.In the method for forming a wiring of the semiconductor device of the present invention having the above structure, forming a first wiring having a one-line direction on a substrate, and forming an interlayer insulating film having a contact hole so that an image of one region of the first wiring is exposed. Forming a contact plug in the contact hole, etching the interlayer insulating layer so that the contact plug protrudes, contacting the upper and side surfaces of the protruding contact plug and having a direction perpendicular to the first wiring. And forming a second wiring.
첨부 도면을 참조하여 본 발명 반도체소자의 배선 및 그 형성방법에 대하여 설명하면 다음과 같다.A wiring and a method of forming the semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 1은 본 발명의 실시예에 따른 배선의 레이아웃도이고, 도 2는 도 1의 A-A'부분을 자른 단면도이며, 도 3은 도 1의 B-B'부분을 자른 단면도이다.1 is a layout view of a wiring according to an exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line B-B ′ of FIG. 1.
본 발명의 실시예에 따른 반도체소자의 배선은 도 1과 도 2와 도 3에 도시한 바와 같이 실리콘기판(10)상에 일라인 방향을 갖는 제1금속배선(11)이 있고, 상기 제1금속배선(11)의 일영역상이 드러나도록 콘택홀을 구비한 층간절연막(12)이 있고, 상기 콘택홀 및 그 상부에 돌출되어 측면이 드러난 콘택플러그(13)이 있고, 상기 돌출된 콘택플러그(13)의 상부 및 그 측면과 접하며 상기 제1금속배선(11)과 직교하는 방향으로 제2금속배선(14)이 형성되어 있다.In the semiconductor device wiring according to the embodiment of the present invention, as shown in FIGS. 1, 2, and 3, a first metal wiring 11 having a one-line direction is formed on the silicon substrate 10. There is an interlayer insulating film 12 having a contact hole so that an area of the metal wiring 11 is exposed, and there is a contact plug 13 protruding from the contact hole and an upper side thereof, the side of which is exposed, and the protruding contact plug ( The second metal wire 14 is formed in a direction orthogonal to the first metal wire 11 and in contact with the upper and side surfaces thereof.
상기와 같은 구성을 갖는 본 발명의 실시예에 따른 반도체소자의 배선 형성방법은 도 1과 도 2와 도 3에 도시한 바와 같이 실리콘기판(10)의 일영역에 도전성 제1금속층을 증착한 후에 배선 패턴 마스크를 이용하여 제1금속층을 식각해서 일라인 방향을 갖는 제1금속배선(11)을 형성한다.In the method of forming a wiring of a semiconductor device according to an embodiment of the present invention having the above configuration, as illustrated in FIGS. 1, 2, and 3, after the conductive first metal layer is deposited on one region of the silicon substrate 10. The first metal layer is etched using the wiring pattern mask to form the first metal wiring 11 having one line direction.
이후에 제1금속배선(11)을 포함한 실리콘기판(10) 전면에 층간절연막(12)을 증착한다.Thereafter, the interlayer insulating film 12 is deposited on the entire surface of the silicon substrate 10 including the first metal wiring 11.
그리고 상기 제1금속배선(11)의 일영역이 드러나도록 층간전연막(12)을 식각해서 콘택홀을 형성한다.The interlayer dielectric film 12 is etched to expose one region of the first metal wiring 11 to form a contact hole.
이어서 상기 콘택홀을 포함한 층간절연막(12)상에 텅스텐과 같이 도전성을 갖는 물질을 증착한 후, 에치백이나 화학적 기계적 연마를 하여 콘택홀내에 콘택플러그(13)를 형성한다.Subsequently, a conductive material such as tungsten is deposited on the interlayer insulating film 12 including the contact hole, and then the contact plug 13 is formed in the contact hole by etching back or chemical mechanical polishing.
다음에 상기 층간절연막(12)을 일정 두께 에치백하여 콘택플러그(13)의 상부 및 그 측면이 일정 두께를 갖고 돌출되도록 한다.Next, the interlayer insulating film 12 is etched back to have a predetermined thickness so that the upper and side surfaces of the contact plug 13 protrude with a predetermined thickness.
이후에 돌출된 콘택플러그(13)의 측면 및 그 상부를 포함한 층간절연막(12) 전면에 제2금속층을 증착한 후에 선택적으로 식각하여 제1금속배선(11)과 직교하도록 일라인 방향을 갖는 제2금속배선(14)을 형성한다.Subsequently, a second metal layer is deposited on the entire surface of the interlayer insulating layer 12 including the side surface and the upper portion of the contact plug 13 protruding therefrom, and then selectively etched to have a one-line direction to be orthogonal to the first metal wiring 11. The two metal wiring 14 is formed.
이때 제2금속배선(14)은 콘택플러그(13)의 상부 뿐만아니라 그 상부 측면과도 접하고 있으므로 표면적이 증대된다.At this time, since the second metal wiring 14 is in contact with not only the upper portion of the contact plug 13 but also the upper side surface thereof, the surface area is increased.
상기와 같은 본 발명 반도체소자의 배선 및 그 형성방법은 다음과 같은 효과가 있다.As described above, the wiring and the method of forming the semiconductor device of the present invention have the following effects.
콘택플러그와 제2금속배선의 접하는 면적을 증가시킬 수 있으므로 접촉 저항을 감소시킬 수 있다.Since the contact area between the contact plug and the second metal wiring can be increased, the contact resistance can be reduced.
또한 콘택플러그를 돌출시키고 콘택주변의 제2금속배선을 도그본리스(dogboneless)로 형성할 수 있으므로 타이트한 디자인룰에도 적용가능하다.In addition, since the contact plug can protrude and the second metal wiring around the contact can be formed as dogboneless, it is also applicable to tight design rules.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010037775A KR20030001908A (en) | 2001-06-28 | 2001-06-28 | Metal line in semiconductor device and method for fabricating the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010037775A KR20030001908A (en) | 2001-06-28 | 2001-06-28 | Metal line in semiconductor device and method for fabricating the same |
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| Publication Number | Publication Date |
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| KR20030001908A true KR20030001908A (en) | 2003-01-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020010037775A KR20030001908A (en) | 2001-06-28 | 2001-06-28 | Metal line in semiconductor device and method for fabricating the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100850069B1 (en) | 2006-12-27 | 2008-08-04 | 동부일렉트로닉스 주식회사 | Method for manufacturing metal line of semiconductor device |
-
2001
- 2001-06-28 KR KR1020010037775A patent/KR20030001908A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100850069B1 (en) | 2006-12-27 | 2008-08-04 | 동부일렉트로닉스 주식회사 | Method for manufacturing metal line of semiconductor device |
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