KR100215842B1 - An interconnection layer structure of semiconductor device and manufacturing method thereof - Google Patents
An interconnection layer structure of semiconductor device and manufacturing method thereof Download PDFInfo
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- KR100215842B1 KR100215842B1 KR1019960038974A KR19960038974A KR100215842B1 KR 100215842 B1 KR100215842 B1 KR 100215842B1 KR 1019960038974 A KR1019960038974 A KR 1019960038974A KR 19960038974 A KR19960038974 A KR 19960038974A KR 100215842 B1 KR100215842 B1 KR 100215842B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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Abstract
본 발명은 반도체 장치에 관한 것으로, 특히 배선층간 토폴로지(topology) 발생을 억제시키는데 적당하도록 한 반도체 장치의 배선구조 및 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a wiring structure and a method of a semiconductor device suitable for suppressing the occurrence of an interlayer topology.
이를 위한 본 발명의 반도체 장치의 배선구조 및 방법은 기판상에 절연층을 형성하고 상기 절연층을 선택적으로 제거하여 콘택흘을 형성하는 제 1 단계와; 배선이 형성될 부위의 상기 절연막을 소정 깊이로 제거하여 트랜치를 형성하는 제 2 단계와; 상기 콘택홀을 통해 기판과 연결되도록 상기 트랜치 부위에 배선을 형성하는 제 3 단계와; 상기 콘택홀 및 트랜치가 형성된 기판 전면에 베리어 금속층을 형성하는 제 4 단계와; 상기 콘택홀과 트랜치에 제 1 금속을 형성하는 제 5 단계와; 선택적으로 식각하는 제 6 단계를 포함하여 이루어지는 것을 특징으로 한다.A wiring structure and a method of a semiconductor device of the present invention for this purpose include a first step of forming an insulating layer on a substrate and selectively removing the insulating layer to form a contact hole; A second step of forming a trench by removing the insulating film at a portion where a wiring is to be formed to a predetermined depth; A third step of forming a wiring in the trench portion to be connected to the substrate through the contact hole; A fourth step of forming a barrier metal layer on the entire surface of the substrate on which the contact hole and the trench are formed; A fifth step of forming a first metal on the contact hole and the trench; And a sixth step of selective etching.
Description
본 발명은 반도체 장치에 관한 것으로, 특히 배선층간 토폴로지(topology) 발생을 억제시키는데 적당하도록 한 반도체 장치의 배선구조 및 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a wiring structure and a method of a semiconductor device suitable for suppressing the occurrence of an interlayer topology.
이하 첨부된 도면을 참조하여 일반적인 반도체 장치의 배선구조에 대하여 설명하면 다음과 같다.Hereinafter, a wiring structure of a general semiconductor device will be described with reference to the accompanying drawings.
도 1은 일반적인 반도체 장치의 배선레이 아웃도이다.1 is a wiring layout diagram of a general semiconductor device.
기판(1)상에 콘택흘을 갖는 절연막(도면에 도시하지 않음)이 형성되고 상기 콘택홀(7)을 통해 기판(1)과 전기적으로 연결되도록 상기 절연막상에 임의의 방향으로 금속배선(9)이 형성된다.An insulating film (not shown) having a contact hole is formed on the substrate 1 and is electrically connected to the substrate 1 through the contact hole 7. The metal wiring 9 Is formed.
이와 같이 반도체 장치의 종래 배선구조 및 방법을 설명하면 다음과 같다.The conventional wiring structure and method of the semiconductor device will now be described.
도 2a 내지 도 2f는 도 1의 A-A'선에 따른 종래의 반도체 장치의 배선공정 단면도이다.2A to 2F are cross-sectional views of a conventional semiconductor device according to a line A-A 'in FIG.
먼저 도 2a에 도시한 바와 같이 반도체 기판(1)상에 제 1, 제 2 절연막(2)(3)을 차례로 형성하고 활성영역을 정의하여 활성영역에만 남도록 패터닝 한다.First, as shown in FIG. 2A, first and second insulating films 2 and 3 are sequentially formed on a semiconductor substrate 1, and an active region is defined and patterned so as to remain only in an active region.
이때 제 1 절연막(2)은 버퍼 산화막이고, 제 2 절연막(3)은 질화막이다.Here, the first insulating film 2 is a buffer oxide film and the second insulating film 3 is a nitride film.
이어 도 2b에 도시한 바와 같이 상기 제 2 절연막(3)을 마스크로 일산화하여 필드영역에 필드 산화막(4)을 형성하고 제 1, 제 2 절연막(2)(3)을 제거한후 활성영역상에 불순물 이온을 주입한다.Next, as shown in FIG. 2B, the field oxide film 4 is formed in the field region by monolithizing the second insulating film 3 with the mask, and the first and second insulating films 2 and 3 are removed, Impurity ions are implanted.
이어서 도 2c에 도시한 바와 같이 불순물 확산영역(5)을 기판내에 형성한후 제 3 절연막(6)을 형성한다.Then, as shown in FIG. 2C, after the impurity diffusion region 5 is formed in the substrate, a third insulating film 6 is formed.
이어 포토에칭 공정을 이용하여 상기 불순물 확산영역(5)이 소정부분 노출되도록 상기 제 3 절연막(6)을 선택적으로 식각하여 상기 불순물 확산영역(5)과 배선층을 접촉시키기 위한 콘택홀(7)을 형성한다.A contact hole 7 for selectively etching the third insulating film 6 and contacting the impurity diffusion region 5 with the wiring layer is formed so as to expose the impurity diffusion region 5 at a predetermined portion using a photoetching process .
이때 제 3 절연막(6)은 후공정에서 형성될 다른 배선충과의 배선상 숏트(short)를 피하기 위하여 형성하며 콘택홀(7)을 포토리소그래피(photolithographic)과 에칭(etching) 방법을 이용하여 형성한다.At this time, the third insulating film 6 is formed in order to avoid a short on the wirings with other wiring lines to be formed in a later process, and the contact holes 7 are formed by photolithographic and etching methods .
이어서 도 2d에 도시한 바와 같이 콘택홀(7)을 포함한 기판(1) 전면에 베리어 금속층(8)을 형성한후 상기 베리어 금속층(8)상에 제 1 금속층(9)을 증착한다.Subsequently, as shown in FIG. 2D, a barrier metal layer 8 is formed on the entire surface of the substrate 1 including the contact hole 7, and then a first metal layer 9 is deposited on the barrier metal layer 8.
이때 콘택홀(7)과 후공정에서 형성될 제 2 금속층의 연결을 위해 상기 베리어 금속층(8)을 형성하고 상기 제 1 금속층(9)을 콘택의 리필링(contact refilling) 금속층이다.At this time, the barrier metal layer 8 is formed for the connection between the contact hole 7 and the second metal layer to be formed in a subsequent process, and the first metal layer 9 is a contact refilling metal layer of the contact.
이어 도 2e에 도시한 바와 같이 에치백(etch-back) 방법에 의해 콘택홀(7)에만 제 1 금속층(9)이 남도록 한다.Then, as shown in FIG. 2E, the first metal layer 9 is left only in the contact hole 7 by an etch-back method.
여기서 콘택홀(7)의 깊이를 보상하기 위하여 상기 제 1 금속층(g)을 에치백 방법에 의해 형성하도록 한다.Here, the first metal layer g is formed by an etch-back method in order to compensate the depth of the contact hole 7.
이어서 도 2f에 도시한 바와 같이 제 1 금속층(9)을 포함한 베리어 금속층(8) 전면에 제 2 금속층(10)을 형성하고 배선모양으로 패터닝 하여 상기 제 1 금속층(9)을 통해상기 불순물 확산영역(5)과 접속되는 배선층을 형성한다.2F, a second metal layer 10 is formed on the entire surface of the barrier metal layer 8 including the first metal layer 9 and is patterned in the form of a wiring so that the impurity diffusion region A wiring layer connected to the wiring layer 5 is formed.
도 3은 도 1의 B-B'선에 따른 종래의 반도체 장치의 배선단면도이다.3 is a cross-sectional view of a conventional semiconductor device taken along the line B-B 'in FIG.
반도체 기판(1)상의 전면에 형성되는 제 3 절연막(6)과, 상기 제 3 절연막(6)상에 일정영역을 가지고 차례로 형성되는 베리어 금속충(8)과 제 1 금속층(9) 및 제 2 금속층(10)으로 구성되어 있다.A third insulating layer 6 formed on the entire surface of the semiconductor substrate 1; a barrier metal layer 8 formed sequentially on the third insulating layer 6 with a predetermined region; a first metal layer 9, And a metal layer (10).
종래의 반도체 장치의 배선구조 및 방법에 있어서는 다음과 같은 문제점이 있었다.The conventional wiring structure and method of a semiconductor device have the following problems.
즉 배선층 금속층이 저항성(resistivity)이 큰 경우 배선층 자체의 저항을 줄이기 위하여 배선층 자체를 두껍게 해야한다.That is, when the metal layer of the wiring layer has a high resistivity, the wiring layer itself must be thickened in order to reduce the resistance of the wiring layer itself.
그러므로 배선층이 두꺼워지면 다층배선(multilayer interconnection) 형성시 토플로지(topology)증가로 인하여 공정이 어려워지고 포토리소그래프(photolithography)과 에칭(etching)시 로딩효과(load effect)을 발생시키는 원인이 된다.Therefore, if the wiring layer becomes thick, the process becomes difficult due to an increase in topology in the formation of multilayer interconnection and causes a load effect in photolithography and etching.
본 발명은 상기와 같은 문제점을 해결하가 위하아 안출한 것으로 배선층의 자체 쟈항의 감소와 다층배선시 배선층간 토폴로지의 발생을 억제시키는 반도체 장치의 배선구조 및 방법을 제증하는데 그 목적이 있다.It is an object of the present invention to propose a wiring structure and a method of a semiconductor device which can reduce the self-reflection of a wiring layer and suppress the occurrence of inter-wiring-layer topology in multi-layer wiring.
도 1은 반도체 장치의 배선 레이아웃도1 is a wiring layout diagram of a semiconductor device
도 2a 내지 도 2f는 도 1의 A-A'선에 따른 종래의 반도체 장치의 배선공정 단면도2A to 2F are cross-sectional views of a wiring process of a conventional semiconductor device taken along a line A-A '
도 3은 도 1의 B-B'선에 따른 종래의 반도체 장치의 배선 단면도3 is a cross-sectional view of a conventional semiconductor device taken along line B-B '
도 4a 내지 도 4g는 도 1의 A-A'선에 따른 본 발명의 반도체 장치의 배선공정 단면도4A to 4G are cross-sectional views of a wiring process of the semiconductor device according to the present invention taken along line A-A '
도 5a 내지 도 5d는 도 1의 B-B'선에 따른 본 발명의 반도체 장치의 배선공정 단면도5A to 5D are cross-sectional views of a wiring process of the semiconductor device according to the present invention taken along line B-B '
도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
40 : 반도체 기판 41 : 제 1 절연막40: semiconductor substrate 41: first insulating film
42 : 제 2 절연막 43 : 필드 산화막42: second insulating film 43: field oxide film
44 : 불순물 확산영역 45 : 제 3 절연막44: impurity diffusion region 45: third insulating film
46 : 콘택홀 47:포토레지스트46: contact hole 47: photoresist
48 : 트랜치 49 : 베리어 금속층48: trench 49: barrier metal layer
50 : 제 1 금속 51 : 제 2 금속50: first metal 51: second metal
본 발명의 반도체 장치의 배선방법은 기판상에 절연충을 형성하고 상기 절연층을 선택적으로 제거하여 콘택흘을 형성하는 제 1 단계와; 배선이 형성될 부위의 상기절연막을 소정 깊이로 제거하여 트랜치를 형성하는 제 2 단계와; 상기 콘택흘을 통해 기판과 연결되도록 상기 트랜치 부위에 배선을 형성하는 제 3 단계와; 상기 콘택홀 및 트랜치가 형성된 기판 전면에 베리어 금속층을 형성하는 제 4 단계와; 상기콘택홀과 트랜치에 제 1 금속을 형성하는 제 5 단계와; 선택적으로 식각하는 제 6 단계를 포함하여 이루어짐에 그 특징이 있다.A method of wiring a semiconductor device according to the present invention includes a first step of forming an insulating layer on a substrate and selectively removing the insulating layer to form a contact hole; A second step of forming a trench by removing the insulating film at a portion where a wiring is to be formed to a predetermined depth; A third step of forming a wiring in the trench portion to be connected to the substrate through the contact hole; A fourth step of forming a barrier metal layer on the entire surface of the substrate on which the contact hole and the trench are formed; A fifth step of forming a first metal on the contact hole and the trench; And a sixth step of performing selective etching.
또한 본 발명의 반도체 배선구조는 기판상의 소정부위에 콘택홀을 갖고 배선이 형성될 부위에 트랜치를 갖는 제 1 절연막과, 상기 제 1 절연막상에 상기 콘택홀을 통해 기판과 연결되도록 상기 트랜치 부위에 형성되는 배선층을 포함하여 구성됨에 그 특징이 있다.The semiconductor wiring structure of the present invention may further include a first insulating film having a contact hole at a predetermined portion of the substrate and having a trench at a portion where a wiring is to be formed and a second insulating film formed on the trench portion to be connected to the substrate through the contact hole, And a wiring layer formed thereon.
상기와 같은 본 발명의 반도체 장치의 배선구조 및 방법을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.The wiring structure and method of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 4a 내지 도 4g는 도 1의 A-A'선에 따른 본 발명의 반도체 장치의 배선공정 단면도이다.4A to 4G are cross-sectional views of the semiconductor device according to the present invention taken along the line A-A 'in FIG.
도 4a에 도시한 바와 같이 반도체 기판(40)상에 제 1, 제 2 절연막(41)(42)을 차례로형성하고 활성영역을 정의하여 활성영역에만 남도록 패터닝 한다.The first and second insulating films 41 and 42 are sequentially formed on the semiconductor substrate 40 as shown in FIG. 4A, and the active region is defined and patterned to remain only in the active region.
이어 도 4b에 도시한 바와 같이 상기 제 2 절연막(42)을 마스크로 열산화 하여 필드영역에 필드 산화막(43)을 형성하고 제 1, 제 2 절연막(41)(42)을 제거한후 활성영역상에 불순물 이온을 주입한다.4B, a field oxide film 43 is formed in the field region by thermal oxidation using the second insulating film 42 as a mask, and the first and second insulating films 41 and 42 are removed. Thereafter, Impurity ions are implanted.
이어서 도 4c에 도시한 바와 같이 불순물 확산영역(44)을 기판(40)내에 형성한후 제 3 절연막(45)을 형성한다.Then, as shown in FIG. 4C, the impurity diffusion region 44 is formed in the substrate 40, and then the third insulating film 45 is formed.
이어 포토에칭 공정을 이용하여 상기 불순물 확산영역(44)이 소정부분 노출되도록 상기 제 3 절연막(45)을 선택적으로 식각하여 콘택흘(46)을 형성한다.The contact hole 46 is formed by selectively etching the third insulating film 45 so that the impurity diffusion region 44 is exposed at a predetermined portion using a photoetching process.
이때 제 3 절연막(45)은 후공정에서 형성될 다른 배선층과의 숏트(short) 피하기 위하여 형성하며 콘택홀(46)을 포토리소그래피와 에칭방법을 이용하여 형성한다.At this time, the third insulating film 45 is formed to avoid a short-circuit with another wiring layer to be formed in a subsequent step, and the contact hole 46 is formed by photolithography and etching.
이어서 도 4d와 도 5a에 도시한 바와 같이 콘택홀(46)을 포함한 전면에 포토레지스트(47)를 증착하고 후공정에서 형성될 제 2 금속층(51) 하부에 배선층을 따라서 트랜치(trench : 48)를 형성한다.A photoresist 47 is deposited on the entire surface including the contact hole 46 and a trench 48 is formed along the wiring layer under the second metal layer 51 to be formed in the subsequent process as shown in FIGS. 4D and 5A. .
이때 후공정에서 형성될 제 2 금속층(51) 하부에도 금속층의 리필링이 될수 있도록한다.At this time, the metal layer may be refilled in the lower part of the second metal layer 51 to be formed in the post-process.
이어 도 4e와 도 5b에 도시한 바와 같이 상기 포토레지스트(47)를 제거한후 콘택홀(46)과 트랜치(48)를 포함한 기판(40) 전면에 베랴어 금속층(49)을 형성한다.After the photoresist 47 is removed as shown in FIGS. 4E and 5B, a barrier metal layer 49 is formed on the entire surface of the substrate 40 including the contact hole 46 and the trench 48.
그리고 상기 베리어 금속층(49)상에 제 1 금속층(50)을 증착한다.A first metal layer 50 is deposited on the barrier metal layer 49.
이어서 도 4f와 도 5c에 도시한 바와 같이 제 1 금속층(50)을 에치백하여 콘택홀(46)과 트랜치(48)에 상기 제 1 금속층(50)을 형성한다.The first metal layer 50 is etched back to form the first metal layer 50 in the contact hole 46 and the trench 48 as shown in FIGS. 4F and 5C.
이어 도 4g와 도 5d에 도시한 바와 같이 제 1 금속층(50)을 포함한 베리어 금속층(49) 전면에 제 2 금속층(51)을 형성한다.The second metal layer 51 is formed on the entire surface of the barrier metal layer 49 including the first metal layer 50 as shown in FIGS. 4G and 5D.
그러므로 제 1 금속층(50)을 통해 상기 불순물 확산영역(44)과 접속되는 배선충의 형성을 완료한다.Therefore, formation of a wiring line connected to the impurity diffusion region 44 through the first metal layer 50 is completed.
본 발명의 반도체 장치의 배선형성 방법에 있어서는 첫째, 같은 두께의 배선에 대하여 배선저항을 감소시킬수 있다.In the method of forming a wiring of a semiconductor device of the present invention, first, wiring resistance can be reduced with respect to wiring having the same thickness.
둘째, 같은 배선저항에 대하여 배선층의 두케를 얇게 할수 있다.Second, the thickness of the wiring layer can be made thinner against the same wiring resistance.
셋째, 배선층의 두께를 얇게 할수 있으므로 다층배선에 있어 층간 토포로지를 개선 할 수 있고 공정의 난이도를 낮출수 있는 효과가 있다.Third, since the thickness of the wiring layer can be made thinner, the interlayer topology can be improved in the multilayer wiring, and the degree of difficulty of the process can be lowered.
Claims (5)
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| KR1019960038974A KR100215842B1 (en) | 1996-09-09 | 1996-09-09 | An interconnection layer structure of semiconductor device and manufacturing method thereof |
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| US10732666B2 (en) | 2017-02-17 | 2020-08-04 | Lg Electronics Inc. | Knob assembly for cook top |
| KR101912932B1 (en) | 2017-02-22 | 2018-10-29 | 엘지전자 주식회사 | Knob assembly having display device for cook top |
| US11231180B2 (en) | 2017-02-17 | 2022-01-25 | Lg Electronics Inc. | Knob assembly for cook top |
| KR102174849B1 (en) | 2017-07-26 | 2020-11-05 | 엘지전자 주식회사 | Universal joint and knob assembly and appliance therewith |
| EP3364266B1 (en) | 2017-02-17 | 2020-01-08 | LG Electronics Inc. | Knob assembly for cooktop |
| KR102101415B1 (en) | 2017-07-24 | 2020-04-16 | 엘지전자 주식회사 | Knob assembly and appliance therewith |
| US11635782B2 (en) | 2017-02-17 | 2023-04-25 | Lg Electronics Inc. | Knob assembly for cook top |
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