JPS60206151A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent short circuits along a step in a multilayer device between its lower and upper conductive layers and disruption of wirings belonging to the upper conductive layer by a method wherein the entire surface of a second insulating layer is flattened by forming a P-doped insulating layer on the surface of the first insulating layer. CONSTITUTION:On a semiconductor substrate 11 covered with an impurity- diffused layer 12, a first insulator 13 of PSG or the like is formed. An insulating layer 14 is then formed densely diffused with P by the ion implantation or diffusion method. A conductive layer 15a for contacts and a conductive layer 15b for wirings are formed. A second insulating layer 16 is formed of P-glass or an oxide by CVD under a normal pressure. Next, a second conductive layer 17 is formed. The existence of the P-doped insulating layer 14 on the first insulating layer 13 accelerates the growth of the second insulating layer 16, which alleviates the inclination C in the second insulating layer 16 at a step. This design greatly reduces the possibility for the second conductive layer to be formed excessively thin or of disruption thereof, which contributes to the prevention of short circuits between the first and second conductive layers.

Description

Detailed Description of the Invention (Technical Field) The present invention solves short-circuits between a lower conductive layer and an upper conductive layer and disconnections in the upper conductive layer at a stepped portion in multilayer wiring, and manufactures an alternating conductor device. Regarding the method.

(Prior Art) An example of a typical manufacturing method for a semiconductor device having a conventional multilayer wiring structure will be described using process diagrams shown in FIGS. 1(a) to 11Q(d). First, as shown in FIG. 1(a), on a semiconductor substrate 1 on which a P-type or N-type diffusion layer 2 is formed,
For example, a first insulating layer 3 such as an oxide film is formed.

Next, as shown in FIG. 1(b), a window for making contact with the diffusion layer 2 is provided in the insulating layer 3, and then a metal film,
For example, an M film is formed by vapor deposition, and a conductive layer 4a for making contact with the diffusion layer 2 and a conductive layer 4bi for wiring are formed by photolithography.

Next, in the structure shown in FIG. 1(c), conductive layers 4a and 4b are formed.
A clean glass oxide film or the like is formed on the entire first insulating layer 3 using a CVD method or the like to form a second insulating layer 5.

Next, as shown in FIG. 1(d), a window for making a contact 'ff- is selectively provided on the first conductive layer 4a by photolithography in the second insulating layer 5, and then this window is A metal film such as an aluminum film is formed on the second insulating layer 5 including the second insulating layer 5. Thereafter, a necessary wiring layer and a second conductive layer 6 are formed by photolithography.

However, the semiconductor device shown in FIG. 1(d) has the following drawbacks. In FIG. 1(d), the second insulating layer 5 has the same uneven surface step as the underlying first conductive layers 4a, 4b, etc.; 6 becomes thinner and rips, resulting in so-called step-cutting.

In addition, since the second insulation N5 becomes thinner at the circle mark B at the end of the lower first conductive layer 4a, etc., the dielectric strength voltage between the first conductive layer 4a and the second conductive layer 6 is significantly reduced at the circle mark B. It has the disadvantage that it decreases.

In order to eliminate all of these drawbacks, various techniques have been developed, including, for example, a method using anodized aluminum (Japanese Patent Publication No. 10788/1988) and a method using inclined wiring etching ( (Japanese Patent Publication No. 49-4177), by low-temperature alumina film (Japanese Patent Publication No. 51-159)
No. 57), polyimide resin film (Special Publication No. 57),
However, these prior art methods have advantages and disadvantages, and are not necessarily good solutions.

(Objective of the Invention) The object of the present invention is to short-circuit the lower conductive layer and the upper conductive layer at the stepped portion in multilayer wiring by adding simple processing without changing all the conventional processes. Another object of the present invention is to obtain a method for manufacturing a semiconductor device that can solve the problem of disconnection in the upper conductive layer.

(Summary of the Invention) The main point of this invention is to form an insulating layer fully doped with phosphorus on the surface of the first insulating layer, and when forming the second insulating layer by atmospheric pressure CVD, phosphorus is CVD on insulating layer containing
Taking advantage of the faster film growth rate, the second conductive layer on the first conductive layer
The purpose is to reduce the difference in thickness between the insulating layer and the second insulating layer on the first insulating layer, thereby flattening the entire surface of the second insulating layer.

(Example) Next, an example of the method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. 2(a) to 2(e). No trenches,
As shown in Fig. 2(a), P-type or N-type diffusion layer 12
For example, an oxide film (P
The first insulating layer 13 such as SG) is completely formed.

Next, as shown in FIG. 2(b), on the surface of the first insulating layer 13, ions are implanted or diffused to form a 1×1 0%-
Doped with phosphorus at a high concentration of about 3 fc1000-200
A phosphorus-doped insulating layer 14 of about 0X is formed.

Next, as shown in FIG. 2(c), a window for making contact with the diffusion layer 12 is provided in the first insulating layer 13 and the phosphorus-doped insulating layer 14, and then a metal film, for example, is 5000λ~9oooA is formed by vapor deposition etc.

A conductive layer 15a for making contact with the diffusion layer 12 and a conductive layer 15kl for forming wiring are formed using photorin technology.

Next, as shown in FIG. 2(cl), a conductive layer 15a is formed.

A nitrogen, phosphorus glass, or oxide film is formed on the first insulating layer 13 including the first insulating layer 15b and the phosphorus-doped insulating layer 14 by atmospheric pressure CVD at 300°C.
The second insulating layer 16 is formed with a thickness of 5000λ to 5oooA at a low temperature of 500° C. and normal pressure.

Next, as shown in FIG. 2(e), a window for forming a contact If is selectively provided on the first conductive layer 15a by photolithography in the second insulating layer 16, and a second A metal film, for example M, is deposited on the insulating layer 16 by vapor deposition.
i~1ooooX is formed.

After that, photolithography technology was applied, the necessary wiring layer thickness,
A second conductive layer 17 is formed.

The characteristic feature of this invention is that the PSG on the first absolute layer 13
(phosphorous-doped insulating layer 14), the second insulating layer 16
The growth rate will be higher if it is fully utilized. That is, the growth rate of the film thickness at the first insulating layer 13 whose base is PSG is faster than that of the conventional example. On the conductive layer, the growth rate of the film thickness is the same as in the conventional example.

Therefore, by selectively growing, Fig. 2(e)
As is clear from 2- et al., the second insulating layer 1 at the stepped portion
The height difference C' can be reduced to 6. Here, when the semiconductor devices obtained by the conventional manufacturing method and the manufacturing method of the present invention are compared in a table, the results are shown in Table 1 below.

Table 1 In Table 1, this effect remains the same whether the CVD film is an oxide film or a phosphorus-doped film. This effect was experimentally confirmed by C
The lower the VD growth temperature, the greater the effect. Therefore, the lowest temperature within the range in which the CVD reaction occurs (300 to 400° C. is preferable).

In this invention, growth is performed by fully utilizing the dependence of the atmospheric pressure CVD film growth rate on the degree of roughness of the underlying surface. As shown in Figure 3 (Ratio of phosphorus content in insulating film to growth rate of CVD@), as the amount of phosphorus in the underlying insulating layer increases, the growth rate of CVD@ increases as well. When the base insulation/layer contains phosphorus, the growth rate of the CVD film increases compared to when it does not contain phosphorus (at the position marked with a circle)5.Using this phenomenon, the second insulation When the layer 16 is formed by an atmospheric pressure CVD method, when an insulating layer doped with phosphorus is formed on the surface of the first insulating layer 13 (this invention), the surface of the first insulating layer 13 is entirely doped with phosphorus. Since the growth rate of the CVD film is increased compared to when no insulating layer is formed (conventional), the thickness of the CVD film on the first insulating layer 13 is increased.

As can be seen from the cross-sectional views of the second insulating film 16 formed by the conventional manufacturing method shown in FIG. 4(a) and the manufacturing method according to the present invention shown in FIG. Compared to the part marked A, the thickness of the second insulating layer 16 in the part A marked with a circle in this disaster example is
In addition to being thicker than the conventional example, the difference in film thickness between the second insulating layer 16 on the conductive layer 15a and the second insulating layer 16 on the insulating layer 14 completely doped with phosphorus is significantly reduced.

Therefore, when the entire manufacturing method according to the present invention is used, the second
As shown in Figure (e), at the circle C portion, the second conductive layer 17 is less likely to become thin or break off. In addition, in the circled part, the conductive i as the first conductive layer
The thinning of the second insulating layer 16 at the end portion of @15a is significantly reduced, and short circuits between the Lυ conductive layer 15a and the second conductive layer 17 are also significantly reduced.

The detailed phenomenon of the difference in the CVD film growth rate on the phosphorus-doped insulating layer 4 used in this invention and on the first insulating layer 3 not fully doped with phosphorus has not yet been elucidated, but FIG. The experimental results shown below have been obtained. Due to the above advantages, multilayer wiring in a semiconductor device can be easily formed.

(Effects of the Invention) As explained above, the present invention is characterized in that when the entire second insulating layer is formed by applying a phosphorus-doped film on the surface of the first insulating layer using the atmospheric pressure CVD method, the CVD process is performed on the insulating layer containing phosphorus. By taking advantage of the high film growth rate, the difference in thickness between the second insulating layer on the first conductive layer and the second insulating layer on the first insulating layer is reduced. Since the entire surface of the layer is flattened, the occurrence of thinning of the second conductive layer and cutting of the second conductive layer is greatly reduced.
Short circuits between the first conductive layer and the second conductive layer can be completely prevented.

Further, it has the advantage that it can be manufactured by adding simple processing without changing the conventional processing steps.

[Brief explanation of drawings]

1(a) to 1(d) are process explanatory diagrams of a conventional semiconductor device manufacturing method, respectively, and FIGS. 2(a) to 2(e) are respectively process explanatory diagrams of a semiconductor device manufacturing method of the present invention. FIG. 3 is a graph showing the relationship between the phosphorous screen ratio in the first insulating layer and the growth rate ratio of the CVD film. , FIG. 4(a) is a diagram for explaining the stepped portion between the first conductive layer and the second insulating layer in a semiconductor device obtained by a conventional semiconductor device manufacturing method, and FIG. FIG. 4(a) shows the entire stepped portion between the first conductive layer and the second insulating layer of a semiconductor device obtained by an embodiment of the semiconductor device manufacturing method of the invention. FIG. 1.1... Semiconductor substrate, 12... Diffusion layer, 13...
- First insulating layer, 14... Phosphorus-doped insulating layer, 15a,
15b... Conductive layer, 16... Second insulating layer, 17...
a second conductive layer; Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] A step of forming a phosphorus-doped insulating layer on the surface of a first insulating layer on a semiconductor substrate, a step of completely forming a first conductive layer on the phosphorus-doped insulating layer, and a step of forming the first conductive layer on the surface of the first insulating layer on the semiconductor substrate. The first insulating layer containing C is formed on the phosphorus-doped insulating layer.
A method for manufacturing a semiconductor device including a step of completely forming a second insulating layer and a step of forming a second conductive layer on the second insulating layer.