JPS632375A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To form structure having no overhang section in order to prevent the lowering of breakdown strength due to the overhang section by processing a lower electrode for a stacked capacitor through oxidation by the self- alignment of a dielectric film. CONSTITUTION:The form of the end section of an silicon nitride film 10 as a dielectric film takes a parallel or slightly pushed-up wind shape because lower polycrystalline silicon 9 is oxidized by self-alignment using the silicon nitride film 10 as the dielectric film as a mask and polycrystalline silicon is converted into an oxide film 12 while being cubically expanded in the forms of the end sections of a lower electrode and the dielectric film. Consequently, the lower electrode 9 and an upper electrode 13 are not short-circuited, and the dielectric film is not shaped irregularly and no stress is applied. The lowering of capacitor breakdown strength resulting from an overhang section which has been at issue is improved, and yield and reliability are also enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a semiconductor device suitable for improving the yield and reliability of stacked capacitor memory cells. .

[Conventional technology]

MOS memory cells are mainly of the one-transistor, one-capacitor type, and as a result of higher integration and smaller cell sizes, the soft error occurrence rate has increased. For this reason, a stacked capacitor type memory cell is used, in which the structure of the memory cell is improved to increase the capacitance of the capacitor. At this time, if the electrode of the capacitor is made of polycrystalline silicon, it is appropriate to use a silicon nitride film or an oxidized silicon nitride film as the dielectric film.

[Problem that the invention seeks to solve]

One stacked capacitor cell will be explained using a cross-sectional view. In FIG. 2, a field oxide film 2 is formed on a silicon substrate 1 using a selective oxidation method, and then a gate oxide film 3 and a third layer gate electrode 4 of polycrystalline silicon are formed. Thereafter, n9 type impurity diffusion regions 5 and 6 are formed by self-alignment to form a transistor. Furthermore, add the insulating film 7 between the eyebrows 5.
The second layer polycrystalline silicon electrode 9 and the impurity diffusion region 6 are connected through the capacitor and the conductive portion 8. The electrode 9 is made of, for example, phosphorus-doped polycrystalline silicon, and is formed of PSG or the like. In order to obtain a capacitor, the area is determined using processing methods such as dry etching.

A capacitor dielectric film 10 is formed thereon using a silicon nitride film or an oxidized nitride film, and later a third layer of polycrystalline silicon electrodes 13 is formed and processed to form a stacked capacitor. Since the stacked capacitor is thus formed on the gate of the cell or on the field oxide film 2, it can occupy a larger area than the capacitor of a normal memory cell laid out on a plane. Therefore, the capacity becomes large and it can be applied to high integration.

However, a decrease in the capacitance breakdown voltage is observed at the end portion 14 of the electrode 9 of the stacked capacitor shown in FIG. 2, resulting in deterioration of device characteristics and problems in yield. Third
The end portion 14 is enlarged in the figure to explain the cause of the decrease in breakdown voltage. That is, Si is grown on the entire surface of polycrystalline silicon 4 by vapor phase growth.
An insulating film 7 of O2 film or PSGIIN is formed, and phosphorus-doped polycrystalline silicon 9 is further formed by vapor phase growth.

Thereafter, polycrystalline silicon 9 is processed using photoresist as a mask, leaving a region equivalent to the area of the capacitor. Processing of this polycrystalline silicon is normally carried out by dry etching, but in order to completely process the inside of the patch or wafer, over-etching occurs, which means that the f-base insulating film 7 is also etched. , a dielectric film 10 to be formed thereafter. Further, the shape of the phosphorus-doped polycrystalline silicon 13 serving as the upper electrode of the capacitor takes the form of an overhang, as shown by a portion 15 surrounded by a circle in the figure. Due to the shape shown in 14, breakdown is likely to occur due to the electric field applied to the Φ capacitor, resulting in a decrease in the capacitor's breakdown voltage. The relationship between this shape and the breakdown voltage drop may be due to the occurrence of 1/l field concentration on the protrusion at the end of the lower electrode 9, irregular growth of the dielectric film 10, 11 on the overhang part, or stress on the film. It is thought that this is taking place.

SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method for forming a structure without an overhang in order to prevent a drop in breakdown voltage due to the overhang in the stacked capacitor described above.

[Means for solving problems]

The above object is achieved by processing the lower part xi of the stacked capacitor by self-aligned oxidation of the dielectric film (silicon nitride film in this case) instead of the conventional dry etching method.

[Effect]

According to the present invention, the lower electrode portion of the stacked capacitor,
Since the dielectric film is processed by self-aligned oxidation, it is possible to form a shape without overlapping, resulting in improved capacitor dielectric strength, improved yield, and a highly reliable stacked capacitor memory cell.

〔Example〕

An embodiment of the present invention will be described below with reference to one drawing.

FIG. 1 is a cross-sectional view of the stacked capacitor of the present invention, in which 3iαl, PS is grown on polycrystalline silicon 4 by vapor phase growth.
An insulating film 7 of G or the like is formed, and a capacitor is further stacked and formed. That is, the lower electrode 9 of the capacitor is obtained by vapor phase growth of polycrystalline silicon in monosilane/Nz gas at a temperature of 630C, and further phosphorus doping using phosphorus oxychloride. Subsequently, a silicon nitride film 10 to be used as a dielectric film of the capacitor is obtained by vapor phase growth at 760 C in an atmosphere of dichlorosilane and ammonia, and the silicon nitride film 10 in the capacitor portion is left by photoetching and dry etching. Next, oxidation is carried out at 950C for 55 minutes in a wet oxygen atmosphere at normal pressure.
Or high pressure wet oxidation, e.g. 90002 at 7 atm.
When oxidation is performed for 5 minutes, a silicon oxide film 11 grows to a thickness of about 4 nm on the silicon nitride film 1o and becomes a dielectric film, and at the same time, the lower part of the capacitor that is not covered with the silicon nitride film 10 is removed. Polycrystalline silicon 9 is also oxidized and converted into silicon oxide film 12. At this time, under the conditions that the above oxidation process forms a silicon oxide film 11 of iC4 (nm) on the silicon nitride film lo, a silicon oxide film 12 of 500 (nm) is formed on the lower polycrystalline silicon 9. If the film thickness of the polycrystalline silicon 9 at the time of formation is 250 (nm) or less, all the polycrystalline silicon in the parts not covered with the silicon nitride film (other than the capacitor part) is converted to a silicon oxide film, and the interlayer Useful as an insulating film. The ratio of oxidation of silicon nitride film 9 and oxidation of polycrystalline silicon 9 can be set over a wide range (for example, by controlling the phosphorus concentration in polycrystalline silicon, or by controlling the temperature and atmosphere during oxidation, etc.) control, etc.), and the thickness of polycrystalline silicon 9 serving as the lower electrode can be freely set. Furthermore, the dimensions of the polycrystalline silicon 9 that will become the lower electrode are determined by the processing dimensions of the capacitor dielectric film 10. In other words, the processing is performed by self-alignment of the dielectric film 10, so processing accuracy is extremely high compared to conventional processing methods. It has the advantage of getting better. Furthermore, the lower electrode processing step of the conventional manufacturing process of capacitor lower electrode processing, GT body film formation, pattern alignment, and dielectric film processing,
There is also the advantage that the two steps of mask alignment of the electrode and dielectric film are eliminated. 15 in the figure shows the shape of the lower electrode and the end of the dielectric film. The shape of this part is such that the lower polycrystalline silicon 9 is oxidized by self-alignment using the silicon nitride film 10, which is a dielectric film, as a mask, and the polycrystalline silicon is converted into an oxide film 12 while expanding in volume. The shape of the end portion of the silicon nitride film 10 is a parallel or slightly pushed-up airfoil shape. As a result, the shape is significantly different from that shown in FIG. 3, and there is no short circuit between the base electrode 9 and the upper electrode 13.

Furthermore, the formation of the dielectric film will not become irregular and stress will not be applied.

The conventional problem of lower capacitor breakdown voltage caused by overhangs has been resolved, and yield and reliability have also been improved.

FIG. 4 is a sectional view of a stacked capacitor showing another embodiment of the present invention, in which a combination film of a silicon nitride film and a silicon oxide film, mainly consisting of a tantalum oxide film, is used as the dielectric film. 5iQ2. is deposited on polycrystalline silicon 4 by vapor phase growth. An insulating film 7 such as PSG and polycrystalline silicon 9 as a lower electrode are formed, and a silicon nitride film 10 and a tantalum oxide film 16, which will become dielectric films, are formed by vapor phase growth and sputtering, respectively. Thereafter, by photoetching and dry etching, the silicon nitride film 10 and tantalum oxide film 16 in the region that will become the capacitor portion are left, and the other regions are removed. Further, when heat-treated in an oxidizing atmosphere, oxygen acts on the tantalum oxide film 16 and at the same time oxidizes a part of the surface of the silicon nitride film 10 and converts it into a silicon oxide film 11.
A dielectric film having a three-layer structure of a silicon oxide film 11 and a tantalum oxide film 16 is formed, and polycrystalline silicon 9 in a region where no silicon nitride film 1° remains is oxidized to form a silicon oxide film region 12. In this way, processing of the polycrystalline silicon 9 that will become the lower electrode of the capacitor does not require the use of processing methods such as photoetching, and is performed by thermal oxidation through self-alignment of the silicon nitride film 10 and tantalum oxide film 16, which reduces the number of processing steps. [Processing accuracy improves. Furthermore, the shape of the end of the dielectric film becomes airfoil-like as in FIG. In case of short circuit of capacitor, dielectric [10
, 11, 16+7) The formation will not become irregular and stress will not be applied.

Therefore, the reduction in capacitor breakdown voltage caused by the overhang portion, which has been a problem in the past, has been improved, and the yield and reliability have also been improved.

〔Effect of the invention〕

According to the present invention, the end structure of the stacked capacitor is improved and overhang is eliminated, so that the dielectric strength of the capacitor is improved, and its yield and reliability are also improved. Moreover, K has the effect that the manufacturing process of the stacked capacitor type cell can be made into a cylindrical process and the degree of processing can be further improved.

[Brief explanation of the drawing]

FIG. 1 is a partially enlarged sectional view showing one embodiment of the present invention, and FIG.
3 is a partially enlarged sectional view of a conventional stacked capacitor, and FIG. 4 is a partially enlarged sectional view showing another embodiment of the present invention. 1... Silicon substrate, 2... Field oxide film, 3
...Gate oxide film, 4...n polycrystalline silicon (gate). 5.6... Impurity diffusion region, 7...5iCh or P
SG film, 8...source or drain contact hole,
9...n" polycrystalline silicon (lower capacitor i[ff1
). 10... Dielectric film (silicon nitride film), 11... Dielectric film (silicon oxide film), 12... Silicon oxide film. 13...n polycrystalline silicon (capacitor upper electrode)
. 14.15... end of capacitor, 16... tantalum oxide film. Plan 1 Words 2 Diagram name 3 countries

Claims (1)

[Claims] 1. Self-alignment of the dielectric film after processing at least a portion of the dielectric film in a method for manufacturing a semiconductor memory device including a stacked capacitor in which a capacitor is formed on a conductive thin film extending from a substrate. 1. A method of manufacturing a semiconductor memory device, comprising processing a lower electrode into a desired shape by using a method of manufacturing a semiconductor memory device. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the lower electrode is made of doped polycrystalline silicon. 3. A method of manufacturing a semiconductor memory device according to claims 1 or 2, wherein the dielectric film includes at least a silicon nitride film. 4. A method of manufacturing a semiconductor memory device according to claims 1 to 3, wherein the lower electrode is processed by thermal oxidation. 5. A method of manufacturing a semiconductor memory device according to claims 1 to 4, wherein the lower electrode is processed by dry etching and thermal oxidation.