JPH04299854A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent a spontaneous oxide film from developing between a first capacitor electrode (a storage electrode) and capacitor dielectric film composed of silicon nitride and its thermal oxide. CONSTITUTION:A second undoped polycrystalline silicon film is formed on the surface of a first capacitor electrode (a storage electrode). When a silicon nitride film 111 is heated to form an oxide layer 112 as capacitor dielectric on its surface, the second undoped polycrystalline silicon film is transformed into a second n<+> polycrystalline silicon film 151.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor device and its manufacturing method, and in particular to a dynamic random access memory (DRAM) having a stacked capacitor.
and its manufacturing method.

0002

2. Description of the Related Art Various structures have been used for DRAM cell structures, and with reference to FIGS. explain.

As shown in FIG. 7, first, an element isolation oxide film 202 is formed on the surface of a p-type silicon substrate 201 by selective oxidation, and a gate electrode 204 is formed on the surface of the element formation region via a gate oxide film 203. After forming a word line, n+ is formed on the surface of the p-type silicon substrate 201 by arsenic ion implantation.
Diffusion layers 205a and 205b are formed. Next, n+
A first silicon oxide film 206 as an interlayer insulating film having a first contact hole 207 reaching the diffusion layer 205a is deposited over the entire surface, and after a non-doped polycrystalline silicon film 208 is deposited, phosphorus is diffused as an impurity.

Next, as shown in FIG. 8, after patterning the polycrystalline silicon film 208 to form a first capacitor electrode (storage electrode) 209, a silicon nitride film 211 is deposited, followed by thermal oxidation. Then, an oxide layer 212 is grown on the surface of the silicon nitride film 211. Thereafter, a non-doped polycrystalline silicon film is deposited, phosphorus is diffused as an impurity, and then patterned to form a second capacitor electrode 213. Note that when patterning the second capacitor electrode 213, the oxide layer 212 directly under the polycrystalline silicon film to be removed,
Silicon nitride film 211 is removed at the same time.

Next, as shown in FIG. 9, a second silicon oxide film 214 is deposited on the entire surface as an interlayer insulating film, and a second contact hole 215 is opened to reach the n+ diffusion layer 205b. Subsequently, an Al film is deposited and patterned to form digit lines 216.

[0006]

[Problems to be Solved by the Invention] First capacitance electrode (storage electrode) 209 of the conventional stacked capacitor described above
When depositing the silicon nitride film 211 on the surface, 700~
Deposition is performed by the low pressure CVD method at a temperature of 800°C, but since the first capacitor electrode (storage electrode) 209 contains a high concentration of phosphorus, it reacts with the oxygen remaining inside the low pressure CVD device. Therefore, a natural oxide film 210 is likely to grow on the surface of the first capacitor electrode (storage electrode) 209. Silicon nitride film 21
1 is deposited on this natural oxide film 209, so as a capacitor insulating film, the natural oxide film 209, silicon nitride film 211,
The oxide film layer 212 has a three-layer film structure, and the film thickness is increased. Further, the thickness of the natural oxide film 209 varies depending on the concentration of residual oxygen in the low pressure CVD apparatus, and it is difficult to control the film thickness. Since such thickening of the capacitor insulating film reduces the capacitance of the capacitor, the circuit operation margin of the DRAM is reduced, and the resistance to alpha rays is reduced, resulting in a decrease in reliability.

Furthermore, on the surface of the first capacitor electrode (storage electrode) 209 into which phosphorus is diffused, PS is formed as a reaction product during the diffusion.
The first problem is that G grows unevenly and then PSG is removed.
Irregularities are formed on the surface of the capacitor electrode (storage electrode) 209. In a capacitor in which a second capacitive electrode 213 is formed on the first capacitive electrode (storage electrode) 209 via a capacitive insulating film, electric field concentration occurs in the uneven portions, resulting in poor long-term reliability of the capacitive insulating film. There's a problem.

[0008]

[Means for Solving the Problems] A semiconductor device of the present invention includes:
a first capacitor electrode formed of a first polycrystalline silicon film containing impurities connected to a semiconductor substrate; a silicon nitride film covering the first capacitor electrode; and oxidation of the silicon nitride covering the surface of the silicon nitride film. In a semiconductor device having a capacitor including a capacitive insulating film formed by a layer and a second capacitive electrode formed by a conductive film covering a surface of an oxide layer, the first capacitive electrode is formed by a first polycrystalline film. It is formed of a silicon film and a second polycrystalline silicon film that covers at least the upper surface of the first polycrystalline silicon film.

The method for manufacturing a semiconductor device of the present invention includes forming a MOS transistor having a diffusion layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, depositing an interlayer insulating film on the entire surface, and forming a capacitor connection that reaches the diffusion layer. forming a first polycrystalline silicon film of opposite conductivity type on the entire surface, and forming a non-doped second polycrystalline silicon film on at least the top surface of the first polycrystalline silicon film. a step of forming a first capacitor electrode having a polycrystalline silicon film; a step of depositing a silicon nitride film on the entire surface; and a step of forming an oxide layer on the surface of the silicon nitride film by thermal oxidation; forming a conductor film on the entire surface; forming a second capacitor electrode.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. 1 to 3 are cross-sectional views of the first embodiment of the present invention in order of steps for explaining the manufacturing method thereof.

First, as shown in FIG. 1, an element isolation oxide film 102 with a thickness of about 500 nm is formed on the surface of a p-type silicon substrate 101 by a conventional method, and then a gate oxide film with a thickness of about 25 nm is formed in the element formation region. 103 is formed by thermal oxidation. A non-doped polycrystalline silicon film with a thickness of about 400 nm is deposited over the entire surface, phosphorus is thermally diffused as an impurity, and then patterned to form the gate electrode 104. Next, arsenic ions are implanted into the entire surface under the conditions of 100 keV and 5 x 1015 cm-2, and the n+ diffusion layers 105a, 1
Form 05b. Next, a first film with a thickness of about 300 nm is formed.
A silicon oxide film 106 is deposited on the entire surface by CVD, and then a first contact hole 10 is formed that reaches the n+ diffusion layer 105a.
Open 7. Next, a non-doped first polycrystalline silicon film is deposited again to a thickness of about 600 nm on the entire surface, and phosphorus is thermally diffused to convert the non-doped first polycrystalline silicon film into an n+ type first polycrystalline silicon film 108. do. Remove PSG generated on the surface. Subsequently, a non-doped second polycrystalline silicon film 150 is deposited thinly (20 nm thick) over the entire surface.

Next, as shown in FIG. 2, the second polycrystalline silicon film 150 and the first polycrystalline silicon film 108 are simultaneously patterned to form a first capacitor electrode (storage electrode) 109.
After forming the silicon nitride film 111, a silicon nitride film 111 with a thickness of about 12 nm is deposited over the entire surface by low pressure CVD, and thermal oxidation is performed to grow an oxide layer 112 with a thickness of about 2 nm on the surface of the silicon nitride film 111. At this time, the first capacitor electrode (storage electrode) 109
Phosphorus contained in the first polycrystalline silicon film 108 diffuses into the non-doped second polycrystalline silicon film 150, which is converted into an n+ type second polycrystalline silicon film 151. As a result, the first capacitor electrode (storage electrode) 109 is entirely composed of an n+ type polycrystalline silicon film. Thereafter, a third non-doped polycrystalline silicon film with a thickness of approximately 200 nm is deposited over the entire surface, phosphorus is thermally diffused, and patterned to cover the first capacitor electrode (storage electrode) 109, forming a second capacitor. Electrodes 113 are formed. During this patterning, the oxide layer 112 and silicon nitride film 111 immediately below the third polycrystalline silicon film to be patterned are also removed at the same time.

Next, as shown in FIG.
Second silicon oxide film 1 as an interlayer insulating film with a thickness of about 0 nm
After forming a second contact hole 115 reaching the n+ diffusion layer 105b, an Al film is deposited and patterned to form a digit line 116.

In this embodiment, the silicon nitride film 111 is deposited by the same method as in the conventional method, but at this stage, a non-doped second polycrystalline silicon film 150 is deposited on the upper surface of the first capacitor electrode (storage electrode) 109. Therefore, even if residual oxygen exists during deposition, the surface of the non-doped second polycrystalline silicon film 150 is unlikely to be oxidized, and the capacitor insulating film can be made thinner.

FIGS. 4 to 6 show a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the order of steps for explaining the manufacturing method.

First, as shown in FIG. 4, after patterning the n+ type first polycrystalline silicon film 108 as in the conventional technique, a non-doped second polycrystalline silicon film 150 is formed over the entire surface. It is deposited and patterned to cover the pattern of the first polycrystalline silicon film 108.

Next, as shown in FIG. 5, a film with a thickness of 12
A silicon nitride film 111 with a thickness of approximately 2 nm is deposited, and thermal oxidation is performed to grow an oxide layer 112 of approximately 2 nm on the surface of the silicon nitride film 111. Through this thermal oxidation, the non-doped second polycrystalline silicon film 150 is
is converted into an n+ type second polycrystalline silicon film 151,
An n+ type first capacitor electrode (storage electrode) 109 is obtained. Next, a third non-doped polycrystalline silicon film with a thickness of about 200 nm is deposited over the entire surface, phosphorus is thermally diffused, and patterned to cover the first capacitor electrode (storage electrode) 109. A capacitor electrode 113 is formed. During this patterning, the oxide layer 112 and silicon nitride film 111 immediately below the third polycrystalline silicon film to be patterned are also removed at the same time.

Next, as shown in FIG.
Second silicon oxide film 1 as an interlayer insulating film with a thickness of about 0 nm
After forming a second contact hole 115 reaching the n+ diffusion layer 105b, an Al film is deposited and patterned to form a digit line 116.

In this embodiment, in comparison with the first embodiment,
Since the second polycrystalline silicon film 151 is also formed on the side surface of the first capacitor electrode (storage electrode) 109, the area where the capacitor insulating film can be made thinner is increased compared to the first embodiment, and the capacitor capacitance is increased. Can be made larger.

[0020]

As explained above, in the present invention, there is a second polycrystalline silicon film that covers at least the upper surface of the first capacitor electrode (storage electrode), and this second polycrystalline silicon film serves as a capacitive insulator. Since the film is not doped until it is deposited, a natural oxide film is difficult to form on at least the upper surface of the first capacitor electrode (storage electrode). Therefore, the capacitive insulating film can be made thinner, the capacitor capacitance can be increased, and when used as a capacitor in a DRAM cell, a DRAM with a wide circuit operation margin and high resistance to alpha rays can be realized.

Furthermore, in the present invention, since the first polycrystalline silicon film is made into n+ type and the PSG film formed on the surface is removed before the second polycrystalline silicon film is formed, the removal of the PSG film is easy. At this time, the unevenness formed on the surface of the first polycrystalline silicon film is alleviated by the deposition of the second polycrystalline silicon film. As a result, electric field concentration between the first capacitor electrode (storage electrode) and the second capacitor electrode is alleviated, and the long-term reliability of the capacitor insulating film is improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining a first embodiment of the present invention.

FIG. 3 is a sectional view for explaining the first embodiment of the present invention.

FIG. 4 is a sectional view for explaining a second embodiment of the present invention.

FIG. 5 is a sectional view for explaining a second embodiment of the present invention.

FIG. 6 is a sectional view for explaining a second embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a conventional technique.

FIG. 8 is a cross-sectional view for explaining a conventional technique.

FIG. 9 is a cross-sectional view for explaining a conventional technique.

[Explanation of symbols]

101, 201 p-type silicon substrate 102, 20
2 Element isolation oxide film 103, 203 Gate oxide film 104, 204 Gate electrode 105a, 105b, 205a, 205b n+
Diffusion layer 106, 206 First silicon oxide film 107, 2
07 First contact hole 108, 208
First polycrystalline silicon film 109, 209 first
Capacitance electrode (storage electrode) 110, 210 Natural oxide film 111, 211 Silicon nitride film 112, 212
Oxide layer 113, 213 Second capacitor electrode 114, 214
Second silicon oxide film 115, 215 Second contact hole 116, 216 Digit line

Claims (4)

[Claims] 1. A first capacitor electrode formed of a first polycrystalline silicon film containing impurities connected to a semiconductor substrate, a silicon nitride film covering the first capacitor electrode, and a surface of the silicon nitride film. In a semiconductor device having a capacitor including a capacitor insulating film formed by the oxide layer of silicon nitride covering the oxide layer, and a second capacitor electrode formed by the conductor film covering the surface of the oxide layer, the first capacitor An electrode is connected to the first polycrystalline silicon film and the first polycrystalline silicon film.
a second polycrystalline silicon film covering an upper surface of the polycrystalline silicon film. 2. A first capacitor electrode formed of a first polycrystalline silicon film containing impurities connected to a semiconductor substrate, a silicon nitride film covering the first capacitor electrode, and a surface of the silicon nitride film. In a semiconductor device having a capacitor including a capacitor insulating film formed by the silicon nitride oxide layer covering the oxide layer, and a second capacitor electrode formed by the conductor film covering the surface of the oxide layer, the first capacitor An electrode is connected to the first polycrystalline silicon film and the first polycrystalline silicon film.
a second polycrystalline silicon film covering the surface of the polycrystalline silicon film. 3. A MOS transistor having a diffusion layer of an opposite conductivity type is formed on a semiconductor substrate of one conductivity type, an interlayer insulating film is deposited on the entire surface, and a contact hole for connecting a capacitor reaching the diffusion layer is formed between the layers. a step of opening an insulating film;
A first polycrystalline silicon film of opposite conductivity type is formed on the entire surface, a non-doped second polycrystalline silicon film is formed on the entire surface, and the second polycrystalline silicon film and the first polycrystalline silicon film are separated. a step of forming a first capacitor electrode by etching, a step of depositing a silicon nitride film on the entire surface and forming an oxide layer on the surface of the silicon nitride film by thermal oxidation, and forming a conductor film on the entire surface, A method of manufacturing a semiconductor device, comprising the step of forming a second capacitor electrode. 4. A MOS transistor having a diffusion layer of an opposite conductivity type is formed on a semiconductor substrate of one conductivity type, an interlayer insulating film is deposited on the entire surface, and a contact hole for connecting a capacitor reaching the diffusion layer is formed between the layers. a step of opening an insulating film;
A first polycrystalline silicon film of opposite conductivity type is formed on the entire surface, the first polycrystalline silicon film is etched to form a first capacitor electrode, and a non-doped silicon film is formed on the surface of the first capacitor electrode. a step of forming a second polycrystalline silicon film; a step of depositing a silicon nitride film on the entire surface and forming an oxide layer on the surface of the silicon nitride film by thermal oxidation; 1. A method of manufacturing a semiconductor device, comprising: forming a capacitor electrode.