JPH05102417A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To provide a structure and a manufacturing method for enlarging a capacitor surface area and increasing the capacity thereof without enlarging a cell area regarding a capacitor part of a semiconductor device with a stacked capacitor. CONSTITUTION:A polysilicon layer (dummy polysilicon layer) 13 is provided on a layer insulating film 5, a contact hole is formed therein and a capacitor lower electrode 7 and a capacitor dielectric film 8 are formed ranging from a part facing the contact hole to the upper surface of the dummy polysilicon layer 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a stacked capacitor and a structure centering around the capacitor portion and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, DRAM (Dynamic Ra)
A stacked capacitor structure is one of the memory cells of the mdom access memory). The structure is shown in FIG. 3, and the steps involved in the present invention will be described below.

As shown in FIG. 3, a field oxide film 2 and a word line (gate electrode) are formed on a P-type (100) silicon substrate 1.
In the structure in which the (first polysilicon) 3, the N ⁺ diffusion layer 4 and the insulating film 5 are formed, the insulating film 5 is selectively etched by using ordinary photolithography and etching techniques, and after removing the resist, 6 An opening for contact is provided as shown in. Then, a second Poly-Si (polysilicon) (hereinafter sometimes abbreviated as 2P) 7 is formed on the entire surface at 1000 to 3000 Å
CVD method (Chemical Vapor Depos)
and the chemical vapor deposition method).
Next, As ⁺ or P ^{+ is} added to the second Poly-Si7.
About 5E15 cm ^{-2 by} ion implantation or POCl
_{Using 3} as a diffusion source, phosphorus is diffused and impurities are introduced to make it conductive. Next, the second Poly-Si 7 is selectively etched by using ordinary photolithography and etching techniques, and then the resist is removed. Then, using a CVD method, a silicon nitride film (Si
₃ N ₄ ) 8 is grown on the entire surface of about 50 to 200 Å. Then, annealing is performed in an oxygen atmosphere to grow a thin oxide film on the silicon nitride film 8 (not shown). Next, the third Poly-Si (hereinafter sometimes abbreviated as 3P) 9 is CVed on the entire surface.
1000 ~ 3000Å growth by D method,
The POLY ₃ is used as a diffusion source in the poly-Si 9 so that phosphorus is diffused to make it electrically conductive. Next, this third Poly-Si 9 is selectively etched by using ordinary photolithography and etching techniques. At the time of this etching, the thin oxide film and the silicon nitride film 8 under the third Poly-Si 9 in the portion to be etched are also etched.

Through the above steps, the second Poly-Si7,
A capacitor is formed with the third Poly-Si 9 and the thin oxide film sandwiched between the third Poly-Si 9 and the silicon nitride film 8 as constituent elements.

[0005]

However, in order to increase the degree of integration in the above manufacturing method, the cell area must be reduced. When the area is reduced, the capacitance of the capacitor is reduced, which causes a malfunction of the circuit and a soft error. As a method of increasing the capacitance of the capacitor, there is a method of thinning the insulating film, but it has a drawback that it causes insulation failure between the upper and lower capacitor electrodes of polysilicon (2P-3P), and eventually lowers the yield. There is also a method of using an insulating film having a high dielectric constant, which is an alternative to SiO ₂ or Si ₃ N ₄ , but there is no material or process that can be put to practical use. For example, Ta as a high dielectric material
There is ₂ O _5, but it is still unstable in the process.

The present invention reduces the capacitor area in order to increase the degree of integration as described above, and thus prevents the malfunctions of the circuit and the soft error, thereby preventing the capacitor capacitance without increasing the cell area. The purpose is to provide a structure and manufacturing method that can increase

[0007]

For the above-mentioned purpose, the present invention has a structure in which a dummy Poly-Si layer (described later) is formed in a method of manufacturing a semiconductor device, particularly in forming a capacitor insulating film of a stacked capacitor structure of DRAM. And then
When the contact is opened, the interlayer film under the second Poly-Si (lower electrode of the capacitor) is subjected to etching using wet etching so as to dramatically increase the capacitor area.

[0008]

In the present invention, as described above, the dummy Poly-S is used.
Since the structure having i is provided to secure a large surface area, it is possible to increase the capacitance of the capacitor without increasing the cell area.

[0009]

2 (a) to 2 (f) are sectional views showing a manufacturing process of an embodiment of the present invention, in which only steps related to the present invention are described and the preceding and following steps are omitted. Further, the same reference numerals are given to the parts having the same functions as those in FIG. First, on the P-type silicon substrate 1, the field oxide film 2 and the word line (gate electrode) are formed on the P-type silicon substrate 1 in the same manner as in the past.
3. An N ⁺ diffusion layer 4 serving as a source and a drain is formed, and an interlayer SiO ₂ 5 is formed by a CVD method at about 1000 to 5000 Å (FIG. 2A).

Next, as shown in FIG. 2B, Poly-Si is used.
13 is grown by the low pressure CVD method to about 1000 to 3000 Å. This is referred to as a dummy Poly-Si layer in this section. Next, in order to form a contact hole, a resist 15 is formed.
Is applied and patterned to form the dummy Poly-Si.
Layer 13 is patterned using conventional photolithography and etching techniques.

Next, as shown in FIG. 2 (c), the above-mentioned Poly
Using the resist 15 used for the etching of Si13 as it is as a mask for contact etching, wet SiO ₂ isotropic etching is applied to the interlayer SiO ₂ 5 by using a hydrofluoric acid solution at about 2000 Å.

Next, the remaining interlayer SiO ₂ 5 is etched by dry etching (anisotropic etching) to open a contact. After that, the resist 15 is removed to obtain a structure as shown in FIG. That is, the interlayer film 5 in the contact opening is undercut below the opening in the Poly-Si film 13.

Next, as shown in FIG. 2E, the second Poly-
Si is formed on the entire surface by a CVD method at about 1000 to 3000Å. Then, impurities of As ⁺ or P ⁺ of about 5E15 cm ⁻² are introduced into the second Poly-Si 7 by an ion implantation method. After that, in an N ₂ atmosphere at about 850 ° C., 30
By annealing for a while, activation of impurities is promoted. Next, patterning is performed using ordinary photolithography and etching techniques. At this time, the portion of the dummy Poly-Si layer 13 that is to be etched is also removed by etching. Therefore, the structure as shown in FIG.

Next, as shown in FIG. 2 (f), a silicon nitride film 8 which is a dielectric film for capacitors is formed by low pressure CVD.
Deposit 0 to 200Å. Then, annealing is performed in an oxidizing atmosphere to grow a thin oxide film on the silicon nitride film 8 (not shown). Next, the third Poly-Si 9 is added to 200
About 0 to 3000 Å (until the step of the contact part is covered) is deposited by the low pressure CVD method, and phosphorus is added at 5 × 10 ²⁰ c
Doping is performed at a concentration of about m ⁻³ , and patterning is performed by the same method as for the second Poly-Si 7 to obtain a structure as shown in FIG. Thereafter, an interlayer SiO ₂ (II) 10 (refer to FIG. 1 for the following symbols) is deposited in the same manner as in the prior art, the bit contact 11 is opened by using a normal photolithography and etching technique, and the bit line 12 is patterned to form the structure shown in FIG. To obtain the structure shown. That is, since the dummy Poly-Si layer 13 is provided, the interlayer film 5 facing the contact hole has an undercut shape as described above, and the side surface facing the contact hole of the dummy Poly-Si 13 from the surface of that portion. Then, the structure is such that a capacitor can be formed up to the upper surface. That is, the capacitor area can be increased in a three-dimensional manner without increasing the cell area. Thereafter, the semiconductor memory device having the stacked capacitor structure according to the present embodiment is completed by a normal process technique.

[0015]

As described above, according to the present invention, a dummy Poly-Si layer is provided and 2P (second Pol) is provided.
In addition to the y-Si layer, that is, the upper surface of the capacitor lower electrode) and the 2P side surface, a large surface area is secured not only on the lower surface around the 2P and on the 2P upper surface of the interlayer SiO ₂ (I) 5 part by wet etching, and the dielectric film for the capacitor Since the silicon nitride film is formed, it is possible to increase the capacitance of the capacitor without increasing the cell area,
This can be expected to reduce circuit malfunctions and soft errors as compared to conventional semiconductor devices. Further, since no complicated process is required, it can be expected that the workability is almost the same as the conventional one.

[Brief description of drawings]

FIG. 1 is a structure of an embodiment of the present invention.

FIG. 2 is a manufacturing process of an embodiment of the present invention.

FIG. 3 Conventional example

[Explanation of symbols]

5 Interlayer SiO ₂ (I) 6 Contact 7 Second Poly-Si 8 Si ₃ N ₄ (Nitride film) 9 Third Poly-Si 13 Poly-Si

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having a stacked capacitor structure, comprising: (a) forming at least a layer to be a gate electrode of a transistor and a diffusion layer to be a source and a drain on a semiconductor substrate; and (b) Forming an interlayer insulating film on the structure and then forming a polysilicon layer on the interlayer insulating film; (c) forming contact holes in the polysilicon layer on the diffusion layer and the interlayer insulating film; (D) forming a layer to be a capacitor lower electrode from a portion facing the opened contact hole to an upper surface of the polysilicon layer, and patterning the polysilicon layer and the capacitor lower electrode layer; (E) at least including a step of forming a capacitor dielectric film on the capacitor lower electrode layer and forming a capacitor upper electrode layer thereon. The method of manufacturing a semiconductor device, characterized in that. 2. As a structure of a capacitor portion of a semiconductor device having a stacked capacitor structure, an interlayer insulating film formed on a semiconductor substrate and a polysilicon layer formed on the interlayer insulating film are formed on the semiconductor substrate. A contact hole is formed on the diffusion layer, and the capacitor lower electrode and the capacitor dielectric film are formed at least from the portion facing the contact hole to the upper surface of the polysilicon layer. Characteristic semiconductor device.