JPH0945767A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To povide a semiconductor integrated circuit device with highly reliable wiring layers and applicable of fine processings thereto, and provide a manufacturing technique capable of the easy manufacturing the same. SOLUTION: A manufacturing method has a process for forming an etching- stop film 10 comprising an insulation film on a substrate 9 with a plurality of formed semiconductor elements and thereafter forming a lower layer wiring layer 11 with no dog bone in a selected region present on the etching-stopper film 10, a process for forming an interlayer insulation film 12 on both the etching-stopper film 10 and the wiring layer 11 and thereafter forming a through hole 15 in the selected region of the interlayer insulation film 12 to expose the surface of the wiring layer 11 in the selected region to the outside, and a process for forming an upper wiring layer 16 on the interlayer insulation film 12 with the formed through hole 15 to connect electrically the upper layer wiring layer 16 and the lower layer wiring layer 11 through the through hole 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a wiring structure requiring fine processing.

[0002]

2. Description of the Related Art In semiconductor integrated circuit devices, high integration and fine processing have been promoted, and accordingly, the wiring structure has become fine, and a highly reliable wiring structure is required.

In the wiring structure of the semiconductor integrated circuit device studied by the present inventor, the lower wiring layer and the upper wiring layer are electrically connected to each other through through holes in selective regions of the interlayer insulating film.

A wide area called a dogbone, which is larger than the line width of the lower wiring layer, is provided in the lower wiring layer area below the through hole. This dogbone is a wiring region having a line width larger than the line width of the lower wiring layer in consideration of the alignment accuracy between the formation region of the through hole and the lower wiring layer in the manufacturing process of the through hole. It functions as an etching stopper film for preventing the insulating film under the lower wiring layer from being etched during the selective etching of the interlayer insulating film forming the through hole.

As a document describing the technique for forming a wiring layer in a semiconductor integrated circuit device, for example, Press Journal Co., Ltd., November 2, 1989, “'90 latest semiconductor process technology” p267 to p273.
Are listed in.

[0006]

However, the present inventor has found that the semiconductor integrated circuit device having the above-mentioned wiring layer has various problems.

That is, since it is necessary to provide a wide area called a dogbone, which is larger than the line width of the lower wiring layer, in the through hole region of the lower wiring layer, the line width of the lower wiring layer becomes lower. Since it becomes larger due to the dog bone in a plurality of regions of the wiring layer, this is a problem for reducing the line width of the lower wiring layer.

Further, since the lower wiring layer adjacent to the lower wiring layer provided with the dog bone is arranged corresponding to the dog bone, the linearity of the adjacent lower wiring layer is disturbed. In addition to the need to form a lower wiring layer having dogbones in a plurality of regions, problems occur in high reliability and fine processing of the lower wiring layer, and the wiring design becomes complicated. There is a problem that becomes.

An object of the present invention is to provide a semiconductor integrated circuit device having a wiring layer with high reliability and capable of fine processing.

Another object of the present invention is to provide a manufacturing technique capable of easily manufacturing a semiconductor integrated circuit device having a wiring layer having high reliability and capable of fine processing.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The typical ones of the inventions disclosed in the present invention will be outlined below.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, after forming an insulating film as an etching stopper film on a substrate on which a plurality of semiconductor elements are formed, a selective region on the etching stopper film is formed. In the process of forming a lower wiring layer without a dogbone, and after forming an interlayer insulating film on the etching stopper film and the lower wiring layer, a through hole is formed in a selective region of the interlayer insulating film, and the lower layer is formed. The step of exposing the surface of the selective region of the wiring layer, the upper wiring layer is formed on the interlayer insulating film in which the through hole is formed, and the upper wiring layer and the lower wiring layer are electrically connected through the through hole. And a step of connecting.

[0014]

According to the method of manufacturing a semiconductor integrated circuit device of the present invention described above, after the etching stopper film is formed, the step of forming the lower wiring layer having no dog bone, and the step of forming the interlayer insulating film, After forming a through hole in a selective region of the interlayer insulating film, an upper wiring layer is formed,
By including the step of electrically connecting the upper wiring layer and the lower wiring layer through the through holes, even if the lower wiring layer without the dog bone is applied, the through holes can be selectively connected to the interlayer insulating film. Since the etching stopper film is formed when the region is formed by etching, the etching stopper film and the insulating film thereunder can be prevented from being etched by the etching.

As a result, since it is not necessary to provide a dog bone in the lower wiring layer, the line width of the lower wiring layer can be reduced and linearity can be provided, so that the distance to the adjacent lower wiring layer is also shortened. In addition, adjacent lower wiring layers can be linearly arranged.

Therefore, the lower wiring layer can be finely processed and arranged at a high density.

That is, since it is not necessary to form a wide area called a dogbone larger than the line width of the lower wiring layer in the through hole region of the lower wiring layer, the line width of the lower wiring layer is reduced. Since the dog bone does not increase the size, the line width of the lower wiring layer can be reduced and linearity can be provided.

Further, since the lower wiring layer adjacent to the lower wiring layer has no dogbone, the adjacent lower wiring layer can have linearity and can be arranged close to each other. The reliability and fine processing can be achieved, and the wiring design can be simplified.

As a result, a semiconductor integrated circuit device having a wiring layer having a high reliability and capable of fine processing can be easily manufactured by adopting a manufacturing process of forming an etching stopper film.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and a duplicate description will be omitted.

(Embodiment 1) FIGS. 1 to 7 are sectional views showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention will be specifically described with reference to FIG.

First, as shown in FIG. 1, a field insulating film made of a silicon oxide film is formed by using a thermal oxidation process on an element isolation region which is a selective region on the surface of a semiconductor substrate 1 made of, for example, p-type silicon single crystal. The film 2 is formed. Although not shown, a channel stopper film for preventing inversion is formed under the field insulating film 2.

Next, as shown in FIG. 2, a gate insulating film 3 made of silicon oxide is formed in the active region surrounded by the field insulating film 2, and a gate made of polycrystalline silicon is formed on the gate insulating film 3. The electrode 4 is formed. The gate electrode 4 is formed by sequentially depositing an insulating film 5 made of a polycrystalline silicon film and a silicon oxide film on the semiconductor substrate 1 and etching these sequentially. Then, the gate electrode 4
Side wall insulating film 6 made of silicon oxide on the side wall of
To form

Next, n such as phosphorus (P) is formed on the semiconductor substrate 1.
Type impurities are ion-implanted to form an n-type semiconductor region 7 serving as a source and a drain.

Next, as shown in FIG. 3, an insulating film 8 is formed on the semiconductor substrate 1. The insulating film 8 is, for example, CVD.
A silicon oxide film or the like formed by the (Chemical Vapor Deposition) method can be used.

In the manufacturing process of the semiconductor integrated circuit device described above, the n-channel MOSFET is formed on the semiconductor substrate 1, but the n-channel MOSFET is formed on the semiconductor substrate 1.
It is possible to adopt a mode in which various semiconductor elements such as p-channel MOSFETs, bipolar transistors, and capacitive elements other than the above are formed.

The manufacturing process of the semiconductor integrated circuit device described above can be performed by combining various prior arts. A main part of the semiconductor integrated circuit device and the manufacturing method thereof according to the present invention is to form a wiring layer in the multilayer wiring / wiring structure of the semiconductor integrated circuit device. In view of this, in order to simplify future illustration, a semiconductor substrate 1 formed by the above-described manufacturing process and an n-channel MOSFET formed as a starting material is comprehensively illustrated as a substrate 9 and has an internal structure. The internal structure of the base body 9 having the above is omitted and the dimensions shown in the drawing are reduced.

Next, as shown in FIG. 4, an etching stopper film 10 made of an insulating film is formed on the surface of the insulating film 8 formed on the substrate 9.

The etching stopper film 10 is made of a material which is not etched by the selective etching when a through hole is formed in the insulating film which is an interlayer insulating film formed on the etching stopper film 10 by the selective etching technique. Is.

In this embodiment, the etching stopper film 10 is, for example, a silicon nitride film formed by the CVD method.

Next, the first wiring layer 11 is formed on the surface of the etching stopper film 10. First wiring layer 11
For example, an aluminum layer is formed by a sputtering method. As a material of the wiring layer 11, a high melting point metal such as a titanium nitride (TiN) layer as a lower layer or an upper layer of the aluminum layer as the wiring layer 11 in order to secure the characteristics of stress migration resistance and electromigration resistance. A wiring layer in which a wiring structure is laminated using layers can be used. Further, as the wiring layer 11, a combination of a polycrystalline silicon layer or a combination of a polycrystalline silicon layer and a refractory silicide layer having electrical conductivity can be used.

The wiring layer 11 includes a wiring layer electrically connected through a through hole provided in the insulating film 8 in a region (not shown), and is electrically connected to the n-type semiconductor region 7. It also includes the wiring layers to be connected.

Next, the first wiring layer 11 is patterned by using the photolithography technique and the selective etching technique.

In this case, since the etching stopper film 10 is formed, it is not necessary to provide the wiring layer 11 with a wide area called a dogbone, as will be apparent from the process described later.

As a result, since it is not necessary to provide a dog bone in the wiring layer 11, the line width of the wiring layer 11 can be reduced and linearity can be provided, so that the distance to the adjacent wiring layer 11 is also shortened. Wiring layer 11 that can be formed and is adjacent to
Can also be arranged in a straight line.

Therefore, the wiring layer 11 can be finely processed and arranged at a high density.

In other words, since it is not necessary to form a wide area called a dogbone, which is larger than the line width of the wiring layer 11, in the through hole region described later in the wiring layer 11, the wiring of the wiring layer 11 is not formed. Since the width does not increase due to the dog bone, the line width of the wiring layer 11 can be reduced and linearity can be provided.

The wiring layer 11 adjacent to the wiring layer 11
Is the adjacent wiring layer 1 due to the absence of dog bones.
Since 1 can have linearity and can be arranged close to each other, the wiring layer 11 can have high reliability and fine processing, and the wiring design can be simplified.

As a result, the wiring layer 11 having high reliability and capable of fine processing can be obtained.

Next, as shown in FIG. 5, a first interlayer insulating film 12 is formed on the entire surface so as to cover the first wiring layer 11. The interlayer insulating film 12 is formed by, for example, forming a silicon oxide film by a CVD method, and then forming an SOG (Spin On Glass) film by using a spin coating device such as a spinner for planarizing the surface. The interlayer insulating film 12 is
For example, after forming a silicon oxide film by the CVD method, P
SG (Phospho Silicate Glass) film or BPSG (Bo
Various forms such as an interlayer insulating film having a laminated structure in which a ro Phospho Silicate Glass film or the like is formed by a CVD method can be used.

Next, an etching stopper film 13 is formed on the surface of the first interlayer insulating film 12.

The etching stopper film 13 is made of a material which is not etched by the selective etching when a through hole is formed in the insulating film which is an interlayer insulating film formed on the etching stopper film 13 by the selective etching technique. Is.

In this embodiment, the etching stopper film 13 is similar to the above-mentioned etching stopper film 10, and for example, a silicon nitride film is formed by the CVD method.

Next, as shown in FIG. 6, a photoresist film 14 serving as an etching mask when forming a through hole is formed on the surface of the etching stopper film 13, and then, for example, silicon nitride is formed by using a selective etching technique. After selectively etching the etching stopper film 13 made of a film or the like, the through hole 15 is formed by selectively etching the interlayer insulating film 12 made of, for example, a silicon oxide film by using another selective etching technique.

In this case, when the through hole 15 is formed in the interlayer insulating film 12 made of, for example, a silicon oxide film, the etching stopper film 10 made of a material different from that of the interlayer insulating film 12, for example, a silicon nitride film is formed. The etching stopper film 1
Since 0 is not etched by the selective etching step when forming the through hole 15, it is possible to prevent the insulating film 8 below the etching stopper film 10 from being etched.

Therefore, even when the misalignment between the through hole 15 and the wiring layer 11 in the photolithography technique occurs, like the through hole 15 shown on the left side of FIG. 6, the etching stopper film 10 is formed. The presence of the etching stopper film 10
Since it is not etched by the selective etching process when forming the through hole 15, it is possible to prevent the insulating film 8 below the etching stopper film 10 from being etched.

The through hole 15 shown on the right side of FIG.
As described above, when the misalignment between the through hole 15 and the wiring layer 11 in the photolithography technique does not occur, the wiring layer 11 functions as an etching stopper film, so that the wiring layer 11 forms the through hole 15. Since it is not etched by the selective etching process at that time, it is possible to prevent the insulating film 8 below the etching stopper film 10 from being etched.

Next, as shown in FIG. 7, after removing the unnecessary photoresist film 14, the through hole 15 is removed.
A second wiring layer 16 is formed on the interlayer insulating film 12 and the etching stopper film 13. Wiring layer 16
For example, an aluminum layer is formed by a sputtering method. The second wiring layer 16 may have various modes such as a wiring layer having a laminated structure made of the same material as the first wiring layer 11 described above.

In this case, since the wiring layer 16 is formed by being embedded in the through hole 15 in the manufacturing process of the second wiring layer 16, the wiring layer 16 which is the upper wiring layer passes through the through hole 15. It is electrically connected to the wiring layer 11, which is a lower wiring layer.

Therefore, when the misalignment between the through hole 15 and the wiring layer 11 occurs, as in the through hole 15 shown on the left side of FIG. 6, the upper surface and the side surface of the wiring layer 11 which is the lower wiring layer. Since the wiring layer 16 which is the upper wiring layer is brought into contact with each other, it is possible to reliably electrically connect them with a wide contact area.

The through hole 15 shown on the right side of FIG.
As described above, when the misalignment between the through hole 15 and the wiring layer 11 does not occur, the upper surface of the wiring layer 11 which is the lower wiring layer has the upper surface of the wiring layer 16 which is the upper wiring layer.
Since they are in contact with each other, they can be reliably electrically connected with a large contact area.

Next, an unnecessary region of the wiring layer 16 is selectively removed by using the photolithography technique and the selective etching technique to form a pattern on the second wiring layer 16.

In this case, since the etching stopper film 13 is formed when the through hole is formed in the interlayer insulating film after the interlayer insulating film is formed on the wiring layer 16, the above-mentioned first layer is formed. Like the wiring layer 11, the wiring layer 16 does not need to have a wide area called a dog bone.

As a result, since it is not necessary to provide a dog bone in the wiring layer 16, the line width of the wiring layer 16 can be reduced and linearity can be provided, so that the distance to the adjacent wiring layer 16 is also shortened. Wiring layer 16 that can be formed and is adjacent to
Can also be arranged in a straight line.

Therefore, the wiring layer 16 can be finely processed and arranged at a high density.

That is, since it is not necessary to form a wide area called a dog bone larger than the line width of the wiring layer 16 in the through hole region of the wiring layer 16, the line width of the wiring layer 16 is reduced. Since the dog bone does not increase the width, the line width of the wiring layer 16 can be reduced and the linearity can be provided.

The wiring layer 16 adjacent to the wiring layer 16
Is the adjacent wiring layer 1 due to the absence of dog bones.
Since 6 can have linearity and can be arranged close to each other, the wiring layer 16 can be highly reliable and finely processed, and the wiring design can be simplified.

As a result, the wiring layer 16 having high reliability and capable of fine processing can be obtained.

Next, although not shown, an interlayer insulating film and a wiring layer are laminated on the substrate 9, and then a surface protective film is formed to complete the manufacturing process of the semiconductor integrated circuit device.

According to the method of manufacturing a semiconductor integrated circuit device of the present embodiment described above, after forming the etching stopper film 10, the lower wiring layer 11 having no dog bone is formed.
And the step of forming the interlayer insulating film 12, the through holes 15 are formed in the selective regions of the interlayer insulating film 12, the upper wiring layer 16 is formed, and the upper wiring layer 16 and the lower wiring layer 16 are formed. Since the wiring layer 11 and the wiring layer 11 are electrically connected to each other through the through hole 15, the through hole 15 is selected as the interlayer insulating film 12 even if the lower wiring layer 11 having no dog bone is applied. Etching stopper film 1 when forming a specific region by etching
Since 0 is formed, it is possible to prevent the insulating film 8 below the etching stopper film 10 from being etched by the etching.

As a result, since it is not necessary to provide a dogbone in the lower wiring layer 11, the line width of the wiring layer 11 can be reduced and linearity can be provided, so that the distance from the adjacent wiring layer 11 can be increased. And the adjacent wiring layers 11 can be arranged linearly.

Therefore, the wiring layer 11 can be finely processed and arranged at a high density.

That is, since it is not necessary to form a wide area called a dog bone, which is larger than the line width of the wiring layer 11, in the area of the through hole 15 in the lower wiring layer 11, Since the line width does not increase due to the dog bone, the line width of the wiring layer 11 can be reduced and linearity can be provided.

Further, since the wiring layer 11 adjacent to the lower wiring layer 11 has no dog bone, the adjacent wiring layer 11 can have linearity and can be arranged close to each other. High reliability and fine processing can be achieved, and the wiring design can be simplified.

As a result, it is possible to easily manufacture a semiconductor integrated circuit device having a wiring layer with high reliability and capable of fine processing by adopting the manufacturing process of forming the etching stopper film 10.

(Embodiment 2) FIGS. 8 to 10 are sectional views showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

The manufacturing process of the semiconductor integrated circuit device of this embodiment is different from the manufacturing process of the multi-layered wiring layer in the manufacturing process of the semiconductor integrated circuit device of the first embodiment described above, and the other processes are described above. The description is omitted because it is the same as the first embodiment.

First, as shown in FIG. 8, the first wiring layer 11 is formed on the surface of the substrate 9. First wiring layer 11
For example, an aluminum layer is formed by a sputtering method. As the material of the wiring layer 11, various wiring materials may be used similarly to the wiring layer 11 of the first embodiment described above.

Next, the first wiring layer 11 is patterned by using the photolithography technique and the selective etching technique.

In this case, by forming the etching stopper film 10, it is not necessary to provide the wiring layer 11 with a wide area called a dog bone, as will be apparent from the process described later.

Next, the etching stopper film 10 made of an insulating film is formed on the substrate 9 including the wiring layer 11.

The etching stopper film 10 is made of a material which is not etched by the selective etching when a through hole is formed in the insulating film which is an interlayer insulating film formed on the etching stopper film 10 by the selective etching technique. Is.

In this embodiment, the etching stopper film 10 is, for example, a silicon nitride film formed by the CVD method.

Next, the first interlayer insulating film 12 is formed on the surface of the etching stopper film 10. Interlayer insulating film 12
Can be formed using the same material as the interlayer insulating film 12 of the first embodiment described above.

Next, as shown in FIG. 9, the interlayer insulating film 12 is formed.
After forming a photoresist film 14 serving as an etching mask when forming a through hole on the surface of the through hole, the interlayer insulating film 12 made of, for example, a silicon oxide film is selectively etched using a selective etching technique to form the through hole. Form 15.

In this case, when the through hole 15 is formed in the interlayer insulating film 12 made of, eg, a silicon oxide film, the etching stopper film 10 made of a material different from that of the interlayer insulating film 12, eg, a silicon nitride film is formed. The etching stopper film 1
Since 0 is not etched by the selective etching step when forming the through hole 15, it is possible to prevent the insulating film 8 below the etching stopper film 10 from being etched.

Therefore, even when the misalignment between the through hole 15 and the wiring layer 11 in the photolithography technique occurs, like the through hole 15 shown on the left side of FIG. 9, the etching stopper film 10 is formed. The presence of the etching stopper film 10
Since it is not etched by the selective etching process when forming the through hole 15, it is possible to prevent the insulating film 8 below the etching stopper film 10 from being etched.

Next, as shown in FIG. 10, the interlayer insulating film 1
The etching stopper film 10 whose surface is exposed by the second through hole 15 is selectively etched and removed using a selective etching technique, and the wiring layer 11 in that region is removed.
Expose the surface of.

Next, the photoresist film 14 that has become unnecessary
After removing, the second wiring layer 16 is formed on the interlayer insulating film 11 having the through holes 15. Wiring layer 16
For example, an aluminum layer is formed by a sputtering method. The second wiring layer 16 may have various modes such as a wiring layer having a laminated structure made of the same material as the first wiring layer 11 described above.

In this case, since the wiring layer 16 is formed by being embedded in the through hole 15 in the manufacturing process of the second wiring layer 16, the wiring layer 16 as the upper wiring layer passes through the through hole 15. It is electrically connected to the wiring layer 11, which is a lower wiring layer.

Therefore, when the misalignment between the through hole 15 and the wiring layer 11 occurs, as in the through hole 15 shown on the left side of FIG. 10, the upper surface and the side surface of the wiring layer 11 which is the lower wiring layer. Since the wiring layer 16 which is the upper wiring layer is brought into contact with each other, it is possible to reliably electrically connect them with a wide contact area.

Further, the through hole 1 shown on the right side of FIG.
5, when there is no misalignment between the through hole 15 and the wiring layer 11, the upper surface of the wiring layer 11 which is the lower wiring layer is the wiring layer 1 which is the upper wiring layer.
Since 6 are contacted, they can be reliably electrically connected with a wide contact area.

Next, an unnecessary region of the wiring layer 16 is selectively removed by using the photolithography technique and the selective etching technique to form a pattern on the second wiring layer 16.

In this case, when the interlayer insulating film is formed on the wiring layer 16 and then the through hole is formed in the interlayer insulating film, this is performed after the etching stopper film is formed on the wiring layer 16. Similar to the first wiring layer 11 described above, the wiring layer 16 does not need to have a wide area called a dog bone.

As a result, since it is not necessary to provide a dog bone in the wiring layer 16, the line width of the wiring layer 16 can be reduced and linearity can be provided, so that the distance to the adjacent wiring layer 16 is also shortened. Wiring layer 16 that can be formed and is adjacent to
Can also be arranged in a straight line.

Therefore, the wiring layer 16 can be finely processed and arranged at a high density.

Next, although not shown, an interlayer insulating film and a wiring layer are laminated on the substrate 9, and then a surface protective film is formed to complete the manufacturing process of the semiconductor integrated circuit device.

According to the method of manufacturing a semiconductor integrated circuit device of this embodiment described above, after forming the wiring layer 11 having no dog bone, the etching stopper film 10 and the interlayer insulating film 12 are formed, and then the interlayer insulating film is formed. After forming the through holes 15 in the selective regions of the film 12, the upper wiring layer 1
6 is formed, and the wiring layer 16 of the upper layer and the wiring layer 11 of the lower layer are electrically connected through the through hole 15, so that the wiring layer 11 of the lower layer without the dog bone is applied. However, since the etching stopper film 10 is formed when the through hole 15 is formed by etching a selective region of the interlayer insulating film 12, the etching stopper film 10 is formed by the etching.
It is possible to prevent the insulating film 8 below the substrate from being etched.

As a result, since it is not necessary to provide a dogbone in the lower wiring layer 11, the line width of the wiring layer 11 can be reduced and linearity can be provided. Therefore, the distance from the adjacent wiring layer 11 can be increased. And the adjacent wiring layers 11 can be arranged linearly.

Therefore, the wiring layer 11 can be finely processed and arranged at a high density.

(Embodiment 3) FIG. 11 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention, and FIG. 12 is a plan view showing a lower wiring layer 11 in FIG. It is a figure.

The manufacturing process of the semiconductor integrated circuit device of the present embodiment is different from the manufacturing process of the wiring layer 11 in the manufacturing process of the semiconductor integrated circuit device of the first embodiment described above, and the other processes are described above. The description is omitted because it is the same as the first embodiment.

As shown in FIG. 11, the wiring layer 11 of the first layer is formed on the surface of the etching stopper film 10 on the substrate 9. The first wiring layer 11 is, for example, an aluminum layer formed by a sputtering method. As the material of the wiring layer 11, various wiring materials may be used similarly to the wiring layer 11 of the first embodiment described above.

Next, the first wiring layer 11 is patterned by using the photolithography technique and the selective etching technique.

In this case, it is not necessary to provide a wide area called a dogbone in the wiring layer 11, and the line width of the wiring layer 11 in the area where the through hole 15 formed by the process described later is arranged is set to another area. The line width should be smaller than the line width.

Even if the line width of the wiring layer 11 in the region where the through hole 15 is arranged in the wiring layer 11 is made smaller than the line widths of the other regions, the etching stopper film 1 is formed.
Since 0 is formed, the etching stopper film 10 is formed in the etching for forming the through hole 15.
The insulating film 8 and the like are not etched.

According to the method of manufacturing a semiconductor integrated circuit device of this embodiment, the line width of the wiring layer 11 in the region where the through holes 15 are arranged in the wiring layer 11 is made smaller than the line widths of the other regions. As a result, the contact area with the upper wiring layer 16 formed in this area becomes wider on the upper surface and both side surfaces of the wiring layer 11, so that the contact area has a wider area. Therefore, the upper wiring layer 16 And the lower wiring layer 11 can be electrically connected with high reliability and fine processing.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-mentioned embodiment, the MOSFE
Although it is a manufacturing technology of a semiconductor integrated circuit device in which T is provided on a semiconductor substrate, a BiMOS or BiCMO in which a CMOSFET, a bipolar transistor, or a MOSFET and a bipolar transistor are combined is provided on the semiconductor substrate.
It can be applied to a manufacturing technique of a semiconductor integrated circuit device in which various semiconductor elements such as an S structure are formed.

[0100]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, after forming the etching stopper film,
A step of forming a lower wiring layer not having a dogbone, an interlayer insulating film is formed, a through hole is formed in a selective region of the interlayer insulating film, and then an upper wiring layer is formed,
By including the step of electrically connecting the upper wiring layer and the lower wiring layer through the through holes, even if the lower wiring layer without the dog bone is applied, the through holes can be selectively connected to the interlayer insulating film. Since the etching stopper film is formed when the region is formed by etching, it is possible to prevent the insulating film below the etching stopper film from being etched by the etching.

As a result, since it is not necessary to provide a dogbone in the lower wiring layer, the line width of the lower wiring layer can be reduced and linearity can be provided, so that the distance to the adjacent lower wiring layer is also shortened. In addition, adjacent lower wiring layers can be linearly arranged.

Therefore, the lower wiring layer can be finely processed and arranged at a high density.

(2) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, the line width of the wiring layer in the region where the through hole is arranged in the lower wiring layer is made smaller than the line width of the other regions. Since the contact area with the upper wiring layer formed in this area is wider on the upper surface and both side surfaces of the wiring layer, the contact area has a wider area. Can be electrically connected with high reliability and fine processing.

(3) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a wide area called a dog bone, which is larger than the line width of the lower wiring layer, is formed in the through hole region of the lower wiring layer. By not having to form
Since the line width of the lower wiring layer does not increase due to the dog bone, the line width of the lower wiring layer can be reduced and linearity can be provided.

Since the lower wiring layer adjacent to the lower wiring layer has no dog bone, the lower wiring layer adjacent to the lower wiring layer can have linearity and can be arranged close to each other. The reliability and fine processing can be achieved, and the wiring design can be simplified.

As a result, it is possible to easily manufacture a semiconductor integrated circuit device having a wiring layer with high reliability and capable of fine processing by adopting a manufacturing process of forming an etching stopper film.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 12 is a plan view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 field insulating film 3 gate insulating film 4 gate electrode 5 insulating film 6 sidewall insulating film 7 semiconductor region 8 insulating film 9 substrate 10 etching stopper film 11 wiring layer 12 interlayer insulating film 13 etching stopper film 14 photoresist film 15 Through hole 16 Wiring layer

Claims (9)

[Claims] 1. A base provided with a plurality of semiconductor elements, a lower wiring layer not provided with dogbones on the base, and at least provided on the base around the lower wiring layer. An etching stopper film, an interlayer insulating film provided on the surfaces of the etching stopper film and the lower wiring layer, and a through hole provided in a selective region of the interlayer insulating film to electrically connect with the lower wiring layer. Integrated circuit device having an upper wiring layer connected electrically. 2. The semiconductor integrated circuit device according to claim 1, wherein a line width of the lower wiring layer in a region connected to the upper wiring through the through hole is smaller than a line width of another region. A characteristic semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the etching stopper film is an insulating film made of a material different from that of the interlayer insulating film. 4. The semiconductor integrated circuit device according to claim 1, wherein the etching stopper film is a silicon nitride film. 5. A step of forming an insulating film as an etching stopper film on a substrate on which a plurality of semiconductor elements are formed, and a lower layer having no dog bone in a selective region on the etching stopper film. Forming a wiring layer, forming an interlayer insulating film on the etching stopper film and the lower wiring layer, forming a through hole in a selective region of the interlayer insulating film, and forming a bottom portion of the through hole. A step of exposing the surface of a selective region of the lower wiring layer to, and forming an upper wiring layer on the interlayer insulating film, and electrically connecting the upper wiring layer and the lower wiring layer through the through hole. And a step of connecting the semiconductor integrated circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, further comprising the step of forming a second insulating film as an etching stopper film on the surface of the interlayer insulating film. Device manufacturing method. 7. A step of forming a lower wiring layer having no dog bones on a substrate on which a plurality of semiconductor elements are formed, and an insulating film serving as an etching stopper film on the substrate including the lower wiring layer. Forming a film, forming an interlayer insulating film on the etching stopper film, and forming a through hole in a selective region of the interlayer insulating film, and then exposing the surface by the through hole. Removing the etching stopper film to expose the surface of a selective region of the lower wiring layer; forming an upper wiring layer on the interlayer insulating film in which the through hole is formed; And a step of electrically connecting the lower wiring layer with the through hole, the method of manufacturing a semiconductor integrated circuit device. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 5, 6 or 7, wherein a line width of the lower wiring layer in a region connected to the upper wiring through the through hole is set to a value different from that of another region. A method for manufacturing a semiconductor integrated circuit device, which is characterized in that it is formed to be smaller than a line width. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 5, 6, 7 or 8, wherein the etching stopper film is a silicon nitride film.