WO2000077840A1

WO2000077840A1 - Semiconductor device and method of manufacture thereof

Info

Publication number: WO2000077840A1
Application number: PCT/JP1999/003178
Authority: WO
Inventors: Hidenori Mochizuki
Original assignee: Asahi Kasei Microsystems Co., Ltd.
Priority date: 1997-12-19
Filing date: 1999-06-15
Publication date: 2000-12-21
Also published as: JPH11186386A

Abstract

An insulating layer (3) is formed on a semiconductor substrate (1) on which a gate electrode (22) and a source drain/region (12) are formed. Contact holes (41, 42) are formed in the insulating layer to expose the upper surfaces of the gate electrode and the source/drain region that are adjacent to each other. Conductor plugs (61, 62) are formed in these contact holes. A conductive film is formed immediately above the conductor plugs and the insulating layer. When the conductive film is etched to form a lower interconnection (7), a cover (8) consisting of the conductive film is formed on the conductor plug (61) that is not connected with this interconnection. This method prevents damage to the conductor plugs (61) and also requires a smaller number of processes steps for manufacture than the conventional method.

Description

Description Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device having a shared contact structure and a method for manufacturing the same. The shared contact structure means a connection structure in which adjacent conductive layers are connected by a conductor plug in one contact hole. Background art

With the progress of higher integration and higher performance in semiconductor devices such as LSI, for example, in the case of MOS transistors, various measures have been taken in designing gate electrodes and wiring structures. For example, in a static random access memory (SRAM) or the like, a shared contact (Shared Contact) structure in which a gate electrode and a source / drain region are formed by a conductor plug in one connector hole. Has been adopted.

FIG. 3 shows an example of a semiconductor device having a shielded contact structure. In part A of this figure, a contact hole is opened in the insulating film 3 so as to extend over the adjacent gate electrode 22 and the source 'drain region 12, and the contact hole is formed in the contact hole. Conductor plugs 61 made of, for example, are formed. The conductor plug 61 connects the gate electrode 22 to the source / drain region 12 adjacent thereto.

In the part B, a conductor plug 62 is formed in the same manner as the conductor plug 61, and a conductor plug 15 is formed immediately above the conductor plug 62. The lower wiring 7 of the layer wiring structure is formed. The lower wiring 7, the gate electrode 22, and the source / drain region 12 are connected by the conductive plug 62 and the conductive plug 15.

That is, in the semiconductor device of FIG. 3, if the conductive film for the lower wiring 7 is formed directly on the insulating film 3, damage to the upper surface of the conductor plug 61 in the portion A occurs when this conductive film is etched. Therefore, an insulating film 14 is further formed on the insulating film 3, and a conductive film for the lower wiring 7 is formed on the insulating film 14. The conductor plug 15 is formed on the insulating film 14.

As described above, in a semiconductor device having a shielded contact structure as indicated by A in FIG. 3, the number of manufacturing steps is reduced in order to prevent the upper surface of the conductor plug 61 from being damaged when the lower wiring 7 is formed. There are many. Therefore, in such a method of manufacturing a semiconductor device, it is required to reduce the number of manufacturing steps.

An object of the present invention is to provide a shielded contact structure as shown in part A of FIG. 3, that is, a shielded contact structure in which no wiring is connected above a conductor plug that connects adjacent conductive layers. A semiconductor device is to be manufactured by a method that does not cause damage to the conductor plug and with a smaller number of steps and L steps than before. Disclosure of the invention

According to the present invention, a conductive plug in one contact hole formed in an interlayer insulating film connects adjacent conductive layers, a wiring layer is formed immediately above the interlayer insulating film, and the wiring layer is connected to the conductive layer. A semiconductor device characterized in that an upper surface of the conductor plug that is not covered with the conductor plug is covered with a conductive covering member isolated from the wiring layer.

As an embodiment of the semiconductor device of the present invention, the coating is for the wiring layer. A semiconductor device formed at the same time as the wiring layer by etching the conductive film.

As an embodiment of the semiconductor device of the present invention, a semiconductor device is characterized in that the conductor plug is mainly made of tungsten and the covering is mainly made of aluminum.

As an embodiment of the semiconductor device of the present invention, a semiconductor device is characterized in that the entire upper surface of the cover is covered with an insulating film.

According to an embodiment of the semiconductor device of the present invention, the conductor plug covered with the cover connects the gate electrode of the MOS transistor to a source / drain region adjacent to the gate electrode. A characteristic semiconductor device is given.

The present invention also provides an interlayer insulating film on a semiconductor substrate including a portion where conductive layers are formed adjacent to each other, and a contact so that the upper surfaces of the two conductive layers are exposed on the interlayer insulating film. A contact hole forming step of forming a hole, a conductor plug forming step of forming a conductor plug in the contact hole, a conductive film forming step of forming a conductive film above the interlayer insulating film, A method of forming a wiring layer by forming a wiring layer by etching a film, wherein a conductive film is formed immediately above the conductor plug and the interlayer insulating film in the conductive film forming step. In the step of forming the wiring layer, a cover isolated from the wiring layer is provided on the conductive plug that is not connected to the wiring layer by etching the conductive film. Provided is a method for manufacturing a semiconductor device, which is formed simultaneously with a line layer.

According to this method, the conductive film for the wiring layer is formed immediately above the conductor plug. However, when this conductive film is etched, the conductive plug is not connected to the wiring layer. An isolated coating is formed from this wiring layer Therefore, no damage occurs to the upper surface of the conductive plug during the etching.

Therefore, a step required to prevent the conductor plug from being damaged by a conventional method (ie, a step of forming an additional insulating film on the insulating layer having the conductor plug, It is not necessary to perform a step of forming a contact hole for connection to a wiring layer and a step of forming a conductor plug in this contact hole.

As an embodiment of the method of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the conductor plug is mainly made of tantalum, and the covering is mainly made of aluminum.

As an embodiment of the method of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a step of covering the entire upper surface of the cover with an insulating film. The present invention also provides an element forming step of forming a gate electrode and a source / drain region of a MOS transistor on a semiconductor substrate, and a first step of forming a first interlayer insulating film on the semiconductor substrate after the element forming step. An interlayer insulating film forming step; a contact hole forming step of forming a contact hole in the first interlayer insulating film such that an upper surface of an adjacent gate electrode and a source / drain region are exposed; and A conductive plug forming step of forming a conductive plug therein; a conductive film forming step of forming a conductive film above the first interlayer insulating film; and a wiring forming a wiring layer by etching the conductive film. A method of manufacturing a semiconductor device having a layer forming step, wherein in the conductive film forming step, a conductive film is formed immediately above the conductive plug and the first interlayer insulating film; In the wiring layer forming step, on the conductive plug not connected to the wiring layer, a cover isolated from the wiring layer is formed simultaneously with the wiring layer by etching the conductive film, and the wiring layer forming layer is formed. Forming a second interlayer insulating film immediately above the wiring layer and the cover after the step The present invention provides a method for manufacturing a semiconductor device, characterized in that: BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and is a partial cross-sectional view showing the vicinity of the surface of a semiconductor substrate.

FIG. 2 is a plan view of FIG. 1 (b).

FIG. 3 is a view showing a conventional example of a semiconductor device having a contact structure, and is a partial cross-sectional view showing the vicinity of the surface of a semiconductor substrate. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described.

FIG. 1 is a view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and is a partial cross-sectional view showing the vicinity of the surface of a semiconductor substrate. The method of this embodiment will be described with reference to FIG.

First, an element including a gate electrode 22 of a MOS transistor and a source / drain region 12 is formed on a semiconductor substrate 1.

That is, first, an element isolation step is performed on the surface of the semiconductor substrate 1 by forming a field oxide film and a trench. Next, a gate oxide film 21 and a gate electrode 22 (22a, 22b) having a two-layer structure are formed at predetermined positions in the element formation region. Next, impurities are introduced into predetermined positions of the element forming region to form impurity diffusion layers 11 to 13. Next, an insulating film 23 that contacts the side surfaces of the gate electrode 22 and the gate oxide film 21 and the upper surface of the impurity diffusion layer 13 is formed. Next, impurities are further introduced into the impurity diffusion layers 11 and 12 to make the impurity diffusion layers 11 and 12 high-concentration diffusion layers. Next, after an insulating film (first interlayer insulating film) 3 is formed on the semiconductor substrate 1 in this state, contact holes 41, 42, and 5 are formed by a photolithography and etching process on the insulating film 3. Form. Of these, contact holes 41 are provided at the portions in contact with the gate electrode 22 and the adjacent source / drain regions 12 so that the upper surfaces of the gate electrode 22 and the source / drain regions 12 are exposed. , 42. A normal contact hole 5 is formed in the portion of the impurity diffusion layer 11. FIG. 1A shows a state after the contact hole forming step.

Next, a barrier layer made of Ti or TiN is formed on the side and bottom surfaces of each contact hole and on the upper surface of the insulating film 3. Next, a tungsten film is deposited on the barrier layer by a CVD method. Next, the tungsten film on the insulating film 3 is removed by a plasma etching method to leave tungsten only in the contact hole. As a result, conductive plugs 61, 62, 63 made of tungsten are formed in contact holes 41, 42, 5, respectively.

Here, the conductor plug 61 connects the gate electrode 22 and the adjacent source / drain region 12 (adjacent conductive layer) to each other. Lower wiring 7 is not connected. On the other hand, the conductive plug 62 connects not only the gate electrode 22 and the source / drain regions 12 adjacent thereto but also these and the lower wiring 7 thereon. The conductor plug 63 connects the impurity diffusion layer 11 to the lower wiring 7 thereon.

Next, an aluminum film (conductive film forming a wiring layer) is formed immediately above the conductor plugs 61 to 63 and the insulating film 3. Next, using a mask having a wiring pattern of the lower wiring 7 and a pattern of a cover 8 covering the upper surface of the conductor plug 61, photolithography is performed on the aluminum film. Perform a tuning step. As the aluminum film, an aluminum alloy film containing Si or Si and Cu as an alloy component can be appropriately selected. Etching of Aruminiumu film is performed using a mixed gas of e.g. BC 1 3 and C 1 ₂ as the etching gas.

Thereby, the lower wiring 7 and the covering 8 are formed on the insulating film 3 and the conductor plugs 61 to 63. FIG. 1B shows the state after the wiring layer forming step. FIG. 2 is a plan view of FIG. 1 (b).

As shown in FIG. 2, the lower wiring 7 extends in a circuit shape in a plane to be connected to other wirings and conductive layers. On the other hand, the cover 8 covers the upper surface of the conductor plug 61 in a state of being isolated from the lower wiring 7.

As described above, when the conductive film for the lower wiring 7 is etched, the conductive film existing on the conductor plug 61 that is not connected to the lower wiring 7 is not etched and is isolated from the lower wiring 7. Left as coating 8. Therefore, the upper surface of the conductor plug 61 not connected to the lower wiring 7 is not damaged by the etching gas when the lower wiring 7 is formed.

Next, an insulating film (second interlayer insulating film) 18 is formed on the lower wiring 7 and the cover 8. After opening a contact hole for connection to the upper wiring 9 in the insulating film 18, a conductor plug 8.1 is formed in each contact hole in the same manner as described above. Thereafter, upper wiring 9 is formed on insulating film 18 by a normal method. As a result, a semiconductor device as shown in FIG. 1 (c) is obtained.

According to the method of this embodiment, as described above, the upper surface of the conductor plug 61 to which the lower wiring 7 is not connected is not damaged in the etching step when the lower wiring 7 is formed. Therefore, in this semiconductor device, the connection between the gate electrode 22 and the source / drain region 12 adjacent thereto by the conductor plug 61 is ensured. The planar shape of the cover 8 may be a shape that covers the entire upper surface of the conductor plug 61, but if the cover 8 has a shape that covers the insulating film 3 around the conductor plug 61 with a predetermined width, damage to the conductor plug 61 can be prevented. This is preferable because it can be more reliably prevented. The dimension (L 1 in FIG. 2) of the portion of the coating 8 protruding outside the conductor plug 61 is equivalent to, for example, 30 to 80% of the dimension (L in FIG. 2) of the conductor plug 61. Make sure it is sized. Preferably, L1 has a size corresponding to 60% of L.

When comparing the semiconductor device of FIG. 1 (c) with the conventional example of FIG. 3, there is an insulating film 14 having a conductor plug 15 in FIG. 3, but not in FIG. 1 (c). Also, the covering 8 is shown in FIG. 1 (c) but not in FIG. For these reasons, the structure of the semiconductor device of FIG. 1 (c) has a smaller number of steps than the conventional example of FIG. Therefore, the semiconductor device of the present invention has higher flatness than a conventional product.

In the above embodiment, the conductor plug 61 to which the lower wiring 7 is not connected is mainly made of tungsten, and an aluminum film is used as a conductive film for the lower wiring 7. However, the materials of the conductive plug 61 and the conductive film for the lower wiring 7 are not limited to these.

For example, when the conductive film for the lower wiring 7 is a film containing aluminum as a main component and the conductor plug 61 is also mainly made of aluminum, the conductive gas is formed by an etching gas for forming the lower wiring 7. The plug 61 is easily etched. In such a case, that is, when the material of the conductor plug 61 is a material which is easily etched by the etching gas for forming the lower wiring 7, the method of the present invention (from providing the covering 8, Protecting the upper surface of the conductor plug 61) is particularly effective. Further, adjacent conductive layers in the above-described embodiment include a gate electrode formed near the surface of the semiconductor substrate and a source / drain formed on the surface of the semiconductor substrate. The present invention is also applied to a case where adjacent conductive layers are formed in a layer on a semiconductor substrate at a position away from the surface of the semiconductor substrate. Industrial applicability

As described above, according to the method of the present invention, a semiconductor device having a shield contact structure in which no wiring is connected on a conductor plug that connects adjacent conductive layers to each other is added to the conductor plug. It can be manufactured with fewer steps than before without causing damage.

Therefore, a semiconductor device in which adjacent conductive layers are reliably connected by the conductive plug having the shield contact structure can be obtained at lower cost than before.

Further, in the semiconductor device of the present invention and the semiconductor device obtained by the method of the present invention, adjacent conductive layers are surely connected to each other by the conductive plug having the shield contact structure.

Claims

The scope of the claims

1. Adjacent conductive layers are connected by conductor plugs in one contact hole formed in the interlayer insulating film, and a wiring layer is formed immediately above the interlayer insulating film, and is not connected to this wiring layer The semiconductor device according to claim 1, wherein an upper surface of the conductor plug is covered with a conductive covering isolated from the wiring layer.

2. The semiconductor device according to claim 1, wherein the cover is formed simultaneously with the wiring layer by etching the conductive film for the wiring layer.

3. The semiconductor device according to claim 1, wherein the conductor plug is mainly made of tungsten, and the cover is mainly made of aluminum.

4. The semiconductor device according to claim 1, wherein an entire upper surface of the cover is covered with an insulating film.

5. The semiconductor device according to claim 1, wherein the conductor plug covered by the cover connects the gate electrode of the MOS transistor to a source / drain region adjacent to the gate electrode. A semiconductor device, comprising:

6. An inter-layer insulating film is provided on the semiconductor substrate including the portion where the conductive layers are formed adjacent to each other, and contact holes are formed in the interlayer insulating film so that the upper surfaces of the two conductive layers are exposed. A contact hole forming step; a conductive plug forming step of forming a conductive plug in the contact hole; a conductive film forming step of forming a conductive film above the interlayer insulating film; and etching the conductive film And a wiring layer forming step of forming a wiring layer by performing the method. Forming a conductive film directly on the conductive plug and the interlayer insulating film in the conductive film forming step;

In the step of forming the wiring layer, a covering isolated from the wiring layer is formed simultaneously with the wiring layer by etching the conductive film on the conductive plug not connected to the wiring layer. A method for manufacturing semiconductor devices.

7. The method according to claim 6, wherein the conductive plug is mainly made of tungsten, and the covering is mainly made of aluminum.

8. The method according to claim 6, further comprising a step of covering an entire upper surface of the cover with an insulating film.

9. An element forming step of forming a gate electrode and a source / drain region of a MOS transistor on a semiconductor substrate; and a first interlayer forming a first interlayer insulating film on the semiconductor substrate after the element forming step. An insulating film forming step; a contact hole forming step for forming a contact hole in the first interlayer insulating film such that an upper surface of an adjacent gate electrode and a source / drain region are exposed; and a conductive hole in the contact hole. Forming a conductive plug, forming a conductive plug over the first interlayer insulating film, forming a conductive layer over the first interlayer insulating film, and forming a wiring layer by etching the conductive film. A method of manufacturing a semiconductor device having

Forming a conductive film directly on the conductive plug and the first inter-layer insulating film in the conductive film forming step;

In the wiring layer forming step, on the conductive plug not connected to the wiring layer, a cover isolated from the wiring layer is formed simultaneously with the wiring layer by etching the conductive film,

After the wiring layer forming step, a second interlayer insulation is provided just above the wiring layer and the cover. A method for manufacturing a semiconductor device, comprising forming an edge film: