WO2000077840A1 - Dispositif a semi-conducteur et son procede de fabrication - Google Patents

Dispositif a semi-conducteur et son procede de fabrication Download PDF

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Publication number
WO2000077840A1
WO2000077840A1 PCT/JP1999/003178 JP9903178W WO0077840A1 WO 2000077840 A1 WO2000077840 A1 WO 2000077840A1 JP 9903178 W JP9903178 W JP 9903178W WO 0077840 A1 WO0077840 A1 WO 0077840A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
forming
wiring layer
insulating film
semiconductor device
Prior art date
Application number
PCT/JP1999/003178
Other languages
English (en)
Japanese (ja)
Inventor
Hidenori Mochizuki
Original Assignee
Asahi Kasei Microsystems Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP9351152A priority Critical patent/JPH11186386A/ja
Application filed by Asahi Kasei Microsystems Co., Ltd. filed Critical Asahi Kasei Microsystems Co., Ltd.
Priority to KR10-2001-7001910A priority patent/KR100399862B1/ko
Priority to DE19983428T priority patent/DE19983428B4/de
Priority to PCT/JP1999/003178 priority patent/WO2000077840A1/fr
Publication of WO2000077840A1 publication Critical patent/WO2000077840A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device having a shared contact structure and a method for manufacturing the same.
  • the shared contact structure means a connection structure in which adjacent conductive layers are connected by a conductor plug in one contact hole.
  • FIG. 3 shows an example of a semiconductor device having a shielded contact structure.
  • a contact hole is opened in the insulating film 3 so as to extend over the adjacent gate electrode 22 and the source 'drain region 12, and the contact hole is formed in the contact hole.
  • Conductor plugs 61 made of, for example, are formed. The conductor plug 61 connects the gate electrode 22 to the source / drain region 12 adjacent thereto.
  • a conductor plug 62 is formed in the same manner as the conductor plug 61, and a conductor plug 15 is formed immediately above the conductor plug 62.
  • the lower wiring 7 of the layer wiring structure is formed.
  • the lower wiring 7, the gate electrode 22, and the source / drain region 12 are connected by the conductive plug 62 and the conductive plug 15.
  • the number of manufacturing steps is reduced in order to prevent the upper surface of the conductor plug 61 from being damaged when the lower wiring 7 is formed. There are many. Therefore, in such a method of manufacturing a semiconductor device, it is required to reduce the number of manufacturing steps.
  • An object of the present invention is to provide a shielded contact structure as shown in part A of FIG. 3, that is, a shielded contact structure in which no wiring is connected above a conductor plug that connects adjacent conductive layers.
  • a semiconductor device is to be manufactured by a method that does not cause damage to the conductor plug and with a smaller number of steps and L steps than before. Disclosure of the invention
  • a conductive plug in one contact hole formed in an interlayer insulating film connects adjacent conductive layers, a wiring layer is formed immediately above the interlayer insulating film, and the wiring layer is connected to the conductive layer.
  • a semiconductor device characterized in that an upper surface of the conductor plug that is not covered with the conductor plug is covered with a conductive covering member isolated from the wiring layer.
  • the coating is for the wiring layer.
  • a semiconductor device is characterized in that the conductor plug is mainly made of tungsten and the covering is mainly made of aluminum.
  • a semiconductor device is characterized in that the entire upper surface of the cover is covered with an insulating film.
  • the conductor plug covered with the cover connects the gate electrode of the MOS transistor to a source / drain region adjacent to the gate electrode.
  • a characteristic semiconductor device is given.
  • the present invention also provides an interlayer insulating film on a semiconductor substrate including a portion where conductive layers are formed adjacent to each other, and a contact so that the upper surfaces of the two conductive layers are exposed on the interlayer insulating film.
  • a cover isolated from the wiring layer is provided on the conductive plug that is not connected to the wiring layer by etching the conductive film.
  • a method for manufacturing a semiconductor device which is formed simultaneously with a line layer.
  • the conductive film for the wiring layer is formed immediately above the conductor plug.
  • this conductive film is etched, the conductive plug is not connected to the wiring layer.
  • An isolated coating is formed from this wiring layer Therefore, no damage occurs to the upper surface of the conductive plug during the etching.
  • a step required to prevent the conductor plug from being damaged by a conventional method ie, a step of forming an additional insulating film on the insulating layer having the conductor plug, It is not necessary to perform a step of forming a contact hole for connection to a wiring layer and a step of forming a conductor plug in this contact hole.
  • the conductor plug is mainly made of tantalum, and the covering is mainly made of aluminum.
  • a method of manufacturing a semiconductor device comprising a step of covering the entire upper surface of the cover with an insulating film.
  • the present invention also provides an element forming step of forming a gate electrode and a source / drain region of a MOS transistor on a semiconductor substrate, and a first step of forming a first interlayer insulating film on the semiconductor substrate after the element forming step.
  • a method of manufacturing a semiconductor device having a layer forming step wherein in the conductive film forming step, a conductive film is formed immediately above the conductive plug and the first interlayer insulating film;
  • a cover isolated from the wiring layer is formed simultaneously with the wiring layer by etching the conductive film, and the wiring layer forming layer is formed.
  • Forming a second interlayer insulating film immediately above the wiring layer and the cover after the step The present invention provides a method for manufacturing a semiconductor device, characterized in that: BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is a view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and is a partial cross-sectional view showing the vicinity of the surface of a semiconductor substrate.
  • FIG. 2 is a plan view of FIG. 1 (b).
  • FIG. 3 is a view showing a conventional example of a semiconductor device having a contact structure, and is a partial cross-sectional view showing the vicinity of the surface of a semiconductor substrate.
  • FIG. 1 is a view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and is a partial cross-sectional view showing the vicinity of the surface of a semiconductor substrate. The method of this embodiment will be described with reference to FIG.
  • an element including a gate electrode 22 of a MOS transistor and a source / drain region 12 is formed on a semiconductor substrate 1.
  • an element isolation step is performed on the surface of the semiconductor substrate 1 by forming a field oxide film and a trench.
  • a gate oxide film 21 and a gate electrode 22 (22a, 22b) having a two-layer structure are formed at predetermined positions in the element formation region.
  • impurities are introduced into predetermined positions of the element forming region to form impurity diffusion layers 11 to 13.
  • an insulating film 23 that contacts the side surfaces of the gate electrode 22 and the gate oxide film 21 and the upper surface of the impurity diffusion layer 13 is formed.
  • impurities are further introduced into the impurity diffusion layers 11 and 12 to make the impurity diffusion layers 11 and 12 high-concentration diffusion layers.
  • FIG. 1A shows a state after the contact hole forming step.
  • a barrier layer made of Ti or TiN is formed on the side and bottom surfaces of each contact hole and on the upper surface of the insulating film 3.
  • a tungsten film is deposited on the barrier layer by a CVD method.
  • the tungsten film on the insulating film 3 is removed by a plasma etching method to leave tungsten only in the contact hole.
  • conductive plugs 61, 62, 63 made of tungsten are formed in contact holes 41, 42, 5, respectively.
  • the conductor plug 61 connects the gate electrode 22 and the adjacent source / drain region 12 (adjacent conductive layer) to each other. Lower wiring 7 is not connected.
  • the conductive plug 62 connects not only the gate electrode 22 and the source / drain regions 12 adjacent thereto but also these and the lower wiring 7 thereon.
  • the conductor plug 63 connects the impurity diffusion layer 11 to the lower wiring 7 thereon.
  • an aluminum film (conductive film forming a wiring layer) is formed immediately above the conductor plugs 61 to 63 and the insulating film 3.
  • photolithography is performed on the aluminum film.
  • an aluminum alloy film containing Si or Si and Cu as an alloy component can be appropriately selected.
  • Etching of Aruminiumu film is performed using a mixed gas of e.g. BC 1 3 and C 1 2 as the etching gas.
  • FIG. 1B shows the state after the wiring layer forming step.
  • FIG. 2 is a plan view of FIG. 1 (b).
  • the lower wiring 7 extends in a circuit shape in a plane to be connected to other wirings and conductive layers.
  • the cover 8 covers the upper surface of the conductor plug 61 in a state of being isolated from the lower wiring 7.
  • the conductive film for the lower wiring 7 is etched, the conductive film existing on the conductor plug 61 that is not connected to the lower wiring 7 is not etched and is isolated from the lower wiring 7. Left as coating 8. Therefore, the upper surface of the conductor plug 61 not connected to the lower wiring 7 is not damaged by the etching gas when the lower wiring 7 is formed.
  • an insulating film (second interlayer insulating film) 18 is formed on the lower wiring 7 and the cover 8. After opening a contact hole for connection to the upper wiring 9 in the insulating film 18, a conductor plug 8.1 is formed in each contact hole in the same manner as described above. Thereafter, upper wiring 9 is formed on insulating film 18 by a normal method. As a result, a semiconductor device as shown in FIG. 1 (c) is obtained.
  • the upper surface of the conductor plug 61 to which the lower wiring 7 is not connected is not damaged in the etching step when the lower wiring 7 is formed. Therefore, in this semiconductor device, the connection between the gate electrode 22 and the source / drain region 12 adjacent thereto by the conductor plug 61 is ensured.
  • the planar shape of the cover 8 may be a shape that covers the entire upper surface of the conductor plug 61, but if the cover 8 has a shape that covers the insulating film 3 around the conductor plug 61 with a predetermined width, damage to the conductor plug 61 can be prevented. This is preferable because it can be more reliably prevented.
  • L1 has a size corresponding to 60% of L.
  • the semiconductor device of FIG. 1 (c) When comparing the semiconductor device of FIG. 1 (c) with the conventional example of FIG. 3, there is an insulating film 14 having a conductor plug 15 in FIG. 3, but not in FIG. 1 (c). Also, the covering 8 is shown in FIG. 1 (c) but not in FIG. For these reasons, the structure of the semiconductor device of FIG. 1 (c) has a smaller number of steps than the conventional example of FIG. Therefore, the semiconductor device of the present invention has higher flatness than a conventional product.
  • the conductor plug 61 to which the lower wiring 7 is not connected is mainly made of tungsten, and an aluminum film is used as a conductive film for the lower wiring 7.
  • the materials of the conductive plug 61 and the conductive film for the lower wiring 7 are not limited to these.
  • the conductive film for the lower wiring 7 is a film containing aluminum as a main component and the conductor plug 61 is also mainly made of aluminum
  • the conductive gas is formed by an etching gas for forming the lower wiring 7.
  • the plug 61 is easily etched.
  • the method of the present invention from providing the covering 8, Protecting the upper surface of the conductor plug 61
  • adjacent conductive layers in the above-described embodiment include a gate electrode formed near the surface of the semiconductor substrate and a source / drain formed on the surface of the semiconductor substrate.
  • the present invention is also applied to a case where adjacent conductive layers are formed in a layer on a semiconductor substrate at a position away from the surface of the semiconductor substrate.
  • a semiconductor device having a shield contact structure in which no wiring is connected on a conductor plug that connects adjacent conductive layers to each other is added to the conductor plug. It can be manufactured with fewer steps than before without causing damage.
  • adjacent conductive layers are surely connected to each other by the conductive plug having the shield contact structure.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Une couche isolante (3) est formée sur un substrat à semi-conducteur (1) sur lequel une électrode de grille (22) et une zone de drain/source (12) sont formées. Des fenêtres de contact (41, 42) sont formées dans la couche isolante, de sorte que les surfaces supérieures de l'électrode de grille et de la région de source/drain adjacentes l'une à l'autre soient exposées. Des prises conductrices (61, 62) sont formées dans ces fenêtres de contact. Un film conducteur est formé immédiatement au-dessus des prises conductrices et de la couche isolante. Lorsque le film conducteur est attaqué, de manière qu'une interconnexion inférieur (7) soit formée, un élément de recouvrement (8) constitué du film conducteur est formé sur la prise conductrice (61) qui n'est pas connectée à ladite interconnexion. Ledit procédé empêche les prises conductrices d'être endommagées (61) et comprend un nombre d'étapes de fabrication inférieur à celui requis dans un procédé classique.
PCT/JP1999/003178 1997-12-19 1999-06-15 Dispositif a semi-conducteur et son procede de fabrication WO2000077840A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP9351152A JPH11186386A (ja) 1997-12-19 1997-12-19 半導体装置およびその製造方法
KR10-2001-7001910A KR100399862B1 (ko) 1999-06-15 1999-06-15 반도체 장치 및 그 제조 방법
DE19983428T DE19983428B4 (de) 1999-06-15 1999-06-15 Halbleitervorrichtung mit einer geteilten Kontaktstruktur und Verfahren zur Herstellung derselben
PCT/JP1999/003178 WO2000077840A1 (fr) 1997-12-19 1999-06-15 Dispositif a semi-conducteur et son procede de fabrication

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP9351152A JPH11186386A (ja) 1997-12-19 1997-12-19 半導体装置およびその製造方法
PCT/JP1999/003178 WO2000077840A1 (fr) 1997-12-19 1999-06-15 Dispositif a semi-conducteur et son procede de fabrication

Publications (1)

Publication Number Publication Date
WO2000077840A1 true WO2000077840A1 (fr) 2000-12-21

Family

ID=26440149

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Application Number Title Priority Date Filing Date
PCT/JP1999/003178 WO2000077840A1 (fr) 1997-12-19 1999-06-15 Dispositif a semi-conducteur et son procede de fabrication

Country Status (2)

Country Link
JP (1) JPH11186386A (fr)
WO (1) WO2000077840A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001176964A (ja) 1999-12-16 2001-06-29 Mitsubishi Electric Corp 半導体装置および半導体装置製造方法
JP4911838B2 (ja) * 2001-07-06 2012-04-04 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4110192B1 (ja) 2007-02-23 2008-07-02 キヤノン株式会社 光電変換装置及び光電変換装置を用いた撮像システム
JP2011049601A (ja) * 2010-12-03 2011-03-10 Renesas Electronics Corp 半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685080A (ja) * 1992-08-31 1994-03-25 Nippon Steel Corp 半導体装置及びその製造方法
JPH08181205A (ja) * 1994-12-26 1996-07-12 Mitsubishi Electric Corp 半導体装置の配線構造およびその製造方法
JPH10326896A (ja) * 1997-03-25 1998-12-08 Toshiba Corp 半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685080A (ja) * 1992-08-31 1994-03-25 Nippon Steel Corp 半導体装置及びその製造方法
JPH08181205A (ja) * 1994-12-26 1996-07-12 Mitsubishi Electric Corp 半導体装置の配線構造およびその製造方法
JPH10326896A (ja) * 1997-03-25 1998-12-08 Toshiba Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JPH11186386A (ja) 1999-07-09

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