JPH04313256A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To enable disconnection failure or damage of a wire to be reduced in a semiconductor device which is coated by an inorganic insulation film where the wire which is formed on a ground insulation film is deposited by the plasma CVD method and enable man-hour of production process to be reduced in the semiconductor integrated circuit device. CONSTITUTION:In a semiconductor integrated circuit device which is coated by an inorganic insulation film 8 where a wire 7 which is formed on a ground insulation film 4 is deposited by the plasma CVD method. a stress-relaxation layer (for example, polyimide resin film) 6 is constituted between the above wire 7 and the ground insulation film 4. Also. a forming process of the stress relaxation layer 6 is incorporated into a forming process of a connection hole 5 and that of the wire 7.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to semiconductor integrated circuit devices, and is particularly applicable to semiconductor integrated circuit devices in which wiring formed on a base insulating film is covered with an inorganic insulating film deposited by plasma CVD. It is related to effective technology.

0002

2. Description of the Related Art Semiconductor memory devices, such as DRAM (Dy
namic Random Access Memory
y), as described in Japanese Patent Application No. 1-65848,
Laminated wiring is used as data lines and shunt word lines. The layered wiring is formed on a base insulating film such as an inorganic silicon oxide film or a PSG film deposited by the CVD method.
It consists of a three-layer structure in which two films are sequentially laminated.

[0003] MoSi2 in the lower layer of the wiring in the laminated structure
The film acts as a barrier metal film that prevents mutual diffusion of Si atoms in the semiconductor region formed on the main surface of the semiconductor substrate and Al atoms in the intermediate layer aluminum alloy film.

The intermediate layer aluminum alloy film is formed of an aluminum film to which at least one of Si, which improves alloy spike resistance, and Cu, which improves electromigration resistance, is added.

The upper MoSi2 film reduces the reflectance of light and prevents pattern changes due to diffraction phenomena during development of the photoresist film in the photolithography process for forming a patterning mask for wiring in this layered structure. Can be reduced. Moreover, this MoSi2 film covers the surface of the intermediate layer aluminum alloy film, and can reduce the occurrence of aluminum hillocks on the surface.

[0006] The above-mentioned DRAM has two layers of wiring having the above-mentioned laminated structure, and a final protective film (final passivation film) is coated on the uppermost (second layer) wiring of the laminated structure. The final protective film is plasma CVD with excellent moisture resistance.
The film is formed of a dense inorganic insulating film deposited by a plasma CVD method, such as a silicon nitride film deposited by a method or a silicon oxide film deposited by a similar method.

[0007]

[Problems to be Solved by the Invention] Since the final protective film is a dense insulating film deposited by plasma CVD method,
It has a large coefficient of linear expansion and applies large stress to wiring in a laminated structure. On the other hand, among interconnects in a laminated structure, the wiring width dimension of the intermediate layer aluminum alloy film is likely to be smaller than the size of Al crystal grains (grain size) due to miniaturization due to higher integration. In other words, the phenomenon that boundaries between Al crystal grains often cross the aluminum alloy film in the wiring width direction occurs. Therefore, due to the stress generated in the final protective film mentioned above, especially the tensile stress acting in the wiring length direction,
Disconnections occur in the intermediate layer aluminum alloy film of the wiring in the stacked structure, mainly in areas where boundaries between Al crystal grains cross. So-called stress migration occurs.

An object of the present invention is to provide a semiconductor integrated circuit device in which wiring formed on a base insulating film is coated with an inorganic insulating film deposited by a plasma CVD method, in which disconnection or damage to the wiring can be reduced. Our goal is to provide the technology that is possible.

Another object of the present invention is to provide a technique capable of reducing the number of manufacturing process steps to achieve the above object in the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0011]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

(1) A semiconductor integrated circuit device in which a single-layer or multilayer interconnection mainly made of metal or alloy formed on a base insulating film is covered with an inorganic insulating film deposited by plasma CVD. In this method, a stress relaxation layer having a lower hardness than either the wiring or the underlying insulating film is interposed between the wiring and the underlying insulating film. This stress relief layer is
It is constructed only under the wiring and is made of polyimide resin.

(2) In the method for forming a semiconductor integrated circuit device, a step of forming a base insulating film over the entire surface of the substrate including on the main surface of the semiconductor substrate or on the lower layer wiring arranged on the main surface of the semiconductor substrate; A first resin film, which is organic and has lower hardness than the base insulating film, is formed on the entire surface of the base insulating film, and a first resin film is formed on the entire surface of the first resin film.
A step of forming a second resin film having an etching selectivity with respect to the resin film and having photosensitivity, and removing a part of the second resin film using photolithography technology.
Using the other part of the resin film as an etching mask, a part of the first resin film is removed by etching to form a first opening, and then the other part of the second resin film used as the etching mask is removed. a step of removing a part of the base insulating film using the other region of the first resin film as an etching mask to form a second opening; The entire surface of the substrate, including other regions, a part of the main surface of the semiconductor substrate exposed from the first opening and the second opening, or a part of the lower wiring layer, is mainly made of metal or alloy. a step of forming a wiring layer having a single-layer structure or a laminated structure; and a step of forming an etching mask having an etching selectivity equal to or close to that of the first resin film in a part of the wiring layer. , using this etching mask, etching away other areas of the wiring layer and forming wiring in the remaining part of the wiring layer; removing the etching mask, and removing the area under the wiring. forming a stress relaxation layer using the first resin film remaining under the wiring; and a step of forming an inorganic insulating film.

[0014]

[Operation] According to the above-mentioned means (1), in a semiconductor integrated circuit device, stress (tensile stress) acting in the wiring length direction of the wiring is reduced based on the expansion of the inorganic insulating film deposited by the plasma CVD method. Since the stress relaxation film absorbs the stress and improves the stress migration resistance of the wiring, it is possible to prevent disconnection and damage to the wiring.

According to the above-mentioned means (2), a second resin film is formed for patterning the second opening formed in the base insulating film, and a first resin film is also formed (part of the multilayer resist film). (a first resin film is formed as a layer), a second resin film is used, a part of the first resin film is removed, and the other part of the first resin film is replaced with the second resin film. A second opening is formed in the underlying insulating film using the area as an etching mask, and then the etching mask for patterning the wiring is removed, leaving the first resin film only under the wiring, and the first resin film is removed. Since the stress relaxation layer was formed in the second
A stress relaxation layer formation process is incorporated into each of the opening process and the wiring etching mask removal process, and the number of steps in the manufacturing process of a semiconductor integrated circuit device can be reduced by the amount corresponding to the stress relaxation layer formation process.

Furthermore, since the other region of the first resin film is patterned using the wiring as an etching mask,
A stress relaxation layer can be formed only under the wiring in a self-aligned manner with respect to the wiring.

The structure of the present invention will be described below along with one embodiment applied to a semiconductor integrated circuit device in which wiring formed on a base insulating film is covered with a final protective film.

In all the drawings for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[0019]

[Embodiments] (Embodiment 1) A schematic configuration of a semiconductor integrated circuit device according to Embodiment 1 of the present invention is shown in FIG. 1 (cross-sectional view of main parts).

The semiconductor integrated circuit device of Example 1 is shown in FIG.
As shown in FIG.
It is mainly composed of. The active region of the main surface of the semiconductor substrate 1 (or the main surface of the well region formed on the main surface) includes the source region and drain region of the MISFET, the resistive element,
Semiconductor regions 2 of opposite conductivity type forming a semiconductor element such as a capacitive element are formed. An element isolation insulating film 3 is provided on the non-active region of the main surface of the semiconductor substrate 1 to isolate the semiconductor elements from each other.
is configured. This element isolation insulating film is formed of, for example, a silicon oxide film formed by selectively oxidizing a non-active region on the main surface of the semiconductor substrate 1.

An interlayer insulating film 4 used as a base insulating film for wiring is formed over the entire main surface of the semiconductor substrate 1, including on the semiconductor element and on the element isolation insulating film 3. This interlayer insulating film 4 is made of, for example, an inorganic silicon oxide film, a PSG film, a BPSG film, or an SOG (Spi) film deposited by the CVD method.
Basically, it is mainly composed of an inorganic silicon oxide film, such as a silicon oxide film coated and cured by the n-on-glass method. In the first embodiment, the interlayer insulating film 4 has a single-layer structure, but for example, a silicon oxide film deposited by a plasma CVD method, a silicon oxide film coated by an SOG method and hardened by a baking process, a silicon oxide film deposited by a plasma CVD method, and a silicon oxide film hardened by a baking process. The silicon oxide film may be formed into a laminated structure in which the silicon oxide films deposited in the above steps are sequentially laminated.

A wiring 7 is formed on the interlayer insulating film 4. The wiring 7 is formed of, for example, an aluminum film or an aluminum alloy film. The aluminum alloy film is formed of an aluminum film to which at least one of Si, which improves alloy spike resistance, and Cu, which improves electromigration resistance, is added. An aluminum film or an aluminum alloy film has characteristics such as low resistance, high signal transmission speed, dry etching, and microfabrication. This wiring 7 is electrically connected to the semiconductor region 2 through a contact hole 5 formed in the interlayer insulating film 4.

In the first embodiment, the wiring 7 has a one-layer structure for the purpose of simplifying the explanation, but the present invention basically has a multilayer wiring structure of two, three or more layers. The present invention may also be applied to a semiconductor integrated circuit device that employs this structure.

A final protective film (final passivation film) 8 is formed on the entire surface of the substrate including the wiring 7. This final protective film 8 is mainly composed of a silicon nitride film deposited by plasma CVD in order to improve moisture resistance. In addition to the silicon nitride film, the final protective film 8 has a single-layer structure such as a silicon oxide film deposited by a plasma CVD method, a silicon oxide film deposited by a plasma CVD method using tetraethoxysilane gas as a source gas, etc. Alternatively, a stacked structure of a silicon nitride film and a silicon oxide film deposited by these methods may be used.

In the semiconductor integrated circuit device constructed as described above, a stress relaxation layer 6 is formed between the interlayer insulating film 4 as a base insulating film and the wiring 7. This stress relaxation layer 6 is connected to the wiring 7
Alternatively, when the wiring 7 and the semiconductor region 2 are connected, it is formed only under the wiring 7 excluding the area of the connection hole 5.

The stress relaxation layer 6 has a hardness lower than that of the interlayer insulating film 4 as a base insulating film and the wiring 7, and is made of, for example, an organic polyimide resin film having insulating properties. Ru. Basically, the stress relaxation layer 6 may be formed of an inorganic material or a conductive material as long as it has low hardness.

FIG. 2 (an enlarged cross-sectional view of the main part modeled in the conventional method) shows that when the wiring 7 is placed directly on the surface of the interlayer insulating film 4, stress due to the expansion of the final protective film 8 acts on the wiring 7. Indicates the state of As shown in FIG. 2, the maximum tensile stress F1 generated at the end of the interconnect 7 is a component force F3 in a direction perpendicular to the surface of the interlayer insulating film 4 (parallel to the end surface of the interconnect 7), and a component force F3 of the interlayer insulating film 4 It can be decomposed into component forces F2 in a direction parallel to the surface (parallel to the length direction of the wiring 7). Vertical force F3
is small because the interlayer insulating film 4 has high hardness and there is little escape of stress in the vertical direction, and the component force F2 in the parallel direction becomes correspondingly large. In other words, the tensile stress of the wiring 7, especially in the wiring length direction, becomes high.

On the other hand, as shown in FIG. 3 (an enlarged cross-sectional view of the main part modeled according to the present invention), the wiring 7 is disposed directly on the surface of the interlayer insulating film 4 with a stress relaxation layer 6 interposed therebetween. In this case, the vertical component force F3 can be absorbed and increased by the stress relaxation layer 6, so that the parallel component force F2 can be reduced by an amount corresponding to the increase in the vertical component force F3. That is,
The tensile stress of the wiring 7 in the wiring length direction can be reduced.

Next, a specific method for forming the semiconductor integrated circuit device constructed as described above will be briefly explained using FIGS. 4 to 9 (cross-sectional views of main parts shown for each manufacturing process).

First, an element isolation insulating film 3 is formed in an inactive region on the main surface of a semiconductor substrate 1 made of single crystal silicon. Thereafter, a semiconductor region 2 is formed in the active region of the main surface of the semiconductor substrate 1.
, and a semiconductor element (not shown) is formed.

Next, an interlayer insulating film 4 is formed over the entire surface of the substrate including the semiconductor element and the element isolation insulating film 3. As described above, the interlayer insulating film 4 is mainly formed of a silicon oxide film deposited by, for example, the CVD method.

Next, as shown in FIG. 4, a stress relaxation layer 6 and a photosensitive photoresist film 10 are sequentially formed over the entire surface of the substrate including the interlayer insulating film 4. The stress relaxation layer 6 is formed, for example, by applying a polyimide resin film by a spin coating method and then hardening it by a baking process. The photosensitive photoresist film 10 is a Si-containing photoresist film (resin film) having an etching selectivity with respect to the stress relaxation layer 6, for example, having resistance to oxygen-reactive ion etching. This photosensitive photoresist film 10 is formed by coating by spin coating and then hardening by baking.

Although the stress relaxation layer 6 and the photosensitive photoresist film 10 are basically formed in separate steps,
Both are processes for forming a resin film, and if the stress relaxation layer 6 is viewed as a photoresist film, one of the multilayer photoresist films.
This can be seen as the formation process of 3 times. That is, the step of forming the stress relaxation layer 6 is incorporated into the step of forming a photosensitive photoresist film (multilayer photoresist film), and does not increase the number of steps in the manufacturing process of a semiconductor integrated circuit device.

Next, using a well-known photolithography technique, the photosensitive photoresist film 10 is exposed and developed, and the area of the semiconductor region 2 (the area where the contact hole 5 is formed) of the photosensitive photoresist film 10 is exposed. After removal, an etching mask is formed in the remaining region of the photosensitive photoresist film 10.

Next, as shown in FIG. 5, using the photosensitive photoresist film 10 as an etching mask, a part of the stress relaxation layer 6 exposed from this etching mask is removed by etching (the pattern is transferred). , forming the connection hole 11. This etching is performed by oxygen reactive ion etching (O2-RIE). In oxygen-reactive ion etching, etching progresses while forming a SiO2 film on the surface of the photosensitive photoresist film 10 due to a reaction between Si contained in the photoresist film 10 and O2, and this SiO2 film and polyimide are bonded together. Since the etching selectivity with respect to the photoresist film 10 is high, the photosensitive photoresist film 10
The etching selectivity between the stress relaxation layer 6 and the stress relaxation layer 6 can be set high.

Next, using the stripping solution, the photosensitive photoresist film 10 described above is stripped and removed.

Next, as shown in FIG. 6, using the stress relaxation layer 6 as an etching mask, the interlayer insulating film 4 is removed by etching within the region defined by the connection hole 11, and the semiconductor region 2 is removed. A connecting hole 5 is formed in which the surface of the connecting hole 5 is exposed. For the etching, reactive ion etching (RIE) using, for example, CF4-based gas is used.

Next, as shown in FIG. 7, the semiconductor region 2 exposed from inside the connection hole 5 is formed on the remaining region of the stress relaxation layer 6.
A wiring layer 7 is formed over the entire surface of the substrate including the main surface thereof. As described above, the wiring layer 7 is formed using an aluminum film or an aluminum alloy film and is deposited by sputtering.

Next, a photosensitive photoresist film 12 is formed on the entire surface of the substrate including the wiring layer 7 by using a spin coating method and hardened by a baking process. Thereafter, a wiring pattern is transferred to this photosensitive photoresist film 12 using a well-known photolithography technique, and it is formed as an etching mask.

Next, as shown in FIG. 8, using the photosensitive photoresist film 12 as an etching mask, a part of the wiring layer 7 is removed by etching, and the wiring 7 is formed in the remaining area of the wiring layer 7. Form. This etching uses, for example, reactive ion etching using a Cl2-based gas.

Next, as shown in FIG. 9, the photosensitive photoresist film 1 used as an etching mask on the wiring 7 is
At the same time, the stress relaxation layer 6 except under the wiring 7 (in the area other than the wiring 7) is removed (patterned). The removal of the photosensitive photoresist film 12 and the stress relaxation layer 6 are performed using, for example, oxygen-reactive ion etching.

Thereafter, a final protective film 8 is formed over the entire surface of the substrate including the wiring 7, thereby completing the semiconductor integrated circuit device shown in FIG. As the final protective film 8, a silicon nitride film deposited by the plasma CVD method is used as described above.

In this way, the interlayer insulating film (base insulating film) 4
The wiring 7 formed on the top, which has a single layer structure mainly made of an aluminum film or an aluminum alloy film, is formed by plasma CVD.
In a semiconductor integrated circuit device coated with an inorganic final protective film 8 deposited by a method, the wiring 7 and the interlayer insulating film 4 have lower hardness than either the wiring 7 or the interlayer insulating film 4. A stress relief layer 6 is interposed. With this configuration,
In the semiconductor integrated circuit device, the stress (tensile stress) acting in the wiring length direction of the wiring 7 is absorbed by the stress relaxation layer 6 based on the expansion of the inorganic final protective film 8 deposited by the plasma CVD method, and the wiring Since the stress migration resistance of the wiring 7 can be improved, disconnection defects and damage to the wiring 7 can be prevented.

In the method for forming a semiconductor integrated circuit device, the step of forming an interlayer insulating film (base insulating film) 4 on the entire surface of the semiconductor substrate 1 including the main surface thereof, and , a stress relaxation layer 6 having lower hardness than the interlayer insulating film 4 and made of an organic material (polyimide resin film).
and a step of forming a photosensitive photoresist film 10 having an etching selectivity with respect to the stress relaxation layer 6 and having photosensitivity on the entire surface of the stress relaxation layer 6; A part of the film 10 is removed by photolithography, and using the other part of the photosensitive photoresist film 10 as an etching mask, a part of the stress relaxation layer 6 is removed by etching to form a connection hole 11. After this, a step of removing the other region of the photosensitive photoresist film 10 used as the etching mask, and using the other region of the stress relaxation layer 6 as an etching mask, the interlayer insulating film 4 is removed. a step of removing a part of the region to form a contact hole 5; and a step of removing a semiconductor region formed in the semiconductor substrate 1 exposed from the contact hole 11 and the contact hole 5 on the other region of the stress relaxation layer 6; A step of forming a wiring layer 7 made of an aluminum film or an aluminum alloy film on the entire surface of the substrate including both the main surfaces of or a process of forming a photosensitive photoresist film 12 having an etching selectivity close to that, and using this photosensitive photoresist film 12 as an etching mask, removing other areas of the wiring layer 7 by etching, and removing the wiring layer 7 by etching. A step of forming the wiring 7 in a part of the remaining region of the layer 7, removing the photosensitive photoresist film 12, and removing the other region of the stress relaxation layer 6 except under the wiring 7; A step of forming a stress relaxation layer 6 remaining only under the wiring 7, and a step of plasma CV over the entire surface of the substrate including the top of the wiring 7.
and a step of forming a final inorganic protective film 8 deposited by method D. With this configuration, a photosensitive photoresist film 10 for patterning connection holes 5 formed in the interlayer insulating film 4 is formed, and a stress relaxation layer 6 is also formed (
A stress relaxation layer 6 is formed as a part of a layer of a multilayer resist film), and a part of the stress relaxation layer 6 is removed using the photosensitive photoresist film 10 as an etching mask, and changed to the photosensitive photoresist film 10. Then, using the other region of this stress relaxation layer 6 as an etching mask, a contact hole 5 is formed in the interlayer insulating film 4, and then a photosensitive photoresist film (etching mask) 12 for patterning the wiring 7 is formed. Since the stress relaxation layer 6 remained only under the wiring 7 during the removal, the process of forming the stress relaxation layer 6 was incorporated into each of the process of forming the connection hole 5 and the process of removing the etching mask of the wiring 7. The number of steps in the manufacturing process of a semiconductor integrated circuit device can be reduced by the amount equivalent to the formation process of .

Further, the other region of the stress relaxation layer 6 is as follows:
Since patterning is performed using the wiring 7 as an etching mask, the stress relaxation layer 6 is formed only under the wiring 7 in self-alignment with the wiring 7.

(Embodiment 2) This embodiment 2 is a second embodiment of the present invention in which the wiring of a semiconductor integrated circuit device is constructed with a laminated structure, or the step coverage in the connection hole portion of the wiring is improved. be.

A schematic configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention is shown in FIG. 10 (cross-sectional view of main parts).

Wiring 7 of the semiconductor integrated circuit device of Example 2
As shown in FIG. 10, the lower MoSi2 film 7A,
Intermediate layer aluminum alloy film 7B, upper layer MoSi2
It has a three-layer structure in which the films 7C are sequentially laminated. The lower MoSi2 film acts as a barrier metal film that prevents mutual diffusion of Si atoms in the semiconductor region 2 and Al atoms in the intermediate aluminum alloy film 7B. Upper Mo
The Si2 film 7C reduces the reflectance of light and is used during the development of a photoresist film (corresponding to the photosensitive photoresist film 12 in Example 1) in the photolithography process for forming a patterning mask for the wiring 7. Pattern changes due to diffraction phenomena can be reduced. Also,
This upper layer MoSi2 film 7C covers the surface of the intermediate layer aluminum alloy film 7B, and can reduce the occurrence of aluminum hillocks on the surface.

Further, in the connection hole 5 connecting each of the wiring 7 and the semiconductor region 2, for example, W (tungsten) 13 deposited by selective CVD is buried. The W 13 embedded in the connection hole 5 can reduce the step shape formed by the connection hole 5 and improve the step coverage of the wiring 7, thereby further reducing disconnection defects in the wiring 7.

Furthermore, in the present embodiment 2 and the above-mentioned embodiment 1, the stress relaxation layer 6 formed under the wiring 7 is coated by a spin coating method, and is coated in the area of the contact hole 5 formed in the interlayer insulating film 4. Even if a step occurs in an area other than the above, the surface can be flattened, and disconnection defects in the wiring 7 can be further reduced.

Note that the MoSi2 film 7A below the wiring 7 may be replaced with a barrier metal layer such as TiN or TiW.

[0052] As described above, the invention made by the present inventor is as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, it goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof.

For example, in the present invention, the interlayer insulating film 4 itself, which is the base insulating film of the wiring 7, may be formed of an organic polyimide resin film and may be used as a stress relaxation layer.

Furthermore, the present invention is not limited to semiconductor integrated circuit devices, but can be applied to so-called wiring boards, such as printed wiring boards using epoxy resin as a substrate, and motherboards using single crystal silicon as a substrate.

[0055]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device in which wiring formed on a base insulating film is covered with an inorganic insulating film deposited by plasma CVD, disconnection defects or damage to the wiring can be reduced.

In the semiconductor integrated circuit device, the number of steps in the manufacturing process can be reduced.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of main parts showing a schematic configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is an enlarged sectional view of main parts modeling a conventional semiconductor integrated circuit device.

FIG. 3 is an enlarged sectional view of a main part modeling the semiconductor integrated circuit device of the present invention.

FIG. 4 is a sectional view of a main part in a first step for explaining the method for forming the semiconductor integrated circuit device.

FIG. 5 is a sectional view of main parts in a second step.

FIG. 6 is a sectional view of main parts in the third step.

FIG. 7 is a sectional view of main parts in the fourth step.

FIG. 8 is a sectional view of main parts in the fifth step.

FIG. 9 is a sectional view of main parts in the sixth step.

FIG. 10 is a sectional view of a main part showing a schematic configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Semiconductor region, 4... Interlayer insulating film (base insulating film), 5... Connection hole, 6... Stress relaxation layer, 7... Wiring,
8... Final protective film, 10, 12... Photosensitive photoresist film, 13... W (buried layer).

Claims (3)

[Claims] Claim 1: In a semiconductor integrated circuit device in which a wiring having a single-layer structure or a multi-layer structure mainly made of metal or alloy formed on a base insulating film is covered with an inorganic insulating film deposited by a plasma CVD method. A semiconductor integrated circuit device, characterized in that a stress relaxation layer having a lower hardness than both the wiring and the underlying insulating film is interposed between the wiring and the underlying insulating film. 2. The semiconductor integrated circuit device according to claim 1, wherein the stress relaxation layer is formed only under the wiring and is made of polyimide resin. 3. A step of forming a base insulating film on the entire surface of the substrate including on the main surface of the semiconductor substrate or on the lower layer wiring arranged on the main surface of the semiconductor substrate, and the step of forming a base insulating film on the entire surface of the base insulating film, Forming an organic first resin film having a hardness lower than that of the base insulating film, and having an etching selectivity with respect to the first resin film over the entire surface of the first resin film and having photosensitivity. a step of forming a second resin film;
A part of the resin film is removed using a photolithography technique, and using the other part of the second resin film as an etching mask, a part of the first resin film is removed by etching to form a first opening. After this, a step of removing the other region of the second resin film used as the etching mask, and using the other region of the first resin film as an etching mask,
a step of removing a part of the base insulating film to form a second opening;
A single layer structure or a laminated structure mainly made of metal or alloy is applied to the entire surface of the substrate, including both a part of the main surface of the semiconductor substrate exposed through the opening and the second opening, or a part of the lower wiring layer. a step of forming a wiring layer; a step of forming an etching mask having an etching selectivity the same as or close to that of the first resin film in a part of the wiring layer; and a step of forming the wiring layer using the etching mask. A step of removing other regions by etching and forming wiring in a part of the remaining region of the wiring layer, and removing the etching mask and etching other parts of the first resin film except under the wiring. a step of removing the area and forming a stress relaxation layer with the first resin film remaining under the wiring; and a step of forming an inorganic insulating film deposited by plasma CVD on the entire surface of the substrate including on the wiring. A method for forming a semiconductor integrated circuit device, comprising: