JPH10313052A - Method for forming wiring of semiconductor device and wiring structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming the wiring of a semiconductor device, in which any margin region for positioning is dispensed with, and a plug capable of satisfactory ohmic contact is formed. SOLUTION: This wiring forming method includes a wiring layer forming step for forming wiring layers 42, 44, and 46 on a substrate, plug forming layer forming step for forming a plug-forming layer 48 connected with the wiring layer on the wiring layer, wiring patterning process for patterning the plug- forming layer and the wiring layer according to a prescribed wiring pattern, and forming a wiring 57 having the plug-forming layer at the upper part, and plug-forming process for patterning the plug-forming layer according to a prescribed plug pattern, and forming a plug 59 conducted with the wiring on the wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device and a wiring structure, and more particularly, to a method for forming a wiring and a wiring structure of a semiconductor device for forming a wiring with high density and high reliability. It is.

[0002]

2. Description of the Related Art With the increasing integration and density of semiconductor devices, the wiring technology of semiconductor devices is increasingly moving toward miniaturization and multi-layering, and more and more in the manufacturing process technology of semiconductor integrated circuits. It is occupying a large proportion. In order to increase the number of layers, a multilayer wiring structure becomes important, and a method of connecting upper and lower wiring layers with a plug via an interlayer insulating film is often used.

Here, a conventional plug forming method will be described with reference to FIGS. 7 and 8. FIG. First, as shown in FIG. 7A, an Al or Al alloy layer 14 and a TiN /
A laminated film with the antireflection film 16 made of Ti is formed as a first metal wiring layer. Next, as shown in FIG. 7B, an interlayer insulating film 18 is formed on the antireflection film 16. Further, as shown in FIG. 7C, a resist film 20 is formed on the interlayer insulating film 18, and the resist film 20 is patterned by photolithography so as to have a desired plug pattern. Next, as shown in FIG. 7D, using the patterned resist film 20 as a mask,
8 is etched to form a contact hole 22.
The resist film 20 is removed. Next, as shown in FIG. 8E, an adhesion layer 24 made of TiN is formed on the entire surface of the substrate by sputtering. Next, as shown in FIG.
A blanket tungsten film 26 is formed on the entire surface of the substrate by the CVD method. Subsequently, as shown in FIG. 8G, the tungsten plug 28 is formed in the contact hole 22 by etching back to the interlayer insulating film 18. Further, FIG.
As shown in (h), an Al or Al alloy layer 30 is formed thereon.
A laminated film of and an antireflection film 32 made of TiN / Ti is formed as a second metal wiring layer, and is patterned to form a predetermined wiring.

[0004]

By the way, the multilayer wiring structure by the conventional plug forming method has the following problems. First, when forming a contact with the first wiring in the lower layer, a margin area much larger than the cross section of the plug as shown in FIG. A was formed as a contact portion, and a contact hole and a plug had to be formed in the region A. For this reason, in recent years, with the miniaturization of the semiconductor device, it is necessary to reduce the wiring interval. However, the wiring interval d is reduced by the margin area A secured for the contact in consideration of the alignment margin. There was a problem that it was not possible. Second, in the conventional plug formation process, after forming the first metal wiring layer and the interlayer insulating film, a contact hole for forming a plug is formed through the interlayer insulating film. Next, Ti and TiN which are to be adhesion layers are formed by sputtering. For this reason, when a film that easily absorbs moisture or degassed, for example, an SOG film is used as the interlayer insulating film, the interlayer insulating film is not sputtered when the adhesion layer is sputtered unless sufficient curing, capping, and post-treatment are performed. As shown in FIG. 10A, a defect (Poisoned Via) B is generated in the adhesion layer, and the adhesion layer is not normally deposited on the wall of the contact hole. Therefore, C
When a blanket tungsten film is formed by the VD method, as shown in FIG. 10B, it is difficult to completely fill the contact holes, and voids C are generated, so that a good plug cannot be formed. Therefore, there has been a problem that ohmic contact resistance cannot be obtained.

Accordingly, an object of the present invention is to provide a wiring forming method which does not require a margin region for alignment between a wiring and a contact hole and can form a plug exhibiting good ohmic contact resistance. is there.

[0006]

In the course of studying means for solving the above-mentioned problems, the present inventor has replaced the conventional method of forming a contact hole in the interlayer insulating film with a method prior to the formation of the interlayer insulating film. The idea of forming a wiring structure composed of a wiring and a plug integrally by etching, thereafter forming an interlayer insulating film, and embedding the wiring structure in the interlayer insulating film was conceived. According to this, since the alignment between the wiring and the contact hole is not required, the margin between the wirings can be reduced by omitting the margin area for the alignment, and since there is no need to form an adhesion layer in the contact hole, Good ohmic contact can be realized.

In order to achieve the above object, based on the knowledge obtained, a wiring forming method for a semiconductor device according to the present invention provides a wiring layer forming step of forming a wiring layer on a substrate, and connecting to the wiring. Forming a plug forming layer for forming a plug on the wiring layer; forming a plug forming layer on the wiring layer; and patterning the plug forming layer and the wiring layer according to a predetermined wiring pattern to form a wiring having the plug forming layer thereon. And a plug forming step of patterning a plug formation layer on the wiring in accordance with a predetermined plug pattern and forming a plug electrically conductive to the wiring on the wiring.

[0008] The material constituting the wiring layer and the plug forming layer is not limited, and for example, Al or an Al alloy can be used. Further, after the wiring layer forming step and before the plug forming layer forming step, a barrier metal layer may be formed on the wiring layer. According to the above configuration, a contact integrated with the wiring can be formed by etching the stacked structure of the wiring layer and the plug forming layer, instead of the conventional plug contact of the contact hole buried type, so that the margin area for alignment can be reduced. There is no need to anticipate, and wiring can be arranged at a higher density than in the past. Further, since no contact hole is formed in the interlayer insulating film, there is no need to form an adhesion layer, and the conventional Poisoned Via does not occur.

[0009] Further, following the plug forming step, an interlayer insulating film is formed on the substrate, an interconnect insulating film forming step of embedding wirings and plugs in the interlayer insulating film, and the interlayer insulating film is polished. The step of exposing the top of the plug from the interlayer insulating film while planarizing and the step of forming another wiring layer connected to the top of the plug on the plug and the interlayer insulating film may be performed. Thereby, a highly reliable multilayer wiring structure can be formed.

In addition, before the step of forming an interlayer insulating film following the plug formation step, a step of forming a barrier metal layer over the entire surface of the substrate, and a step of forming a barrier metal layer between wirings on the substrate. And removing by etching. Accordingly, metal diffusion from the wiring layer and the plug can be suppressed, and a more reliable multilayer wiring structure can be formed. For polishing the interlayer insulating film, for example, a CMP method is used.

[0011]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings by way of examples. Embodiment 1 This embodiment is an embodiment of a wiring forming method according to the present invention for a semiconductor device. FIGS. 1A to 1D, FIGS. 2E to 2H, and FIGS. 3I to 3H respectively show cross sections of the wiring structure in each step of the wiring forming method of the present embodiment. FIG. First Step In this embodiment, first, as shown in FIG.
0, a first barrier metal layer 42 made of a Ti / TiN / Ti film, a first Al alloy layer 44 made of an Al-Cu alloy or an Al-Si-Cu alloy, and a second barrier metal layer made of a Ti / TiN / Ti film 46, Al-Cu alloy or Al-
A plug forming layer 48 made of a Si—Cu alloy and TiN /
The first wiring layer 52 is formed as a laminated film of the antireflection film 50 made of a Ti film. Second Step Next, as shown in FIG. 1B, an inorganic film, for example, a TEOS film 54 is formed on the antireflection film 50. Third Step Further, as shown in FIG. 1C, a resist film 56 is applied on the TEOS film 54, and a mask pattern of the resist film 56 having a desired plug pattern is formed by photolithography. Fourth Step Next, as shown in FIG. 1D, using the patterned resist film 56 as a mask, T
The EOS film 54 is patterned to form an inorganic mask 54 having a desired plug pattern. After patterning, the resist film 56 is removed.

[0012] The fifth step Next, as shown in FIG. 2 (e), another resist film 58
Is formed and patterned to form a mask pattern of another resist film 58 having a desired wiring pattern and covering the TEOS film 54. Sixth Step Next, as shown in FIG. 2F, the first wiring layer 52, that is, the antireflection film 50, the plug forming layer 48, the second barrier metal 46, and the first Al are formed using another resist film 58 as a mask. Etching the alloy layer 44 and the first barrier metal layer 42,
The remaining portion 55 is formed as a first stage contact plug structure. Subsequently to the seventh step , another resist film 58 is removed, and further, FIG.
As shown in (g), the antireflection film 50 and the plug formation layer 48 are etched using the TEOS film 54 as a mask.
As a result, the wiring 57 including the first barrier metal layer 42, the first Al alloy layer 44, and the second barrier metal layer 46,
A plug 59 is formed by etching the plug forming layer 48. Eighth step Next, as shown in FIG.
An S film 60 is formed. The P-TEOS film 60 is
In addition, diffusion of Al from the plug 59 can be prevented.

Ninth Step Further, as shown in FIG. 3I, an interlayer insulating film 62 is formed on the P-TEOS film 60 by using an SOG film (inorganic or organic). Subsequently to the tenth step , as shown in FIG. 3J, the interlayer insulating film 62, the P-TEOS film 60, and the TEO of the inorganic mask are formed by the CMP method.
The substrate surface is flattened while polishing the S film 54 and the antireflection film 50, and the top of the plug 59 made of Al alloy is exposed. Eleventh Step Next, a barrier metal layer 64 made of a Ti / TiN / Ti film, a second Al alloy layer 66 and a TiN / Ti
Wiring layer 7 as a laminated film of an anti-reflection film 68 made of
0 is formed.

In this embodiment, since the contact plug and the wiring layer are formed as an integrated etched body, it is not necessary to secure a margin area in consideration of misalignment as in the prior art. As shown in the figure, the wiring interval can be reduced as compared with the related art in FIG. 9, and the degree of integration of the wiring structure can be increased. Further, since the contact hole is not opened, it is not necessary to form an adhesion layer in the contact hole, and an ohmic contact can be formed.

Embodiment 2 This embodiment is another embodiment of the wiring forming method according to the present invention. In the present embodiment, as in the first embodiment, FIG.
To (d) and FIGS. 2 (e) to (g), up to the seventh step. FIGS. 5A to 5C and FIGS. 6D to 6F are cross-sectional views of the wiring structure in each step of the wiring forming method of the present embodiment, and FIG.
It is a figure following (g). Eighth step Next, as shown in FIG. 5 (a), Ti, TiN or Ti
ON is continuously sputtered to form a barrier metal layer 80 made of a Ti / TiN film on the entire surface of the substrate including the side surfaces of the first wiring layer 57 and the plug 59. Ninth Step Next, as shown in FIG. 5B, a resist film 82 is applied to the entire surface of the substrate, and the resist is formed so as to have a mask pattern for exposing the barrier metal layer 80a between the wirings on the substrate. The film 82 is patterned. Subsequently to the tenth step , as shown in FIG. 5C, the barrier metal layer 80a on the substrate at the bottom of the opening is etched by dry etching using the patterned resist film 82 as a mask. As a result, electrical disconnection between the wirings is ensured, so that no short circuit occurs between the wirings. Next, the resist film 82 is removed, and the remaining barrier metal layer 80 is exposed.

Eleventh step Then, as shown in FIG. 6D, P-TE
An OS film 84 is formed. The P-TEOS film 60 is formed of the wiring 5
Al and diffusion from the plug 59 and the plug 59 can be prevented. Twelfth Step Further, as shown in FIG. 6E, an interlayer insulating film 86 is formed on the P-TEOS film 84 by using an SOG film (inorganic or organic). Subsequently to the thirteenth step , as shown in FIG. 6F, the interlayer insulating film 86, the P-TEOS film 84, and the barrier metal layer 8 are formed by the CMP method.
0, the substrate surface is flattened while polishing the TEOS film 54 and the antireflection film 50 of the inorganic mask, and the top of the plug 59 made of Al alloy is exposed. Next, as in the first embodiment, a second wiring layer connected to the top of the plug 59 is formed.

In this embodiment, in addition to the effects of the first embodiment, the barrier metal layers are provided on the upper and side surfaces of the wiring and on the side surfaces of the plug, so that the diffusion of Al is suppressed, and the reliability of the wiring layer and the plug is improved. It can be further improved.

[0018]

According to the present invention, a laminated film of a wiring layer and a plug forming layer for forming a plug connected to the wiring is formed, and the plug forming layer and the wiring layer are patterned according to a predetermined wiring pattern. Then, by patterning the plug formation layer according to a predetermined plug pattern, it is possible to form a plug that is electrically connected to the wiring on the wiring without expecting a margin area for alignment. This makes it possible to form a contact integrated with the wiring by etching, instead of the conventional plug contact of the contact hole buried type, and to arrange the wiring at a higher density than in the conventional case. Further, since it is not necessary to form a contact hole in the interlayer insulating film and form an adhesion layer, a contact with higher reliability than before can be formed.

[Brief description of the drawings]

FIGS. 1 (a) to 1 (d) each show Embodiment 1. FIGS.
FIG. 4 is a cross-sectional view of a wiring structure in each step of the wiring forming method of FIG.

2 (e) to 2 (h) correspond to FIG. 1 respectively.
FIG. 3D is a cross-sectional view of the wiring structure in each step of the wiring forming method according to the first embodiment, following FIG.

FIGS. 3 (i) to 3 (k) correspond to FIGS.
FIG. 6 is a cross-sectional view of a wiring structure in each step of the wiring forming method according to the first embodiment, following FIG.

FIG. 4 is a plan view of a wiring explaining an effect of the present embodiment.

FIGS. 5 (a) to 5 (c) correspond to FIGS.
FIG. 7G is a cross-sectional view of the wiring structure in each step of the wiring forming method according to the second embodiment, following FIG.

FIGS. 6 (d) to 6 (f) correspond to FIGS.
FIG. 7C is a cross-sectional view of the wiring structure in each step of the wiring forming method according to the second embodiment, following FIG.

FIGS. 7A to 7D are cross-sectional views of a wiring structure in each step of a conventional wiring forming method.

8 (e) to 8 (h) correspond to FIG. 7 respectively.
FIG. 4D is a cross-sectional view of the wiring structure in each step of the conventional wiring forming method, following FIG.

FIG. 9 is a plan view of a wiring explaining a problem of a conventional wiring forming method.

FIGS. 10A and 10B are cross-sectional views of a wiring structure for explaining another problem of a conventional wiring forming method.

[Explanation of symbols]

12 ... substrate, 14 ... Al alloy layer, 16 ... antireflection film, 18 ... interlayer insulating film, 20 ... resist film, 22 ...
... contact holes, 24 ... adhesion layers, 26 ... blanket tungsten films, 28 ... tungsten plugs, 30 ... Al alloy layers, 32 ... antireflection films, 40 ...
... Substrate, 42 ... First barrier metal layer, 44 ... 1A
l alloy layers 44, 46 ... second barrier metal layers, 48 ...
Plug forming layer, 50 antireflection film, 52 first wiring layer, 54 TEOS film, 55 remaining part, 56 resist film, 57 wiring, 58 another resist film, 59
... Plug, 60 P-TEOS film, 62 interlayer insulating film, 64 barrier metal layer, 66 second Al alloy layer, 68 antireflection film, 70 second wiring layer, 80 …
... barrier metal layer, 82 ... resist film, 84 ... P-
TEOS film, 86 ... interlayer insulating film.

Claims (5)

[Claims] A wiring layer forming step of forming a wiring layer on a substrate; a plug forming layer forming step of forming a plug forming layer for forming a plug connected to the wiring on the wiring layer; A wiring patterning step of patterning the plug formation layer and the wiring layer according to a predetermined wiring pattern to form a wiring having the plug formation layer thereon; and patterning the plug formation layer on the wiring according to the predetermined plug pattern to conduct with the wiring. Forming a plug on a wiring. A method for forming a wiring of a semiconductor device, comprising: 2. The semiconductor device according to claim 1, further comprising a step of forming a barrier metal layer on the wiring layer after the step of forming the wiring layer before the step of forming the plug formation layer. Wiring formation method. 3. An inter-layer insulating film forming step of forming an inter-layer insulating film on the substrate and embedding wirings and plugs in the inter-layer insulating film following the plug forming step, and polishing and flattening the inter-layer insulating film. 2. The method according to claim 1, further comprising: exposing a top portion of the plug from the interlayer insulating film while forming, and forming another wiring layer connected to the plug top portion on the plug and the interlayer insulating film. A method for forming a wiring of a semiconductor device. 4. A step of forming a barrier metal layer over the entire surface of the substrate before the step of forming an interlayer insulating film following the step of forming the plug, and the step of forming a barrier metal layer between the wirings on the substrate. 4. The method according to claim 3, further comprising the step of removing by etching. 5. A wiring structure of a semiconductor device, wherein a wiring and a contact plug disposed on the wiring are integrally formed by etching a laminated film of a wiring layer and a plug forming layer. A wiring structure of a semiconductor device, characterized in that the wiring structure is an etched body.