JPS60177652A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to enable to upgrade the conductive characteristics of the double-layer wiring structure of a semiconductor device by a method wherein, before the interlayer insulating film is formed, a conductor protrusion is previously disposed in upright on a connection part of the lower wiring film, where one end of the connection part of the upper and lower wiring films is to be provided, and successively, the interlayer insulating film and the upper wiring film are formed. CONSTITUTION:An SiO2 film 2 and a PSG film 7 are laminated on an Si substrate 1 to form a laminated material, an Al film 16 and an about 1,000Angstrom thick MOS film 17 are superposed on a substrate, which is the laminated material to constitute a lower wiring film 10, and an Al film 18 is formed on the lower wiring film 10. A masking 12 is performed using a resist, the Al film 18 is subjected to an etching using the MOS film 17 as a stopper and a protrusion 18a is formed. A masking is performed using a photosensitive polyimide 13, the lower wiring film 10 is etched in a prescribed pattern and after the mask 13 was removed, an interelement insulating film 14, such as an SiO2 film and so forth, is formed on the whole surface by a CVD method. The insulating film 14 is lifted off along with the resist film 12, the protrusion 18a, which is used as a connecting part, is made to expose on the same plane as the surface of the film 14, an upper wiring film 15 is formed and a double-layer wiring structure is completed. According to this constitution, even through the element is microscopically formed, the connection between the wirings is secured and no step disconnection generates in the upper wiring film.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device with good conductive characteristics in upper and lower conductive films of a multilayer wiring structure.

[Background technology]

In a semiconductor device in which an element pattern is formed on the main surface of a semiconductor substrate, there is a tendency for wiring layers to become multilayered as the element turn density increases. ) are formed in an overlapping manner via an interlayer insulating film, and each wiring film is electrically connected to each other through a through hole provided in the interlayer insulating film.

By the way, in the manufacturing method of this type of multilayer wiring structure, an interlayer insulating film is formed on the lower wiring film in a predetermined pattern shape, and after drilling necessary through holes in this interlayer insulating film, the upper wiring film is The wiring film is formed by a sputtering method or the like, and at this time, a part of the upper wiring film is protruded downward through the through hole, so that the upper and lower wiring films are directly connected at the through hole.

However, according to the inventor's study, as the diameter of the through-hole becomes smaller with the increasing integration and miniaturization of device patterns, metal particles sputtered during the formation of the upper wiring film become smaller in this method. It becomes difficult to penetrate into the interior K of the through hole, and there are problems such as poor step coverage at the stepped portion (around the through hole), resulting in increased conductive resistance or disconnection. In addition, in this manufacturing method, if the through holes are misaligned, the through holes will be formed at the edge of the lower wiring film, further worsening the step coverage described above, and in some cases, the glabella insulating film may be damaged. There is also the problem that elements on the main surface of the semiconductor substrate are damaged due to overetching.

[Purpose of the invention]

The purpose of the present invention is to ensure the contact between the upper and lower wiring films regardless of the miniaturization of the through holes, and to prevent deterioration of the wiring such as disconnection in the upper wiring film and deterioration of the leakage.
An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the conductive characteristics of a wiring structure.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, before forming the glabella insulating film, a conductive protrusion is erected in advance at the contact part on the lower wiring film, and an interlayer insulating film and an upper wiring film are formed on the protrusion, thereby making use of the through hole. This prevents various defects in the contact structure and thereby improves conductive properties.

[Example 1] FIGS. 1(A) to (Gl) show an example in which the present invention is applied to the manufacture of an MO8 field effect transistor (MOSFET).

First, as shown in the figure (AI), a field insulating film 2 and a gate insulating film 3 are formed on the main surface of a semiconductor substrate 1 made of silicon or the like, and a gate is formed with polysilicon on the gate insulating layer m3.
form. Further, a saw 2 is provided on the main surface of the substrate 1 below the gate insulating film 3. Drain regions 5 and 6 are formed, thereby configuring an MO8 type field effect transistor. A PSG film 7 is then formed on the entire surface.

Next, in the same figure (as shown in Bl, the source and drain regions are 5°6
Contact holes 8 and 9 are formed in the gate insulating film 3 and the PEG film 7 facing each other, and then a lower wiring film 10 is formed on the entire surface of the PSG film 7 by sputtering aluminum (AA') or the like. . At this time, a portion of the lower wiring film 10 is also provided in the contact holes 8 and 9 and connected to the source and drain regions 5 and 6. Further, a molybdenum (Mo) film 11 is formed on the entire surface of the lower wiring film 10.

Next, as shown in the same figure (C1), a photoresist film 12 is formed on the MO film 11 by patterning, leaving the photoresist film 12 at a portion corresponding to the contact portion, and then the Mo film 11 is etched using this as a mask. This results in
Mo (conductor) is deposited on the lower wiring film 10 of the contact portion.
A protrusion 11a is formed. Then, leaving the photoresist film 12 'fc, a material made of a material with a different removal agent (etching rate) from the photoresist, for example, a photosensitive polyimide film 13, is formed on the entire surface, and this is buttered, and this is used as a mask to form the etching layer below the photoresist. The side wiring film 10 is pattern-etched as shown in the same figure (DI).From this K, the lower wiring film 10 is formed into a predetermined pattern, and the wiring film connected to the source and drain regions 5.6 is etched. Form.

After that, the photosensitive polyimide film 13 is removed, and an interlayer insulation film 14 of SiO, PSG, etc. is then formed by CVD.
It is formed on the entire surface as shown in the figure (El) by a method or the like.

At this time, at the portion of the photoresist film 12, the interlayer insulating film 1
4 is considered to be a stage-broken state. Then, the photoresist film 12
, the interlayer insulating film thereon is removed by the so-called lift-off method as shown in FIG. If the upper wiring film 15 is patterned thereon, a multilayer wiring structure with upper and lower layers is formed as shown in the same figure (Gl), and each of the upper and lower wiring films 10 and 15 has a protrusion 11a of the Mo film. They will be electrically connected to each other as contacts.

Therefore, according to this manufacturing method, the upper and lower wiring films 10.
5 contact connections can be made, so even if the contacts are miniaturized, problems such as disconnection will not occur, and good conductive properties can be obtained.

[Embodiment 2] Figure 2+A1~(F'l indicates another embodiment of the present invention, in particular, only the contact portion is shown. In the figure,
The same parts as in FIG. 1 are given the same reference numerals.

First, in the same figure (like Al, the lower interconnection film lO is A/film 16).
After forming two layers of a Mo film 17 and a Mo film 17, an All film 18 is formed thereon. A Mo pattern film of about 1'N''t000A is sufficient.Next, a photoresist film 12 is patterned on the upper surface, and this is used as a mask to form a photoresist film 12 in the same figure (as in Bl).
18 is etched to form conductive protrusions 18a.

At this time, the Mo film 17 functions as an etching stopper for the lower All film 16 11111.

Next, as in the same figure (C1), 'photosensitive polyimide 13
After patterning and using this as a mask, the Al film 16 and Mo film 17 as the lower wiring film 10 are etched into desired patterns. After removing this photosensitive polyimide 13, an interlayer insulating film 14 such as S t O, P2O, etc. is formed on the entire surface by the CVD method as shown in the figure (D+).Then, the photoresist film 12 is removed and a The interlayer insulating film 14 is lifted off to expose the protrusion 18a of AA' on the same plane as Tfi1 on the interlayer insulating film 14 as shown in the same figure (El). Once the upper wiring film 15 is formed, the protrusion 18a of the AJ
A two-layer wiring structure consisting of the following line film 10.15 is formed with the contact portion formed as a contact portion.

According to this example, not only the same effect as the previous example can be obtained, but also the contact protrusion 18a that connects the upper and lower wiring films 10.15 to each other is formed by AJ, so it is formed as a thick film. The manufacturing process can be made easier than the previous method in which a Mo film, which is difficult to form, is used for the contact.

Here, in each of the embodiments shown in FIGS. 1 and 2, the interlayer insulating film may be formed using a bias sputtering method or an etchback method, and if these methods are used, the photoresist film must be removed (later Even if an interlayer insulating film is formed, Fig. 1 fF
The structure of i and Figure 2 (El) can be constructed.

[Effects] (1) Since a conductor protrusion is pre-erected at the contact position on the lower wiring film, and then an interlayer insulating film and an upper wiring film are formed to form a two-layer wiring structure, There is no need to form a through hole in the interlayer insulating film and fill the through hole with four materials to form a contact, and there is no need to form a through hole in the interlayer insulating film to form a contact. By preventing this, a multilayer wiring structure with good conductive properties can be obtained.

(2) Since the 2# pre-formed on the lower wiring film is connected to the upper and lower wiring films using the protrusion of the body, reliable conduction can be achieved, and through-hole formation and etching can be achieved. Since there is no membership fee for etching, it is possible to prevent damage to the main surface of the conductor substrate due to etching.

(3) Since no through holes are formed, the flatness of the contact area can be improved, and the adhesion of the upper wiring film and the passivation film formed thereon can be improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, Al and Mo are used as conductors for wiring films and contacts.
Other metals such as W, Ta, T1, etc. may be used, or metal silicide made by reacting silicon and metal may be used, and it can also be applied to a multilayer wiring structure of three or more layers. Furthermore, the present invention is not limited to application to MO8 field effect transistors, but can also be applied to bipolar transistors and other semiconductor devices.

[Application field]

In the above summary, we will mainly refer to the invention made by the present inventor, which is the field of application which is the background of the invention (monolithic type σ)
Although the description has been given of the fc case applied to a semiconductor device, the present invention is not limited thereto, and can be similarly applied to a multilayer wiring structure in a hybrid type semiconductor device.

[Brief explanation of drawings]

FIG. 1 IAI~(Gl is a sectional view of the manufacturing process of an embodiment in which the present invention is applied to the manufacturing of a MOS type semiconductor device, and FIG. 2 (A
t-(Fl is a manufacturing process cross-sectional view of a main part of another example. 1... Semiconductor substrate, 2... Field insulating film, 3...
... Gate insulating film, 4... Gate electrode, 5, 6...
sauce. Drain region, 7... PSG film, 8, 9... Contact hole, 10... Lower wiring film, 11... MoJI
#, 11a...Protrusion, 12...Photoresist, 13
... Photosensitive polyimide, 14 ... Interlayer insulating film, 15
... Upper wiring film, 16-hl film, 17.''Mo film, 1
B-hl membrane, 18a... protrusion. Figure 1 Figure 1 Figure 2 (B) (C

Claims (1)

[Claims] 1. A semiconductor having a multilayer wiring structure in which an upper wiring film and a lower wiring film, which are provided above and below the interlayer insulating film, are electrically connected via a contact portion formed through the interlayer insulating film. A method for manufacturing a device, wherein a protrusion of a conductor is erected in advance at a contact portion on a lower wiring film before forming the interlayer insulating film, and then an interlayer insulating film and an upper wiring film are sequentially formed. A method of manufacturing a semiconductor device, characterized in that: 2. The interlayer insulation R film is formed to have a thickness substantially the same as that of the protrusion of the conductor. A method for manufacturing a semiconductor device according to claim 1, which is configured to exhibit the following characteristics. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the interlayer insulating film formed on the protrusion of the two conductive bodies is removed by a lift-off method.