JPS63208249A - Manufacture of multilayer interconnection structure - Google Patents
Manufacture of multilayer interconnection structureInfo
- Publication number
- JPS63208249A JPS63208249A JP4188687A JP4188687A JPS63208249A JP S63208249 A JPS63208249 A JP S63208249A JP 4188687 A JP4188687 A JP 4188687A JP 4188687 A JP4188687 A JP 4188687A JP S63208249 A JPS63208249 A JP S63208249A
- Authority
- JP
- Japan
- Prior art keywords
- film
- photoresist
- metal
- resin film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 239000011347 resin Substances 0.000 claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 16
- 125000003118 aryl group Chemical group 0.000 claims abstract description 8
- GTDPSWPPOUPBNX-UHFFFAOYSA-N ac1mqpva Chemical compound CC12C(=O)OC(=O)C1(C)C1(C)C2(C)C(=O)OC1=O GTDPSWPPOUPBNX-UHFFFAOYSA-N 0.000 claims abstract description 5
- 150000004985 diamines Chemical class 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- -1 aminosilicon compound Chemical class 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 3
- 239000010703 silicon Substances 0.000 claims abstract description 3
- 239000002253 acid Substances 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 19
- 125000004432 carbon atom Chemical group C* 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 125000001931 aliphatic group Chemical group 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 125000000217 alkyl group Chemical group 0.000 claims description 2
- 125000001997 phenyl group Chemical group [H]C1=C([H])C([H])=C(*)C([H])=C1[H] 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 229920005575 poly(amic acid) Polymers 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 16
- 239000011229 interlayer Substances 0.000 abstract description 9
- 229920001721 polyimide Polymers 0.000 abstract description 7
- 239000004952 Polyamide Substances 0.000 abstract 1
- 229920002647 polyamide Polymers 0.000 abstract 1
- 150000000000 tetracarboxylic acids Chemical class 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 21
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 21
- 230000004888 barrier function Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 125000006158 tetracarboxylic acid group Chemical group 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HLBLWEWZXPIGSM-UHFFFAOYSA-N 4-Aminophenyl ether Chemical compound C1=CC(N)=CC=C1OC1=CC=C(N)C=C1 HLBLWEWZXPIGSM-UHFFFAOYSA-N 0.000 description 1
- CNODSORTHKVDEM-UHFFFAOYSA-N 4-trimethoxysilylaniline Chemical compound CO[Si](OC)(OC)C1=CC=C(N)C=C1 CNODSORTHKVDEM-UHFFFAOYSA-N 0.000 description 1
- VQVIHDPBMFABCQ-UHFFFAOYSA-N 5-(1,3-dioxo-2-benzofuran-5-carbonyl)-2-benzofuran-1,3-dione Chemical compound C1=C2C(=O)OC(=O)C2=CC(C(C=2C=C3C(=O)OC(=O)C3=CC=2)=O)=C1 VQVIHDPBMFABCQ-UHFFFAOYSA-N 0.000 description 1
- FXHOOIRPVKKKFG-UHFFFAOYSA-N N,N-Dimethylacetamide Chemical compound CN(C)C(C)=O FXHOOIRPVKKKFG-UHFFFAOYSA-N 0.000 description 1
- OBFQBDOLCADBTP-UHFFFAOYSA-N aminosilicon Chemical compound [Si]N OBFQBDOLCADBTP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 description 1
- 238000011534 incubation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910001258 titanium gold Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、多層配線を有する半導体装置の製造方法に関
し、特に、微細コンタクトを有する多層配線構造体の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device having multilayer wiring, and particularly to a method for manufacturing a multilayer wiring structure having fine contacts.
従来、この種の多層配線構造体の形成技術として、ポリ
イミド樹脂膜を用いるピラー法がある。Conventionally, as a technique for forming this type of multilayer wiring structure, there is a pillar method using a polyimide resin film.
従来のピラー法を簡単に説明すると、まず第2図(a)
に示されるように、第1のアルミニウム配線302上に
アルミニウム膜と、エツチングレートの異なるバリアメ
タル303が形成さ1.た基板301上に、同図(bl
に示すように第2のアルミニウム膜304を形成し、同
図(qに示すように第1と第2のアルミニウム配線30
2と304との間の電気的導通をとる部分のみにアルミ
ニウム膜を残し、ピラー305t−形成する。次に、ポ
リイミド樹脂膜306を、回転塗布し、熱処理の工程の
後、酸素プラズマ中で、同図(d)に示すようにピラー
305の表面が現れるまでポリイミド樹脂膜をエツチン
グし、同図telに示すように、公知の方法で、M2の
アルミニウム配線307を形成する。To briefly explain the conventional pillar method, first, Figure 2 (a)
As shown in FIG. 1, an aluminum film and a barrier metal 303 having different etching rates are formed on the first aluminum wiring 302. The same figure (bl
A second aluminum film 304 is formed as shown in FIG.
Pillar 305t- is formed by leaving the aluminum film only in the portion where electrical conduction is established between pillars 2 and 304. Next, a polyimide resin film 306 is spin-coated, and after a heat treatment step, the polyimide resin film is etched in oxygen plasma until the surface of the pillar 305 appears as shown in FIG. As shown in FIG. 3, an M2 aluminum wiring 307 is formed by a known method.
しかしながら上述した従来の方法では、ピラー305上
のポリイミド膜306を、ピラー表面が現れるまでエツ
チングする際に、ピラー305のない部分も同じ厚さだ
けエツチングされるため、層間絶縁特性が不均一になシ
、その結果、歩留シが悪くなるという欠点がある。However, in the conventional method described above, when the polyimide film 306 on the pillar 305 is etched until the pillar surface appears, the part without the pillar 305 is also etched to the same thickness, resulting in non-uniform interlayer insulation properties. However, as a result, there is a drawback that the yield rate becomes poor.
本発明の目的は、上記の問題点を解消し、平担な層間絶
縁膜をもつ多層配線構造体の製造方法を提供し、もって
製造歩留シの向上をはかることにある。An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a multilayer wiring structure having a flat interlayer insulating film, thereby improving the manufacturing yield.
本発明の多層配線構造体の製造方法は、半導体基板の一
主面上に第1の金属配線を形成する工程と、第1の金属
配線上に金属層を形成し、この金属層をフォトレジスト
膜を用いた選択エツチングにより、第2の金属配線との
電気的導通をとるために第1の金属配線上に選択的に設
けられた柱状金属とする工程と、該柱状金属上のフォト
レジスト膜を残存させた状態で、下記の式(11で表わ
される芳香族テトラカルボン酸二無水物と、式(2)で
表わされるジアミンと、式(3)で表わされるアミンシ
リコン化合物とを混合反応せしめることによって形成し
たポリアミド酸シリコン型中間体を含有してなる溶液を
全面に塗布し、150″0−200℃の温度で熱処理せ
しめることによって全面に樹脂膜を形成すも工程と1次
に1反応性イオンエッチングにより該樹脂膜と、上記フ
ォトレジストとのエツチングレートが等しい条件で該柱
状金属上のフォトレジスト全面が現れるまで該樹脂膜を
一様に除去する工程と、続いて、フォトレジスト膜のエ
ツチングレートが、該樹脂膜のエッチングレートよりも
大きい条件でフォトレジスト膜を除去する工程と、続い
て該樹脂膜を300℃〜450℃の温度で熱処理する工
程と第2の金属配線を形成する工程とを含でいる。The method for manufacturing a multilayer wiring structure of the present invention includes the steps of forming a first metal wiring on one main surface of a semiconductor substrate, forming a metal layer on the first metal wiring, and applying a photoresist to the metal layer. A step of forming a columnar metal selectively provided on the first metal wiring in order to establish electrical continuity with the second metal wiring by selective etching using a film, and a photoresist film on the columnar metal. An aromatic tetracarboxylic dianhydride represented by the following formula (11), a diamine represented by the formula (2), and an amine silicon compound represented by the formula (3) are mixed and reacted while leaving the A solution containing the polyamic acid silicon type intermediate formed by this process is applied to the entire surface, and a resin film is formed on the entire surface by heat treatment at a temperature of 0 to 200°C for 150 cm. a step of uniformly removing the resin film by chemical ion etching under conditions where the etching rates of the resin film and the photoresist are equal until the entire surface of the photoresist on the columnar metal is exposed; a step of removing the photoresist film under conditions where the etching rate is higher than the etching rate of the resin film, followed by a step of heat-treating the resin film at a temperature of 300° C. to 450° C., and forming a second metal wiring. It includes the process.
NH,−R−NH,・・・・山・・ (2)式(1)〜
(3)において、Rは4価の炭素環式芳香族基を表わし
、R2は炭素数6〜30個の芳香脂肪族基、又は炭素数
6〜30個の炭素環式芳香族基、R3及びR4は独立に
炭素数1〜6のアルキル基又はフェニル基であυ、Kは
1≦に≦3の値である。NH, -R-NH, ... Mountain... (2) Formula (1) ~
In (3), R represents a tetravalent carbocyclic aromatic group, R2 is an aromatic aliphatic group having 6 to 30 carbon atoms, or a carbocyclic aromatic group having 6 to 30 carbon atoms, R3 and R4 is independently an alkyl group or phenyl group having 1 to 6 carbon atoms, and K has a value of 1≦ and ≦3.
次に、本発明を図面を用いてよシ詳細に説明する。本実
施例では、アミノシリコン化合物としてCHa
で表わされるP−アミノフェニルトリメトキシシランを
用い、ジアミンとして、ジアミノジフェニルエーテルを
、また、芳香族テトラカルボン酸二無水物として、ベン
ゾフェノンテトラカルボン酸二無水物を用い、P−アミ
ノフンルトリメトキシシランのモル濃度を40%とし念
。また、溶媒はジメチルアセトアミドを用い、この溶液
の粘度を300cm−poiseとした。Next, the present invention will be explained in detail using the drawings. In this example, P-aminophenyltrimethoxysilane represented by CHa was used as the amino silicon compound, diaminodiphenyl ether was used as the diamine, and benzophenonetetracarboxylic dianhydride was used as the aromatic tetracarboxylic dianhydride. The molar concentration of P-aminofurtrimethoxysilane was set to 40%. Further, dimethylacetamide was used as the solvent, and the viscosity of this solution was set to 300 cm-poise.
〔実施例1〕
第1図(al〜(h)は、本発明の第1の実施例である
2層アルミニウム配線構造体を形成する場合の工程断面
図である。[Example 1] FIGS. 1A to 1H are process cross-sectional views for forming a two-layer aluminum wiring structure according to the first example of the present invention.
第1図(a)において、半導体素子能動部が形成され、
さらに化学気相成長によるリンガラス膜102を介した
ポリシリコン電極103,103’が形成された素子基
板101の表面に、化学気相成長によるリンガラス膜1
04を形成し、公知のリソグラフィー、ドライエツチン
グによ)、同図(b)に示すようにポリシリコン電極1
03,103’ とその上に形成される第1のアルミニ
ウム配線106゜106′との電気的導通をとるための
開口105゜105’を設け、続いて、スパッタ法によ
シ厚さ約1μmのアルミニウム膜を形成し、さらにバリ
アメタルとしてスパッタ法によシ、厚さ約0.2μmの
チタン金JAMを形成し、フォトリソグラフィー。In FIG. 1(a), a semiconductor element active part is formed,
Further, on the surface of the element substrate 101 on which polysilicon electrodes 103, 103' are formed via a phosphorus glass film 102 formed by chemical vapor deposition, a phosphorus glass film 1 formed by chemical vapor deposition is applied.
04, and by known lithography and dry etching), as shown in FIG.
03, 103' and the first aluminum wiring 106, 106' formed thereon are provided with openings 105, 105', and then, by sputtering, an opening with a thickness of approximately 1 μm is formed. An aluminum film is formed, and a titanium-gold JAM with a thickness of about 0.2 μm is formed as a barrier metal by sputtering, followed by photolithography.
ドライエッチングにより、同図(C1に示すように表面
にバリアメタル107,107’i有する第1のアルミ
ニウム配線106,106’を形成する。By dry etching, first aluminum wirings 106, 106' having barrier metals 107, 107'i on their surfaces are formed as shown in FIG.
次に、スパッタ法によシ、厚工約1μmのアルミニウム
膜を形成し、フォトリソグラフィー、ドライエッチング
により、同図(dlに示されるように、第1のアルミニ
ウム配線106,106’ とその上に形成される第2
のアルミニウム配線111゜111′との間の電気的導
通をとるための、上部表面に、フォトレジスト109,
109’を有するピラー108,108’を形成する。Next, an aluminum film with a thickness of about 1 μm is formed by sputtering, and then photolithography and dry etching are applied to the first aluminum wirings 106, 106' and on top of them, as shown in FIG. The second formed
A photoresist 109,
Pillars 108, 108' having 109' are formed.
硯いて、アミンシリコン化合物とジアミンと芳香族テト
ラカルボン酸二無水物とを混合反応させ72:塗布溶液
を、2000rpmで30秒間、回転塗布し、窒素ガス
雰囲気中で200℃で30分間熱処理せしめることによ
って、同図telに示すように樹脂膜110を形成する
。The amine silicon compound, the diamine, and the aromatic tetracarboxylic dianhydride are mixed and reacted by incubation. 72: The coating solution is spin-coated at 2000 rpm for 30 seconds, and heat-treated at 200° C. for 30 minutes in a nitrogen gas atmosphere. In this way, a resin film 110 is formed as shown in tel of the figure.
次に、CF4と02の混合ガスを用いる反応性イオンエ
ツチングを用い、CF4の流量を508CCM。Next, using reactive ion etching using a mixed gas of CF4 and 02, the flow rate of CF4 was 508 CCM.
02の流量を1108CCとし、チャンバー内圧力を5
pa、印加電力を50Wとして、樹脂膜110 とフォ
トレジスト膜109,109’ とのエツチングレート
が約1000A/ m i nと、同じ条件で3分間、
フォトレジスト膜109,109’ と樹脂膜110と
の一様なエツチングを行った(同図(f))。The flow rate of 02 is 1108CC, and the pressure inside the chamber is 5.
pa, the applied power was 50 W, and the etching rate of the resin film 110 and the photoresist films 109, 109' was about 1000 A/min for 3 minutes under the same conditions.
The photoresist films 109, 109' and the resin film 110 were uniformly etched (FIG. 4(f)).
続いて、CF4の流量t−58CCM、02の流量を5
5 SCCMとし、チャンバー内圧力5pa、印加電力
50Wとして、樹脂膜110のエツチングレートが、4
00λ/m i n 、フォトレジスト109 、10
9’のエツチングレートが、1500A/minである
条件で5分間、樹脂膜110と、フォトレジスト109
゜109′とをエツチングし、108,108’ 上の
フォトレジスト109,109’を除去した同図(g)
。Next, the flow rate of CF4 is t-58CCM, and the flow rate of 02 is 58CCM.
5 SCCM, the chamber pressure is 5 pa, the applied power is 50 W, and the etching rate of the resin film 110 is 4.
00λ/min, photoresist 109, 10
The resin film 110 and the photoresist 109 were etched for 5 minutes under the condition that the etching rate of 9' was 1500 A/min.
゜109' is etched and the photoresist 109, 109' on 108, 108' is removed (g).
.
続いて、樹脂膜110を窒素ガス雰囲気中で、400℃
1時間の熱処理を加え、次に、スパッタ法により、厚工
約1μmのアルミニウム膜を形成し、フォトリソグラフ
ィー、ドライエツチングにより同図(hlに示すように
、第2のアルミニウム配線111,111’を形成する
ことによって、2層アルミニウム配線構造体が形成され
る。Subsequently, the resin film 110 is heated at 400° C. in a nitrogen gas atmosphere.
After applying heat treatment for 1 hour, an aluminum film with a thickness of approximately 1 μm is formed by sputtering, and the second aluminum wirings 111 and 111' are formed by photolithography and dry etching as shown in the same figure (hl). By forming, a two-layer aluminum wiring structure is formed.
〔実施例2〕
次に、第λの実施例として、第1の実施例で述べた多層
配線構造体の製造方法を、B i −CMU S超LS
Iに適用した例について説明する。Bi−0MO8超L
SIは3層kl配線を有し、その配線ピッチは、1層目
が2.5μm、2層目が3.5μm、3層目が4.5μ
mである。第1図fal〜(hlに示した製造方法で1
層目配線と2層目配線間の層間膜および2層目配線と3
層目配線間の層間膜を形成した。[Example 2] Next, as a λ-th example, the method for manufacturing the multilayer wiring structure described in the first example is applied to a B i -CMUS super LS
An example applied to I will be explained. Bi-0MO8 super L
SI has three-layer KL wiring, and the wiring pitch is 2.5 μm in the first layer, 3.5 μm in the second layer, and 4.5 μm in the third layer.
It is m. Figure 1 fal ~ (1 by the manufacturing method shown in hl)
Interlayer film between layer wiring and second layer wiring and second layer wiring and 3
An interlayer film was formed between the wiring layers.
本発明の有効性を示すために本発明の多層配線形成法に
より形成したB i −CMOS超LSIと、従来の多
層配線形成法によシ形成したBi−0MO8超LSIと
を作成し、比較した。表1はこれら2つのBi−0MO
8超LSI装置の歩留9および2000時間の信頼性試
験後の良品率を示す。歩留シおよび良品率共に本発明に
よる製造方法の万が、従来の方法よりも優れていること
がわかる。このことは、本発明の利点、すなわちピラー
形成時に層間絶縁特性が均一であることに基づくもので
るる。In order to demonstrate the effectiveness of the present invention, a Bi-CMOS VLSI formed by the multilayer wiring formation method of the present invention and a Bi-0MO8 VLSI formed by the conventional multilayer wiring formation method were created and compared. . Table 1 shows these two Bi-0MO
8 shows the yield of 9 and the non-defective rate after a 2000 hour reliability test for an 8-super LSI device. It can be seen that the manufacturing method according to the present invention is superior to the conventional method in both yield and quality. This is based on the advantage of the present invention, that is, the interlayer insulation properties are uniform during pillar formation.
以上説明したように、本発明は、ピラー上にフォトレジ
スト膜を残存させ、かつ層間膜にSiO成分を含有した
ポリイミド膜を用いるため、フォトレジスト除去時に、
樹脂層間膜の目減シを防ぐことが可能となる。従って、
歩留りが高く、かつ信頼性の優れた多層配線構造体を形
成することが可能となる。すなわち、本発明は集積回路
装置の高集積化に多大な効果をもたらす。As explained above, in the present invention, since a photoresist film remains on the pillar and a polyimide film containing an SiO component is used as an interlayer film, when the photoresist is removed,
It becomes possible to prevent the resin interlayer film from becoming thinner. Therefore,
It becomes possible to form a multilayer wiring structure with high yield and excellent reliability. That is, the present invention has a great effect on increasing the degree of integration of integrated circuit devices.
第1図(al〜(hlは、本発明に基づく第1の実施例
である2層アルミニウム配線構造体を形成する場合の工
程断面図である。
101・・・・・・素子基板、102・・・・・・リン
ガラス膜、103.103’・・・・・・ポリシリコン
電極、104・・・・・・リンガラス膜、105,10
5’・・・・・・開口、106.106’・・・・・・
第1のアルミニウム配線、107.107’・・・・・
・バリアメタル、108,108’・・・・・・ピラー
、109,109’・・・・・・フォトレジスト、11
0・・・・・・樹脂膜、111,111’・・・・・・
第2のアルミニウム配線。
第2図(al〜(e)は、従来のピラー法による2層ア
ルミニウム配線構造体を形成する場合の工程断面図であ
る。
301・・・・・・基板、302・・・・・・第1のア
ルミニウム配線、303・・・・・・バリアメタ/l/
、304・・・・・・アルミニウム膜、305・・・・
・・ピラー、306・川・・ポリイミド樹脂膜、307
・・・・・・第2のアルミニウム配線。FIG. 1 (al to (hl) are process cross-sectional views when forming a two-layer aluminum wiring structure according to the first embodiment of the present invention. 101... Element substrate, 102... ...Phosphorus glass film, 103.103'...Polysilicon electrode, 104...Phosphorus glass film, 105,10
5'...Opening, 106.106'...
First aluminum wiring, 107.107'...
・Barrier metal, 108, 108'... Pillar, 109, 109'... Photoresist, 11
0... Resin film, 111, 111'...
Second aluminum wiring. 2(al) to (e) are process cross-sectional views when forming a two-layer aluminum wiring structure by the conventional pillar method. 301...Substrate, 302...... 1 aluminum wiring, 303...barrier metal/l/
, 304... Aluminum film, 305...
・・Pillar, 306・River・・Polyimide resin film, 307
...Second aluminum wiring.
Claims (1)
と、該第1の金属配線上に金属膜を形成し、この金属膜
をフォトレジストを用いた選択エッチングによりエッチ
ングして前記第1の金属配線上に選択的に柱状金属を形
成する工程と、該柱状金属上の前記フォトレジスト膜を
残存させたまま下記の式(1)で表わされる芳香族テト
ラカルボン酸二無水物と、式(2)で表わされるジアミ
ンと、式(3)で表わされるアミノシリコン化合物とを
混合反応せしめることによって形成したポリアミド酸シ
リコン型中間体を含有してなる溶液を塗布し、150℃
〜200℃の温度で熱処理せしめることによって樹脂膜
を全面に形成する工程と、次に反応性イオンエッチング
により該樹脂膜と、前記フォトレジストとのエッチング
レートが等しい条件で前記フォトレジスト表面が現れる
まで前記樹脂膜をエッチングし、続いて前記フォトレジ
スト膜のエッチングレートが前記樹脂膜のエッチングレ
ートよりも小さい条件のエッチングで前記フォトレジス
ト膜を除去する工程と、前記樹脂膜を300℃〜400
℃の温度で熱処理する工程と、前記樹脂膜上に前記柱状
金属の表面と接触する第2の金属配線を形成する工程と
を含むことを特徴とする多層配線構造体の製造方法。 ▲数式、化学式、表等があります▼・・・・・・・・・
(1) NH_2−R^2−NH_2・・・・・・・・・(2) ▲数式、化学式、表等があります▼・・・・・・・・・
(3) 式(1)〜(3)において、R^1は4価の炭素環式芳
香族基を表わし、R^2は炭素数6〜30個の芳香脂肪
族基、又は炭素数6〜30個の炭素環式芳香族基、R^
3及びR^4は独立に炭素数1〜6のアルキル基又はフ
ェニル基であり、Kは、1≦K≦3の値である。[Claims] A step of forming a first metal wiring on one main surface of a semiconductor substrate, forming a metal film on the first metal wiring, and selectively etching the metal film using a photoresist. selectively forming a columnar metal on the first metal wiring by etching, and an aromatic tetracarbon represented by the following formula (1) while leaving the photoresist film on the columnar metal. A solution containing a polyamic acid silicon type intermediate formed by a mixed reaction of an acid dianhydride, a diamine represented by formula (2), and an aminosilicon compound represented by formula (3) is applied. , 150℃
A process of forming a resin film on the entire surface by heat treatment at a temperature of ~200°C, and then reactive ion etching until the photoresist surface appears under conditions where the etching rate of the resin film and the photoresist is equal. etching the resin film and then removing the photoresist film by etching under conditions where the etching rate of the photoresist film is smaller than the etching rate of the resin film;
A method for manufacturing a multilayer wiring structure, comprising the steps of: heat-treating at a temperature of °C; and forming a second metal wiring on the resin film in contact with the surface of the columnar metal. ▲There are mathematical formulas, chemical formulas, tables, etc.▼・・・・・・・・・
(1) NH_2-R^2-NH_2・・・・・・・・・(2) ▲There are mathematical formulas, chemical formulas, tables, etc.▼・・・・・・・・・
(3) In formulas (1) to (3), R^1 represents a tetravalent carbocyclic aromatic group, and R^2 represents an aromatic aliphatic group having 6 to 30 carbon atoms, or an aromatic aliphatic group having 6 to 30 carbon atoms. 30 carbocyclic aromatic groups, R^
3 and R^4 are independently an alkyl group having 1 to 6 carbon atoms or a phenyl group, and K has a value of 1≦K≦3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62041886A JPH0612791B2 (en) | 1987-02-24 | 1987-02-24 | Method for manufacturing multilayer wiring structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62041886A JPH0612791B2 (en) | 1987-02-24 | 1987-02-24 | Method for manufacturing multilayer wiring structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63208249A true JPS63208249A (en) | 1988-08-29 |
JPH0612791B2 JPH0612791B2 (en) | 1994-02-16 |
Family
ID=12620760
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62041886A Expired - Lifetime JPH0612791B2 (en) | 1987-02-24 | 1987-02-24 | Method for manufacturing multilayer wiring structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0612791B2 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6064451A (en) * | 1983-09-19 | 1985-04-13 | Toshiba Corp | Manufacture of semiconductor device |
JPS60177652A (en) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | Manufacture of semiconductor device |
JPS6187355A (en) * | 1984-10-05 | 1986-05-02 | Nippon Telegr & Teleph Corp <Ntt> | Forming method of multilayer wiring |
JPS61283145A (en) * | 1985-06-10 | 1986-12-13 | Nec Corp | Semiconductor device and manufacture thereof |
-
1987
- 1987-02-24 JP JP62041886A patent/JPH0612791B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6064451A (en) * | 1983-09-19 | 1985-04-13 | Toshiba Corp | Manufacture of semiconductor device |
JPS60177652A (en) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | Manufacture of semiconductor device |
JPS6187355A (en) * | 1984-10-05 | 1986-05-02 | Nippon Telegr & Teleph Corp <Ntt> | Forming method of multilayer wiring |
JPS61283145A (en) * | 1985-06-10 | 1986-12-13 | Nec Corp | Semiconductor device and manufacture thereof |
Also Published As
Publication number | Publication date |
---|---|
JPH0612791B2 (en) | 1994-02-16 |
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