JP2743366B2 - Method for manufacturing multilayer wiring structure using resin interlayer film - Google Patents

Method for manufacturing multilayer wiring structure using resin interlayer film

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Publication number
JP2743366B2
JP2743366B2 JP63052133A JP5213388A JP2743366B2 JP 2743366 B2 JP2743366 B2 JP 2743366B2 JP 63052133 A JP63052133 A JP 63052133A JP 5213388 A JP5213388 A JP 5213388A JP 2743366 B2 JP2743366 B2 JP 2743366B2
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JP
Japan
Prior art keywords
film
wiring structure
chemical vapor
vapor deposition
multilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP63052133A
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Japanese (ja)
Other versions
JPH01225339A (en
Inventor
哲哉 本間
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NEC Corp
Original Assignee
NEC Corp
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  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、樹脂層間膜を用いた多層配線構造体の製造
方法に関し、特に耐湿性が強化された樹脂層間膜を利用
した多層配線構造体の製造方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer wiring structure using a resin interlayer film, and more particularly to a multilayer wiring structure using a resin interlayer film having enhanced moisture resistance. And a method for producing the same.

〔従来の技術〕[Conventional technology]

従来、樹脂膜を層間絶縁膜として用いる多層配線は、
樹脂膜として耐熱性に優れたポリイミド樹脂すなわち芳
香族テトラカルボン酸二無水物と芳香族ジアミンとを等
モルで反応せしめることによって形成したポリアミド酸
溶液を加熱重合せしめることによって形成した膜を用い
ている。
Conventionally, multilayer wiring using a resin film as an interlayer insulating film is
As a resin film, a polyimide resin having excellent heat resistance, that is, a film formed by heating and polymerizing a polyamic acid solution formed by reacting an aromatic tetracarboxylic dianhydride and an aromatic diamine in equimolar amounts is used. .

〔発明が解決しようとする課題〕 しかしながら上述したポリイミド樹脂は、このポリイ
ミド樹脂膜上に耐湿性強化のためにパッシベーション膜
としてプラズマ化学気相成長によるシリコン窒化膜等の
無機膜を形成したときにその無機膜にクラックが発生し
たり(Semiconductor World 1986年10月号第40頁)、し
わが発生するという欠点があり、著しく耐湿性信頼性を
劣化させるという問題がある。
[Problems to be Solved by the Invention] However, when the above-described polyimide resin is formed on the polyimide resin film by forming an inorganic film such as a silicon nitride film by plasma enhanced chemical vapor deposition as a passivation film to enhance moisture resistance, Cracks are generated in the inorganic film (Semiconductor World, October 1986, p. 40) and wrinkles are generated, and there is a problem that reliability of moisture resistance is remarkably deteriorated.

本発明の目的は上記問題点を解消したすなわち耐湿性
の強化された樹脂層間膜を用いた多層配線構造体の製造
方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a multilayer wiring structure using a resin interlayer film in which the above problem is solved, that is, the moisture resistance is enhanced.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の樹脂層間膜を用いた多層配線構造体の製造方
法は、層間絶縁樹脂膜が下記の式(1)で表わされる芳
香族テトラカルボン酸二無水物と、式(2)で表わされ
るジアミンと、式(3)で表わされるアミノシリコン化
合物とを混合反応せしめることによって形成されるポリ
アミド酸シリコン型中間体を含有してなる溶液を塗布・
熱処理せしめることによって形成され、かつ、その層間
絶縁膜上に最終金属配線を選択的に形成後、300〜450℃
の温度で熱処理をし、プラズマ化学気相成長シリコン窒
化膜又はプラズマ化学気相成長シリコン酸化窒化膜又
は、プラズマ化学気相成長シリコン酸化窒化膜と、プラ
ズマ化学気相成長シリコン窒化膜との2層膜によるカバ
ー膜を形成することを特徴としている。
In the method for producing a multilayer wiring structure using a resin interlayer film according to the present invention, the interlayer insulating resin film is preferably made of an aromatic tetracarboxylic dianhydride represented by the following formula (1) and a diamine represented by the formula (2): And a solution containing a polyamic acid silicon-type intermediate formed by mixing and reacting an aminosilicon compound represented by the formula (3).
After heat treatment, and after selectively forming the final metal wiring on the interlayer insulating film, 300 ~ 450 ℃
Heat treatment at a temperature of 2 ° C., and two layers of a plasma-enhanced chemical vapor deposition silicon nitride film, a plasma-enhanced chemical vapor deposition silicon oxynitride film, a plasma-enhanced chemical vapor deposition silicon oxynitride film, and a plasma-enhanced chemical vapor deposition silicon nitride film It is characterized in that a cover film is formed by a film.

式(1)〜(3)において、R1は4価の炭素環式芳香
族基を表わし、R2は炭素数6〜30個の芳香脂肪族又は、
炭素数6〜30個の炭素環式芳香族基、R3及びR4は独立
に、炭素数1〜6のアルキル基又はフェニル基であり、
Kは1≦K≦3の値である。
In the formulas (1) to (3), R 1 represents a tetravalent carbocyclic aromatic group, and R 2 represents an araliphatic having 6 to 30 carbon atoms or
A carbocyclic aromatic group having 6 to 30 carbon atoms, R 3 and R 4 are each independently an alkyl group having 1 to 6 carbon atoms or a phenyl group,
K is a value of 1 ≦ K ≦ 3.

さらに上記のプラズマ化学気相成長シリコン窒化膜又
はプラズマ化学気相成長シリコン窒化膜はその内部応力
が圧縮応力でありその大きさが、109〜1010dyne/cm2
あることを特徴としている。
Furthermore, the above-mentioned plasma enhanced chemical vapor deposition silicon nitride film or plasma enhanced chemical vapor deposition silicon nitride film is characterized in that its internal stress is a compressive stress and its magnitude is 10 9 to 10 10 dyne / cm 2 . .

本発明によれば層間膜として用いる樹脂膜中にSiO成
分を含有せしめることによってその樹脂膜上にカバー膜
としてその内部応力が圧縮応力であり、その大きさが10
9〜1010dyne/cm2であるプラズマ化学気相成長シリコン
窒化膜又は、プラズマ化学気相成長シリコン酸化窒化膜
又は、プラズマ化学気相成長シリコン窒化膜とプラズマ
化学気相成長シリコン窒化膜との2層膜を形成したとき
にクラックやしわが発生しない。
According to the present invention, by incorporating an SiO component into a resin film used as an interlayer film, the internal stress is a compressive stress as a cover film on the resin film, and the magnitude thereof is 10%.
9 to 10 10 dyne / cm 2 of a plasma enhanced chemical vapor deposition silicon nitride film, a plasma enhanced chemical vapor deposition silicon oxynitride film, or a plasma enhanced chemical vapor deposition silicon nitride film and a plasma enhanced chemical vapor deposition silicon nitride film. Cracks and wrinkles do not occur when a two-layer film is formed.

〔実施例〕〔Example〕

次に、本発明を実施例に基づき図面を用いて説明す
る。
Next, the present invention will be described based on embodiments with reference to the drawings.

本実施例で用いた樹脂膜形成用塗布溶液はアミノシリ
コン化合物として で表わされる。P−アミノフェニルトリメトキシシラン
をジアミンとしてジアミノジフェニルエーテルを、ま
た、芳香族テトラカルボン酸二無水物として、ベンゾフ
ェノンテトラカルボン酸二無水物を用いP−アミノフェ
ニルトリメトキシシランのモル濃度を40%とした。また
溶媒としてジメチルアセトアミドを用い溶液の粘度を30
0cm・poiseとした。
The coating solution for forming the resin film used in this example was an aminosilicon compound. Is represented by Diaminodiphenyl ether was used as a diamine using P-aminophenyltrimethoxysilane, and benzophenonetetracarboxylic dianhydride was used as an aromatic tetracarboxylic dianhydride. The molar concentration of P-aminophenyltrimethoxysilane was 40%. . Also, using dimethylacetamide as a solvent, the viscosity of the solution was 30.
It was 0cm · poise.

〔実施例1〕 本実施例では、シリコン基板上に本発明に基づく樹脂
膜を形成し、その樹脂膜上にプラズマ化学気相成長シリ
コン窒化膜を形成し、クラック,しわが発生するかどう
かを調べた。なお比較としてP−アミノフェニルトリメ
トキシシランを含まないベンゾフェノンテトラカルボン
酸二無水物とジアミノジフェニルエーテルから成るポリ
イミド樹脂膜を用いた。
Example 1 In this example, a resin film based on the present invention was formed on a silicon substrate, and a plasma-enhanced chemical vapor deposition silicon nitride film was formed on the resin film to determine whether cracks and wrinkles occurred. Examined. As a comparison, a polyimide resin film containing benzophenonetetracarboxylic dianhydride and diaminodiphenyl ether without P-aminophenyltrimethoxysilane was used.

シリコン基板上に本発明に基づく樹脂膜と、ポリイミ
ド膜を同様な熱処理に加えることにより約1.5μmの膜
厚で形成し、最終熱処理を350℃,400℃,450℃で1時
間、窒素ガス雰囲気中で施しその試料上にプラズマ化学
気相成長でそのガス流量比を変えることにより、その内
部応力が圧縮応力でありその大きさを1×109〜1×10
10dyne/cm2の間で変化させ、300℃の温度で厚さ約1.0μ
mのシリコン窒化膜を形成したときのクラック,しわの
有無を調べた結果を第1表に示す。同図から本発明によ
る樹脂膜を用いた場合にはその最終熱処理温度が350℃,
400℃,450℃でさらにシリコン窒化膜の内部応力が1×1
09〜1×1010dyneの間でクラック,しわは発生しなかっ
た。しかしながらポリイミド樹脂膜の場合には、クラッ
クは発生しなかったが、しわが発生した。
A resin film based on the present invention and a polyimide film are formed on a silicon substrate to a thickness of about 1.5 μm by applying the same heat treatment, and the final heat treatment is performed at 350 ° C., 400 ° C., 450 ° C. for 1 hour in a nitrogen gas atmosphere. By changing the gas flow ratio on the sample by plasma chemical vapor deposition, the internal stress is a compressive stress, and the size is 1 × 10 9 to 1 × 10
10 dyne varied between / cm 2, about the thickness at a temperature of 300 ° C. 1.0 micron
Table 1 shows the results of examining the presence or absence of cracks and wrinkles when the m-type silicon nitride film was formed. From the figure, when the resin film according to the present invention is used, the final heat treatment temperature is 350 ° C,
At 400 ℃ and 450 ℃, the internal stress of silicon nitride film is 1 × 1
No cracks or wrinkles occurred between 09 and 1 × 10 10 dyne. However, in the case of the polyimide resin film, cracks did not occur, but wrinkles occurred.

〔実施例2〕 第1図(a)〜(g)は実施例により耐湿性強化され
た2層Al配線構造体を形成する場合の工程断面図であ
る。
Example 2 FIGS. 1A to 1G are cross-sectional views showing steps in the case of forming a two-layer Al wiring structure having enhanced moisture resistance according to an example.

第2図(a)において半導体素子能動部が形成され、
さらに化学気相成長によるリンガラス膜202を介したポ
リシリコン電極203,203′が形成された素子基板201の表
面に化学気相成長によるリンガラス膜204を形成し、公
知のリソグラフィー,ドライエッチングにより同図
(b)に示すようにポリシリコン電極と第1のアルミニ
ウム配線との電気的導通をとるための第1の開口205,20
5′を設け、続いてスパッタ法により厚さ約1μmのア
ルミニウム膜を形成し、フォトリソグラフィー,ドライ
エッチングにより同図(c)に示すように第1のアルミ
ニウム配線206,206′を形成する。次に、同図(d)に
示すように、本発明による塗布溶液を毎分2000回転で30
秒間回転塗布し、100℃で1時間、240℃で30分間さらに
400℃で1時間窒素ガス雰囲気中で熱処理し、約1.5μm
厚の樹脂膜207を形成する。続いて樹脂膜のエッチング
マスクとして約0.1μmのチタン金属膜をスパッタ法に
より形成し、公知のフォトリソグラフィー,ドライエッ
チングによりチタン金属膜と樹脂膜をエッチング後、エ
ッチングマスクとして用いたチタン金属を除去すること
によって同図(e)に示すように第1のアルミニウム配
線206,206′と、第2のアルミニウム配線との電気的導
通をとるための第2の開口208,208′を設ける。次にス
パッタ法により厚さ約1μmのアルミニウム膜を形成
し、フォトリソグラフィー,ドライエッチングにより同
図(f)に示すように第2のアルミニウム配線209,20
9′を形成することによって2層アルミニウム配線構造
体が形成される。
In FIG. 2A, a semiconductor element active portion is formed,
Further, a phosphorus glass film 204 formed by chemical vapor deposition is formed on the surface of the element substrate 201 on which the polysilicon electrodes 203 and 203 'are formed via a phosphorus glass film 202 formed by chemical vapor deposition, and the lithography and dry etching are performed in the same manner. As shown in (b), first openings 205 and 20 for establishing electrical continuity between the polysilicon electrode and the first aluminum wiring.
Then, an aluminum film having a thickness of about 1 μm is formed by sputtering, and first aluminum wirings 206 and 206 ′ are formed by photolithography and dry etching as shown in FIG. Next, as shown in FIG. 3D, the coating solution of the present invention was applied at 2000 revolutions per minute for 30 minutes.
Spin coating at 100 ℃ for 1 hour and 240 ℃ for 30 minutes
Heat treated at 400 ° C for 1 hour in nitrogen gas atmosphere, about 1.5μm
A thick resin film 207 is formed. Subsequently, a titanium metal film of about 0.1 μm is formed by a sputtering method as an etching mask for the resin film, and the titanium metal film and the resin film are etched by known photolithography and dry etching, and then the titanium metal used as the etching mask is removed. As a result, second openings 208 and 208 'for establishing electrical continuity between the first aluminum wirings 206 and 206' and the second aluminum wiring are provided as shown in FIG. Next, an aluminum film having a thickness of about 1 μm is formed by a sputtering method, and second aluminum wirings 209 and 20 are formed by photolithography and dry etching as shown in FIG.
By forming 9 ', a two-layer aluminum wiring structure is formed.

次に、樹脂膜が吸収した水分を除去するために、400
℃で15分間、窒素ガス雰囲気中で熱処理後、同図(g)
に示すようにただちにプラズマ化学気相成長により350
℃の温度で約1μmの厚さでその内部応力が圧縮応力で
あり、その大きさが3×109dyne/cm2であるシリコン窒
化膜210を形成後、フォトリソグラフィー,ドライエッ
チングによりチップ外と電気的導通をとるためのアルミ
ニウムパッド上のシリコン窒化膜を除去する。
Next, to remove moisture absorbed by the resin film,
After heat treatment in nitrogen gas atmosphere at ℃ for 15 minutes, the same figure (g)
As shown in the figure, 350
After forming a silicon nitride film 210 having a thickness of about 1 μm at a temperature of about 1 μm and a compressive stress whose size is 3 × 10 9 dyne / cm 2, it is separated from the outside of the chip by photolithography and dry etching. The silicon nitride film on the aluminum pad for electrical conduction is removed.

以上の工程により耐湿性強化された2層アルミニウム
配線構造体が形成される。
Through the above steps, a two-layer aluminum wiring structure having enhanced moisture resistance is formed.

本実施例で形成した耐湿性強化された2層アルミニウ
ム配線構造体を150℃で2気圧の飽和水蒸気中で300時間
の耐湿性試験を行ったところ、アルミニウム配線の腐食
は全くないものであった。
When the moisture resistance test was performed on the two-layer aluminum wiring structure with enhanced moisture resistance formed in this example in saturated steam at 150 ° C. and 2 atm for 300 hours, there was no corrosion of the aluminum wiring. .

カバー膜として、2×109dyne/cm2の圧縮応力を有す
るシリコン酸化窒化膜を用いた場合、シリコン酸化窒化
膜との2層膜を用いた場合にも同様な効果が得られた。
Similar effects were obtained when a silicon oxynitride film having a compressive stress of 2 × 10 9 dyne / cm 2 was used as the cover film, and when a two-layer film including the silicon oxynitride film was used.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明に基づく樹脂膜はその樹脂
膜上にその内部応力が圧縮応力であり、その大きさが10
9〜1010dyme/cm2であるプラズマ化学気相成長によるシ
リコン窒化膜、又はシリコン酸化窒化膜、又はシリコン
窒化膜とシリコン酸化窒化膜との2層膜を形成してもク
ラック,しわが発生しないため耐湿信頼性を向上できる
という効果がある。したがって、本発明によって得られ
る耐湿性強化された樹脂間膜を用いた多層配線構造体
は、高耐湿性,高信頼性を要求される半導体装置に多大
な効果をもたらす。
As described above, in the resin film according to the present invention, the internal stress is a compressive stress on the resin film, and the size thereof is 10%.
9 ~10 10 dyme / cm 2 in a plasma chemical vapor silicon nitride film due to the growth, or silicon oxynitride film, or cracks to form a two-layered film of a silicon nitride film and a silicon oxynitride film, wrinkles occur Therefore, there is an effect that the moisture resistance reliability can be improved. Accordingly, the multilayer wiring structure using the moisture-resistant interlayer resin obtained by the present invention has a great effect on a semiconductor device which is required to have high moisture resistance and high reliability.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(g)は本発明の他の実施例に基づく耐
湿性の強化された2層アルミニウム配線構造体を形成す
る場合の工程断面図である。 201……素子基板、202……リンガラス膜、203,203′…
…ポリシリコン電極、204……リンガラス膜、205,205′
……第1の開口、206,206′……第1のアルミニウム配
線、207……本発明に基づく樹脂膜、208,208′……第2
の開口、209,209′……第2のアルミニウム配線、210…
…シリコン窒化膜。
1 (a) to 1 (g) are cross-sectional views showing steps in the case of forming a two-layer aluminum wiring structure with enhanced moisture resistance according to another embodiment of the present invention. 201: Element substrate, 202: Phosphor glass film, 203, 203 '
... Polysilicon electrode, 204 ... Phosphor glass film, 205,205 '
... first opening, 206, 206 '... first aluminum wiring, 207 ... resin film based on the present invention, 208, 208' ... second
Opening, 209, 209 '... second aluminum wiring, 210 ...
... Silicon nitride film.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】層間絶縁膜が、下記の式(1)で表される
芳香族テトラカルボン酸二無水物と、式(2)で表され
るジアミンと、式(3)で表されるアミノシリコン化合
物とを混合反応せしめることによって形成されるポリア
ミド酸シリコン型中間体を含有してなる溶液を塗布・熱
処理せしめることによって形成され、続いて、該層間絶
縁樹脂膜上に最終金属配線構造体を選択的に形成後、30
0〜450℃の温度で熱処理をし、プラズマ化学気相成長シ
リコン窒化膜または、プラズマ化学気相成長シリコン酸
化窒化膜又は、プラズマ化学気相成長シリコン酸化窒化
膜と、プラズマ化学気相成長シリコン窒化膜との2層膜
によるカバー膜を形成することを特徴とする耐湿性強化
された樹脂層間膜を用いた多層配線構造体の製造方法 (式(1)〜(3)において、R1は4価の炭素環式芳香
族基を表し、R2は炭素数6〜30個の芳香族基、又は炭素
数6〜30個の炭素環式芳香族基、R3及びR4は独立に炭素
1〜6のアルキル基、又はフェニル基であり、Kは1≦
K≦3の値である。)。
1. An interlayer insulating film comprising an aromatic tetracarboxylic dianhydride represented by the following formula (1), a diamine represented by the formula (2), and an amino represented by the formula (3): It is formed by applying and heat-treating a solution containing a silicon polyamic acid type intermediate formed by mixing and reacting with a silicon compound. Subsequently, a final metal wiring structure is formed on the interlayer insulating resin film. After selective formation, 30
Heat-treated at a temperature of 0 to 450 ° C. to form a plasma-enhanced chemical vapor deposition silicon nitride film, a plasma-enhanced chemical vapor deposition silicon oxynitride film, or a plasma-enhanced chemical vapor deposition silicon oxynitride film; A method of manufacturing a multilayer wiring structure using a resin interlayer film having enhanced moisture resistance, comprising forming a cover film by a two-layer film with a film. (In the formulas (1) to (3), R 1 represents a tetravalent carbocyclic aromatic group, and R 2 represents an aromatic group having 6 to 30 carbon atoms or a carbon ring having 6 to 30 carbon atoms. R 3 and R 4 are independently an alkyl group having 1 to 6 carbon atoms or a phenyl group, and K is 1 ≦
K ≦ 3. ).
【請求項2】特許請求の範囲第1項記載の樹脂層間膜を
用いた多層配線構造体の製造方法において、前記多層配
線構造体上に形成せしめるプラズマ化学気相成長シリコ
ン窒化膜、又はプラズマ化学気相成長シリコン酸化窒化
膜はその内部応力が圧縮応力でありその大きさが109〜1
010dyne/cm2であることを特徴とする樹脂層間膜を用い
た多層配線構造体の製造方法。
2. A method of manufacturing a multilayer wiring structure using a resin interlayer film according to claim 1, wherein a plasma-enhanced chemical vapor deposition silicon nitride film formed on said multilayer wiring structure, The internal stress of a vapor-grown silicon oxynitride film is a compressive stress and its magnitude is 10 9 to 1
0 10 dyne / cm 2 , a method for manufacturing a multilayer wiring structure using a resin interlayer film.
JP63052133A 1988-03-04 1988-03-04 Method for manufacturing multilayer wiring structure using resin interlayer film Expired - Fee Related JP2743366B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63052133A JP2743366B2 (en) 1988-03-04 1988-03-04 Method for manufacturing multilayer wiring structure using resin interlayer film

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Application Number Priority Date Filing Date Title
JP63052133A JP2743366B2 (en) 1988-03-04 1988-03-04 Method for manufacturing multilayer wiring structure using resin interlayer film

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JPH01225339A JPH01225339A (en) 1989-09-08
JP2743366B2 true JP2743366B2 (en) 1998-04-22

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0555386A (en) * 1991-08-23 1993-03-05 Nec Corp Manufacture of semiconductor device
JP2757618B2 (en) * 1991-09-27 1998-05-25 日本電気株式会社 Method for manufacturing semiconductor device
US9305788B2 (en) 2012-10-29 2016-04-05 Sumitomo Electric Device Innovations, Inc. Method of fabricating semiconductor device
JP6052977B2 (en) * 2012-10-29 2016-12-27 住友電工デバイス・イノベーション株式会社 Semiconductor device and manufacturing method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5779648A (en) * 1980-11-05 1982-05-18 Sanyo Electric Co Ltd Multilayer wiring of semiconductor device
JP2561244B2 (en) * 1986-05-08 1996-12-04 日本電気株式会社 Method for manufacturing semiconductor device

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