JPH0555386A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0555386A
JPH0555386A JP23566391A JP23566391A JPH0555386A JP H0555386 A JPH0555386 A JP H0555386A JP 23566391 A JP23566391 A JP 23566391A JP 23566391 A JP23566391 A JP 23566391A JP H0555386 A JPH0555386 A JP H0555386A
Authority
JP
Japan
Prior art keywords
metal wiring
polyimide resin
film
resin film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23566391A
Other languages
Japanese (ja)
Inventor
Michio Sakurai
道雄 櫻井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23566391A priority Critical patent/JPH0555386A/en
Publication of JPH0555386A publication Critical patent/JPH0555386A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent short circuit from occurring between wirings by a method wherein a second metal wiring is formed into a laminated structure where refractory metal is used as its upper layer, and the side wall of the second metal wiring is covered with an inorganic film. CONSTITUTION:A first metal wiring 5 is formed on an insulating film 2 provided onto a semiconductor substrate 1, the first metal wiring 5 is covered with a polyimide resin film 7, and a through-hole 7 is bored in the polyimide resin film 7 so as to enable the first metal wiring layer 5 to be exposed. Then, a second metal wiring 8 of laminated structure provided with a refractory metal layer 9 as an upper layer is formed on the polyimide resin film 7, and an inorganic film 10 is formed on all the surface including the second metal wiring 8. In succession, the inorganic film 10 is removed through anisotropical etching so as to be partially left covering the side wall of the second metal wiring 8. The polyimide resin film 7 is prebaked, and then an inorganic film 11 is formed all the surface. By this setup, short circuits are prevented from occurring between the wirings 5 ands 8.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は微細配線を多層に構成し
た多層配線構造を有する半導体装置の製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multi-layer wiring structure in which fine wiring is formed in multiple layers.

【0002】[0002]

【従来の技術】従来、この種の半導体装置における層間
絶縁膜としては平坦性に有利なポリイミド樹脂膜が使わ
れている。その製造方法を図2を用いて説明する。先
ず、図2(a)のように、半導体基板21の絶縁膜上に
アルミニウム配線22を形成後、同図(b)のようにシ
リコン窒化膜23を全面に形成し、更に同図(c)のよ
うにポリイミド樹脂膜24を回転塗布し、熱処理を行
う。
2. Description of the Related Art Conventionally, a polyimide resin film, which is advantageous in flatness, has been used as an interlayer insulating film in this type of semiconductor device. The manufacturing method will be described with reference to FIG. First, as shown in FIG. 2A, after forming the aluminum wiring 22 on the insulating film of the semiconductor substrate 21, a silicon nitride film 23 is formed on the entire surface as shown in FIG. 2B, and then FIG. As described above, the polyimide resin film 24 is spin-coated and heat-treated.

【0003】次に、同図(d)のように、フォトリソグ
ラフィ技術及びドライエッチング技術を利用して前記ア
ルミニウム配線22上のポリイミド樹脂膜24にスルー
ホール24aを開口し、この上に、同図(e)のように
公知の技術でアルミニウム配線5と高融点金属膜26か
らなる第2の金属配線を形する。そして、同図(f)の
ようにP−CVD装置中でプリベークを行い前記ポリイ
ミド樹脂膜24から水分除去を行った後、P−CVD法
によりカバーのシリコン窒化膜27を形成する。以上の
ようにして多層配線構造が形成される。
Next, as shown in FIG. 3D, a through hole 24a is formed in the polyimide resin film 24 on the aluminum wiring 22 by using the photolithography technique and the dry etching technique. As shown in (e), the second metal wiring including the aluminum wiring 5 and the refractory metal film 26 is formed by a known technique. Then, as shown in FIG. 3F, after prebaking is performed in the P-CVD apparatus to remove water from the polyimide resin film 24, the silicon nitride film 27 of the cover is formed by the P-CVD method. The multilayer wiring structure is formed as described above.

【0004】[0004]

【発明が解決しようとする課題】このような従来の製造
方法では、第2の金属配線を形成した後でカバーシリコ
ン窒化膜27を形成する直前に、ポリイミド樹脂膜24
からの水分除去を行うためのプリベークを行っているた
め、図3に示すように、このプリベークで第2の金属配
線を構成するアルミニウム配線25にラテラルヒロック
25Aが生じ、配線間ショートが起こり製品歩留や信頼
性が劣化するという問題があった。本発明の目的は、第
2の金属配線におけるラテラルヒロックを防止して信頼
性を高めた半導体装置の製造方法を提供することにあ
る。
In the conventional manufacturing method as described above, the polyimide resin film 24 is formed after the second metal wiring is formed and immediately before the cover silicon nitride film 27 is formed.
Since pre-baking is performed to remove water from the metal, lateral hillocks 25A are generated in the aluminum wiring 25 that constitutes the second metal wiring by this pre-baking, and a short circuit occurs between wirings, resulting in a product step. There was a problem that retention and reliability deteriorated. An object of the present invention is to provide a method of manufacturing a semiconductor device in which lateral hillocks in the second metal wiring are prevented and reliability is improved.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板の絶縁膜上に第1の金属配線を形
成する工程と、この第1の金属配線をポリイミド樹脂膜
で被覆する工程と、このポリイミド樹脂膜に前記第1の
金属配線が露呈されるスルーホールを開口する工程と、
前記ポリイミド樹脂膜の上に少なくとも上層が耐熱性の
ある金属層で形成された積層構造の第2の金属配線を形
成する工程と、この第2の金属配線を含む全面に無機膜
を形成する工程と、この無機膜を異方性エッチングによ
り除去して第2の金属配線の側面を覆うように残す工程
と、前記ポリイミド樹脂膜に対してプリベークを行った
後、全面に無機膜を形成する工程を含んでいる。
According to a method of manufacturing a semiconductor device of the present invention, a step of forming a first metal wiring on an insulating film of a semiconductor substrate and coating the first metal wiring with a polyimide resin film. A step of forming a through hole in which the first metal wiring is exposed in the polyimide resin film,
A step of forming a second metal wiring having a laminated structure in which at least an upper layer is a heat-resistant metal layer on the polyimide resin film, and a step of forming an inorganic film on the entire surface including the second metal wiring And a step of removing this inorganic film by anisotropic etching to leave it so as to cover the side surface of the second metal wiring, and a step of prebaking the polyimide resin film and then forming an inorganic film on the entire surface. Is included.

【0006】ここで、ポリイミド樹脂膜は、一般式が
〔化1〕で表される芳香族テトラカルボン酸二無水物
と、〔化2〕で表されるジアミンと、〔化3〕で表され
るアミノシリコン化合物とを混合反応せしめることによ
って形成したポリアミド酸シリコン型中間体を含有して
なる溶液を塗布し、 150℃〜 200℃の温度で熱処理して
形成する。
Here, the polyimide resin film is represented by an aromatic tetracarboxylic dianhydride represented by the general formula [Chemical formula 1], a diamine represented by the [Chemical formula 2], and a [Chemical formula 3]. It is formed by applying a solution containing a polyamic acid silicon type intermediate formed by mixing and reacting with an aminosilicon compound, and heat treating at a temperature of 150 to 200 ° C.

【0007】[0007]

【化1】[Chemical 1]

【化2】[Chemical 2]

【化3】但し、R1 は4価の炭素環式芳香族基を表し、
2は炭素数6〜30個の炭素環式芳香族基、R3 及びR
4 は独立に炭素数1〜6のアルキル基又はフェニル基、
Kは1≦K≦3の値である。
Wherein R 1 represents a tetravalent carbocyclic aromatic group,
R 2 is a carbocyclic aromatic group having 6 to 30 carbon atoms, R 3 and R
4 are independently an alkyl group having 1 to 6 carbon atoms or a phenyl group,
K is a value of 1 ≦ K ≦ 3.

【0008】[0008]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例として2層配線構造を有す
る半導体装置の製造方法を工程順に示す図である。先
ず、図1(a)のように半導体素子能動部が形成され、
さらに化学気相成長により下地絶縁膜としてリンガラス
膜2を形成した後にポリシリコン電極3を形成し、かつ
全面に化学気相成長によるリンガラス膜4を形成する。
次いで、同図(b)のように公知のリソグラフィー、ド
ライエッチングによりポリシリコン電極3上のリンガラ
ス膜4に開口4aを設ける。続いて、同図(c)のよう
にスパッタ法により厚さ約1μmのアルミニウム膜を形
成し、これをフォトリソグラフィー、ドライエッチング
によりエッチングして第1のアルミニウム配線5を形成
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a method of manufacturing a semiconductor device having a two-layer wiring structure in the order of steps as one embodiment of the present invention. First, as shown in FIG. 1A, a semiconductor element active portion is formed,
Further, a phosphorus glass film 2 is formed as a base insulating film by chemical vapor deposition, then a polysilicon electrode 3 is formed, and a phosphorus glass film 4 by chemical vapor deposition is formed on the entire surface.
Next, as shown in FIG. 3B, an opening 4a is provided in the phosphor glass film 4 on the polysilicon electrode 3 by known lithography and dry etching. Subsequently, as shown in FIG. 3C, an aluminum film having a thickness of about 1 μm is formed by the sputtering method, and the first aluminum wiring 5 is formed by etching the aluminum film by photolithography and dry etching.

【0009】次に、同図(d)のように、密着性改善の
ために、N2 ・NH3 ・SiH4 の混合ガスを用いるP
−CVD法を用い、N2 の流量を1SLM 、NH3 の流量
を 300SCCM、SiH4 の流量を0.87SLM とし、圧力を0.
36TOW 、温度を 300℃、印加電圧を1KWとして膜厚1500
Åのシリコン窒化膜6を形成する。更に、アミノシリコ
ン化合物とジアミンと芳香族テトラカルボン酸二無水物
とを混合反応させた塗布溶液を2000rpm で30秒間、回転
塗布し、窒素ガス雰囲気中で 200℃で30分間熱処理後、
窒素ガス雰囲気中で 400℃1時間の熱処理を加えること
によりポリイミド樹脂膜7を形成する。次に、同図
(e)のように、フォトリソグラフィーとCF4 ,O2
混合ガスを用いる反応性イオンエッチングを用い、CF
4 の流量を20SCCM,O2 の流量を20SCCMとし、チャンバ
ー内圧力を5pa、印加電力を 300Wとして前記ポリイミ
ド樹脂膜7にスルーホールに開口7aを設ける。
Next, as shown in FIG. 2D, P is used to improve the adhesion by using a mixed gas of N 2 NH 3 SiH 4.
Using the CVD method, the flow rate of N 2 is 1 SLM, the flow rate of NH 3 is 300 SCCM, the flow rate of SiH 4 is 0.87 SLM, and the pressure is 0.
Film thickness 1500 with 36TOW, temperature 300 ℃, applied voltage 1KW
A Å silicon nitride film 6 is formed. Furthermore, a coating solution obtained by mixing and reacting an aminosilicon compound, a diamine, and an aromatic tetracarboxylic dianhydride was spin-coated at 2000 rpm for 30 seconds, and heat-treated at 200 ° C. for 30 minutes in a nitrogen gas atmosphere,
A polyimide resin film 7 is formed by applying heat treatment at 400 ° C. for 1 hour in a nitrogen gas atmosphere. Next, as shown in FIG. 6E, photolithography and CF 4 , O 2 are performed.
CF using reactive ion etching using mixed gas
The flow rate of 4 is 20 SCCM, the flow rate of O 2 is 20 SCCM, the pressure in the chamber is 5 pa, and the applied power is 300 W. The polyimide resin film 7 is provided with through holes 7a.

【0010】続いて、同図(f)のようにスパッタ法に
より厚さ約1μmのアルミニウム膜と、厚さ 0.1μmの
窒化チタン膜を形成し、フォトリソグラフィー、ドライ
エッチングにより第2のアルミニウム配線8と窒化チタ
ン膜9から成る積層構造の第2の金属配線を形成する。
Subsequently, as shown in FIG. 3F, an aluminum film having a thickness of about 1 μm and a titanium nitride film having a thickness of 0.1 μm are formed by the sputtering method, and the second aluminum wiring 8 is formed by photolithography and dry etching. Then, a second metal wiring having a laminated structure including the titanium nitride film 9 is formed.

【0011】次に、同図(g)のようにP−CVD法を
用いて全面に膜厚3000Åのシリコン窒化膜10を形成す
る。続いて、同図(h)のようにCF4 ガスを用いる反
応性イオンエッチングを用い、CF4 の流量を20SCCM,
圧力5pa、印加電力 300Wとし、シリコン窒化膜10を
エッチングバックし、配線の側壁のみにシリコン窒化膜
10を形成する。しかる後、同図(i)のようにP−C
VD装置中で 320℃1時間のプリベークを行い、前記ポ
リイミド樹脂膜7から水分除去を行った後、P−CVD
法を用い膜厚1μmのカバー用シリコン窒化膜11を形
成することにより2層配線構造が形成される。
Next, as shown in FIG. 3G, a silicon nitride film 10 having a film thickness of 3000 Å is formed on the entire surface by P-CVD. Then, as shown in FIG. 6H, reactive ion etching using CF 4 gas is used, and the flow rate of CF 4 is 20 SCCM,
The pressure is 5 pa and the applied power is 300 W, and the silicon nitride film 10 is etched back to form the silicon nitride film 10 only on the side wall of the wiring. Then, as shown in (i) of the figure, PC
After prebaking at 320 ° C. for 1 hour in a VD apparatus to remove water from the polyimide resin film 7, P-CVD is performed.
A two-layer wiring structure is formed by forming a cover silicon nitride film 11 having a film thickness of 1 μm using the method.

【0012】ここで、前記したポリイミド樹脂膜7は、
アミノシリコン化合物とジアミンと芳香族テトラカルボ
ン酸二無水物とを混合反応させた塗布溶液で構成してい
るが、アミノシリコン化合物としては、〔化4〕で表さ
れるP−アミノフェニルトリメトキシシランを用いてい
る。又、ジアミンとしては、ジアミノジフェニルエーテ
ルを、更に、芳香族テトラカルボン酸二無水物としては
ベンゾフェノンテトラカルボン酸二無水物を用いてい
る。そして、P−アミノフェニルトリメトキシシランの
モル濃度を40%とし、その溶媒はジメチルアセトアミド
を用い、この溶液の粘度を 300cm・poise としている。
Here, the above-mentioned polyimide resin film 7 is
The coating solution is prepared by mixing and reacting an aminosilicon compound, a diamine, and an aromatic tetracarboxylic dianhydride. As the aminosilicon compound, P-aminophenyltrimethoxysilane represented by [Chemical Formula 4] is used. Is used. Further, diaminodiphenyl ether is used as the diamine, and benzophenonetetracarboxylic dianhydride is used as the aromatic tetracarboxylic dianhydride. The molar concentration of P-aminophenyltrimethoxysilane is 40%, dimethylacetamide is used as the solvent, and the viscosity of this solution is 300 cm · poise.

【0013】[0013]

【化4】 [Chemical 4]

【0014】[0014]

【発明の効果】以上説明したように本発明は第2の金属
配線を上層に耐熱性のある金属を用いた積層構造とし、
かつその側壁を無機膜で被覆しているため、層間膜であ
るポリイミド樹脂中の水分除去のためにベークを行って
も、第2の金属配線に用いたアルミニウム合金にラテラ
ルヒロックが発生することがなく、配線間ショートを抑
制して、製品歩留や信頼性を向上することができる効果
がある。
As described above, according to the present invention, the second metal wiring has a laminated structure using a heat resistant metal as an upper layer,
Moreover, since the side wall is covered with an inorganic film, lateral hillocks may be generated in the aluminum alloy used for the second metal wiring even if baking is performed to remove water in the polyimide resin that is the interlayer film. In other words, there is an effect that short-circuiting between wirings can be suppressed and product yield and reliability can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の製造方法の一実施例を製造工程順に示
す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a manufacturing method of the present invention in the order of manufacturing steps.

【図2】従来の製造方法を製造工程順に示す断面図であ
る。
FIG. 2 is a sectional view showing a conventional manufacturing method in the order of manufacturing steps.

【図3】従来の問題点を示す断面図である。FIG. 3 is a cross-sectional view showing a conventional problem.

【符号の説明】[Explanation of symbols]

1 半導体基板 2,4 リンガラス 3ポリシリコン電極 5 第1のアルミニウム配線 6 シリコン窒化膜 7 ポリイミド樹脂膜 8 第2のアルミニウム配線 9 窒化チタン膜 10,11 シリコン窒化膜 1 Semiconductor Substrate 2,4 Phosphorous Glass 3 Polysilicon Electrode 5 First Aluminum Wiring 6 Silicon Nitride Film 7 Polyimide Resin Film 8 Second Aluminum Wiring 9 Titanium Nitride Film 10,11 Silicon Nitride Film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の絶縁膜上に第1の金属配線
を形成する工程と、この第1の金属配線をポリイミド樹
脂膜で被覆する工程と、このポリイミド樹脂膜に前記第
1の金属配線が露呈されるスルーホールを開口する工程
と、前記ポリイミド樹脂膜の上に少なくとも上層が耐熱
性のある金属層で形成された積層構造の第2の金属配線
を形成する工程と、この第2の金属配線を含む全面に無
機膜を形成する工程と、この無機膜を異方性エッチング
により除去して第2の金属配線の側面を覆うように残す
工程と、前記ポリイミド樹脂膜に対してプリベークを行
った後、全面に無機膜を形成する工程を含むことを特徴
とする半導体装置の製造方法。
1. A step of forming a first metal wiring on an insulating film of a semiconductor substrate, a step of coating the first metal wiring with a polyimide resin film, and a step of coating the polyimide resin film with the first metal wiring. And a step of forming a second metal wiring having a laminated structure in which at least an upper layer of the heat resistant metal layer is formed on the polyimide resin film; A step of forming an inorganic film on the entire surface including the metal wiring, a step of removing this inorganic film by anisotropic etching and leaving it so as to cover the side surface of the second metal wiring, and a pre-baking for the polyimide resin film. A method of manufacturing a semiconductor device, comprising a step of forming an inorganic film on the entire surface after the step.
【請求項2】 ポリイミド樹脂膜は、一般式が〔化1〕
で表される芳香族テトラカルボン酸二無水物と、〔化
2〕で表されるジアミンと、〔化3〕で表されるアミノ
シリコン化合物とを混合反応せしめることによって形成
したポリアミド酸シリコン型中間体を含有してなる溶液
を塗布し、 150℃〜 200℃の温度で熱処理して形成する
請求項1の半導体装置の製造方法。 【化1】 【化2】 【化3】 但し、R1 は4価の炭素環式芳香族基を表し、R2 は炭
素数6〜30個の炭素環式芳香族基、R3 及びR4 は独立
に炭素数1〜6のアルキル基又はフェニル基、Kは1≦
K≦3の値である。
2. The polyimide resin film has a general formula:
A polyamic acid silicon type intermediate formed by mixing and reacting an aromatic tetracarboxylic dianhydride represented by the formula (4), a diamine represented by the formula (2) and an aminosilicon compound represented by the formula (3) The method for manufacturing a semiconductor device according to claim 1, wherein the solution containing the body is applied and heat-treated at a temperature of 150 ° C to 200 ° C. [Chemical 1] [Chemical 2] [Chemical 3] However, R 1 represents a tetravalent carbocyclic aromatic group, R 2 is a carbocyclic aromatic group having 6 to 30 carbon atoms, and R 3 and R 4 are independently an alkyl group having 1 to 6 carbon atoms. Or phenyl group, K is 1 ≦
It is a value of K ≦ 3.
JP23566391A 1991-08-23 1991-08-23 Manufacture of semiconductor device Pending JPH0555386A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23566391A JPH0555386A (en) 1991-08-23 1991-08-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23566391A JPH0555386A (en) 1991-08-23 1991-08-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0555386A true JPH0555386A (en) 1993-03-05

Family

ID=16989357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23566391A Pending JPH0555386A (en) 1991-08-23 1991-08-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0555386A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63188956A (en) * 1987-01-31 1988-08-04 Sony Corp Manufacture of semiconductor device
JPH01225339A (en) * 1988-03-04 1989-09-08 Nec Corp Manufacture of multilayer wiring structure using resin interlayer film
JPH0214525A (en) * 1988-07-01 1990-01-18 Oki Electric Ind Co Ltd Manufacture of semiconductor integrated circuit
JPH0327551A (en) * 1989-06-23 1991-02-05 Nec Corp Wiring structure of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63188956A (en) * 1987-01-31 1988-08-04 Sony Corp Manufacture of semiconductor device
JPH01225339A (en) * 1988-03-04 1989-09-08 Nec Corp Manufacture of multilayer wiring structure using resin interlayer film
JPH0214525A (en) * 1988-07-01 1990-01-18 Oki Electric Ind Co Ltd Manufacture of semiconductor integrated circuit
JPH0327551A (en) * 1989-06-23 1991-02-05 Nec Corp Wiring structure of semiconductor device

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