JPS6064451A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a change into a thin-film of a metal in a contact section by forming an inter-layer insulating film on a conductive pattern, selectively removing the insulating film to expose the pattern and forming an upper electrode to the pattern. CONSTITUTION:Ti patterns 321-323 and first Al patterns 31... are shaped to contact sections, resist patterns 30 are formed on the patterns 31..., a first SiO2 film 33 is formed on the whole surface, and the resists 30 and the SiO2 films 33 on the patterns 31... are removed simultaneously through a lift-off. Consequently, the surfaces of the residual films 33 and the surfaces of the patterns 31... are brought to the same level, and the contact sections can be flattened. Accordingly, a change into thin-films of Al in the contact sections can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which the connection between an upper electrode and a lower electrode is improved.

[Technical background of the invention and its problems]

Conventionally, a semiconductor device having a two-layer structure having an upper electrode and a lower electrode has been manufactured as shown in FIG. First, a field oxide film 2 is formed on a predetermined surface of a semiconductor substrate 1 by a conventional method, and an oxide film (not shown) is formed on the substrate 1 separated by the field oxide film 2. Subsequently, after forming a polycrystalline silicon layer over the entire surface, it is patterned to form a lower electrode 3 on the field oxide film 2, and a gate electrode 4 on the oxide film. Next, the oxide film is selectively removed using the gate electrode 4 as a mask, and the gate insulating film 5 is removed.
form.

Thereafter, impurity ions are implanted into the base vi1 using the gate electrode 4 as a mask to form source and drain regions 6' and 7. Furthermore, after forming the first interlayer insulating film 8 on the entire surface, the interlayer insulating film 8 corresponding to the lower electrode 3 and a portion of each of the source and drain regions 7 and 8 is selectively removed to form a contact hole 98. ,9□,9. form and draw. Continuing, A4 all over? After vapor deposition, patterning is performed to form a contact hole 9. an upper electrode 101. connected to the lower electrode 3 via the upper electrode 101. Contact hole 9! Contact electrodes 11 and 11 were formed to connect to the source and drain regions 7.8 through s98, respectively. Thereafter, after forming the second interlayer insulating film J2 on the entire surface in the same manner, contact holes 1
3. The upper electrode 10 via the contact hole 13
A semiconductor device is manufactured by forming an extraction wiring 14 connected to the semiconductor device.

However, according to the manufacturing method described above, contact holes 9I to 9. ．． As the opening area of contact holes 9i to 9, . 13 becomes difficult to drill. This is because when the interlayer insulating films 8 and 12 are etched with gas plasma or liquid, the etching products flow out of the contact holes by diffusion because the opening area of the contact holes is small. This is because it becomes difficult. Further, even when a contact hole is formed, the AJ formed by sputtering, vapor deposition, etc. around the upper corner of the contact hole becomes thinner than the AJ deposited on a flat surface, which poses a serious problem in device reliability.

For this reason, recently, semiconductor devices as shown in FIG. 2 have been manufactured. First, an oxide film 15 is formed only around the gate electrode 4, and a first interlayer insulating film 8 is formed.
63 is drilled. Subsequently, openings 171 to 17. are formed on the entire surface corresponding to the interlayer insulating film 8. A photoresist film 18 is formed, and then Alh419 is deposited on the entire surface, and the contact holes 16x to 16 are also filled with the AJ layer 20. Next, by lift-off technique, the photoresist film 18 is removed and the kl)mx9 above it is also removed at the same time. After that, the interlayer insulating film 8 of the mud 1 is removed by applying AJ layer 2o. Thereafter, the AIj layer is temporarily inspected and patterned again to manufacture a semiconductor device. However, in the manufacturing method using such a lift-off technology, a contact hole that is deep compared to the opening area of the contact hole is filled with a layer 1, etc., thereby making the actual step shallow and preventing thinning of the AJ film at the upper corner of the contact hole. This is what I am trying to do. However, according to this method, the lift-off technique itself is difficult because the area where AI should be removed occupies most of the area. In addition, since the photoresist film 18 is used, AJ is used before AJ is deposited and after the contact hole is opened.
It becomes difficult to clean the contact holes that should be filled, and it is difficult to reduce the resistance of the contact portion. .

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is capable of manufacturing a semiconductor device in which an upper electrode is formed on a flat base to prevent thinning of the metal film at the contact portion, and at the same time, the resistance of the contact portion can be reduced. The purpose is to provide a method.

[Summary of the invention]

The present invention exposes a conductive pattern by discharging a diffusion layer on the surface of a semiconductor substrate or a lower part provided on the substrate via an insulating film, and further connects the conductive pattern on an insulating layer between iT tl /%. By forming the upper electrode, the main purpose is to prevent the metal from becoming thin in the contact portion and to reduce the resistance of the contact portion.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in Figures 81 and 3 (al to ldl
Explain with reference to.

(1) First, a field oxide film 22 is formed on a predetermined surface of an 81 substrate 21 as a semiconductor substrate by a conventional method, and an oxide film (not shown) is formed on the substrate 1 separated by the oxide film 22 in this field'. was formed. Subsequently, polycrystalline silicon 1tIJ was formed on the entire surface, and then patterned to form a lower electrode 13 on the field oxide film 22, and a gate electrode 24 on the oxide film. Next, the gate electrode 24
Using this as a mask, the oxide film was selectively removed to form a gate insulating film 25. Next, impurity ions are implanted into the substrate using the gate base Fi 24 as a mask, and the source and drain regions 26 . ; After forming j7, an oxide film 28 was formed around the gate electrode 24. After further forming a titanium (Ti) layer 29 with a thickness of approximately 1000 mm,
On this Tl129, a 5000^ thick aluminum (a
/) layer (not shown), a resist pattern 3o was formed only in the area where a contact hole was to be formed on this AJ layer. Thereafter, using this resist pattern 3o as a mask, the A6 layer is selectively etched away to form a first AJ pattern 31 that forms part of the conductor pattern.
・ was formed (Fig. 3 (resistance illustration)).

[Cylinder] Next, the exposed Ti R1J29 was selectively etched away using dilute HF, and the first An? Pattern 3... and TI pattern 32 constituting a conductor pattern. ~32s was formed. Next, plasma CVD
A first 5i02 film 33 with a thickness of 5000λ as a first interlayer insulating film was formed on the entire surface at about 100° C. by a method (shown in FIG. 3 (b1)). Next, the resist pattern 30
At the same time, the S t O film 33 covering the resist pattern 30 was also removed (lift-off). Furthermore, the entire surface of the tg-Alt sushi is broken and patterned to form the above 810. The Ti pattern 32. is formed on the film 33. At the same time, forming the upper electrode 34 made of A/l' connected to the source and drain regions 26 and 27 of
A 20th Ae pattern 35.35 connected through the pattern 327, the first Ad pattern 31 and Ti pattern 323, and the first AAl pattern 31 was formed.

Note that the Ti pattern 322, the first A6 pattern 31, and the second AI! The pattern 35 constitutes a contact electrode 36 with the source region 26, and includes the Ti pattern 323, the first AAl pattern 31 and the second A! A contact electrode 37 with the drain region 17 is formed from the pattern 35 (as shown in FIG. 3(e)). Thereafter, a Ti pattern 3B and a kl pattern 39 are formed on the upper electrode 34 using the method described above.
A second 810 as a second interlayer insulating film is formed.
．． Form the film 40, and then continue to form the second Sin film 4.
A semiconductor device was manufactured by forming an extraction wiring 41 made of AA and connecting it to the upper electrode 34 via an AAl pattern 39 and a Ti pattern 38 on the semiconductor device 0 (as shown in FIG. 3(d)).
- According to the present invention, it is possible to apply Ti to the contact portions of the lower electrode 23 and the source and drain regions 26 and 27 in advance.
Pattern 32. ~323, After forming the first AJ pattern 3, a resist pattern 30 is formed on the first AJ pattern 3o, and a first StO film 33 is further formed on the entire surface. The lift-off removes the resist pattern 3o on the first Ad pattern 30 and the first 810. The film 33 can be removed at the same time.

Therefore, as shown in FIG. 3(b), the remaining first S
tO, the surface of the film 33 and the first AAl pattern 31...
The contact area can be flattened by keeping the surfaces at the same - level. As a result, it is possible to prevent the AA from becoming thinner in the contact portion as in the semiconductor device shown in FIG. 1, and the reliability of the device can be improved.

Furthermore, when forming the Ae pattern 31... on the contact portion, the photoresist M is not used as in the semiconductor device shown in FIG. 2, so a clean surface can be maintained after the AI pattern 31... The resistance of the contact part can be reduced.

Furthermore, when forming AI pattern 3, the A1 layer that is etched away can flow out almost freely from a wide plane, so in principle it is possible to form an extremely small contact portion of about 0.1 μ'. becomes possible.

In the above embodiment, Al and TI were used as the materials for forming the contact portion with the lower electrode, but the material is not limited to this, and an isoelectric material having an etching rate different from polycrystalline silicon, which is the material of the lower electrode, may be used. Any material can be used.

Further, in the above embodiment, the case where the upper electrode has a single layer structure made of AA has been described, but it can be similarly applied to a case where the upper electrode has a two layer structure consisting of an Ae pattern 51 and a TI pattern 52 as shown in FIG.

〔Effect of the invention〕

As described above in detail, according to the present invention, it is possible to provide a method of manufacturing a highly reliable semiconductor device that can prevent the metal from becoming thin in the contact portion and reduce the resistance of the contact portion.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a conventional semiconductor device, FIGS. 3(a) to (dl) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and FIG. is a sectional view of a semiconductor device according to another embodiment of the present invention. 21...81 substrate (semiconductor substrate), 22... field oxide film, 23... lower electrode, 24... gate electrode , 25... Gate insulating film, 26... Source region,
27..Drain region, 28.+1 curved oxide film, 29.
...Titanium (Ti) layer, 30...Resist pattern,
31゜35, 39, 5 J---All<9-n, 32. ~32,...Ti pattern (conductor) (turn), 33°40...5i02 film, 34...upper electrode, 36, 37...contact electrode, 38.52...
・'pi%9-V, 41...Exit wiring. Applicant's representative Patent attorney Takehiko Suzue

Claims (1)

[Claims] 111 A step of forming a conductive pattern on at least one of a diffusion layer on the surface of a semiconductor substrate or a lower electrode provided on the substrate via an insulating film, and forming an interlayer insulating film on the entire surface. a step of selectively removing an interlayer insulating film on the conductor pattern to expose the conductor pattern; and a step of forming an upper electrode connected to the conductor pattern on the interlayer insulating film. A method for manufacturing a semiconductor device, characterized in that: (2) The method of manufacturing a semiconductor device according to claim 1, wherein the upper electrode or the lower electrode has a two-layer structure consisting of different types of conductor patterns.