JPH08236622A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE: To realize highly accurate interconnection by interconnecting upper and lower interconnections in first and second conductive regions through each contact hole made in a common insulation layer while decreasing or without increasing the number of steps. CONSTITUTION: Contact holes 33, 34, 39 and 35, 37 are made through a common insulation layer 7 in order to connect a lower interconnection 38 to be connected with a gate electrode 10 and a source region 3 with an upper interconnection 42 to be connected with a drain region 4. In this regard, a common mask is employed and the conductive material 36 for the lower interconnection 38 is left as a plug at the time of patterning thereof and the upper interconnection 42 is formed on a through hole 50 made by side wall technology. Consequently, the masking, patterning and etching are required only once in the formation of each contact hole. Furthermore, through hole for upper interconnection can be made without requiring any mask and thereby the number of steps can be decreased while reducing the cost and shortening the cycle time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device (in particular, an IC including a transistor having a multilayer wiring structure) and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a multilayer wiring structure has a MOS (Metal) structure.
It is often used in ICs composed of oxide semiconductor transistors and is indispensable for devices.

20 to 25 show an example thereof according to a manufacturing process.

First, as shown in FIG. 20, a polysilicon gate electrode 10 is formed on one main surface of a P ⁻ type silicon substrate 1 with a gate oxide film 5 interposed therebetween, and N ⁺ type source regions are formed on both sides of the gate electrode. 3 and the drain region 4 are respectively formed by impurity diffusion, and a sidewall 11 such as an oxide film (SiO ₂ ) or a nitride film (Si ₃ N ₄ ) is formed on the side surface of the gate electrode 10.

Then, CVD (Chemical Vapor) is formed on the entire surface.
Deposition) on the insulating layer 7 such as SiO ₂ formed by
A mask 12 (for example, photoresist) for forming contact holes is provided in a predetermined pattern, and the insulating layer 7 is etched by using the mask 12 as shown in FIG.
Form 13, 14 and 15, respectively.

Next, as shown in FIG. 22, each contact hole is filled with aluminum 16 which is a conductive material (at this time, aluminum deposited on the insulating layer 7 is removed by etching), and the entire surface is covered with a lower electrode material. A certain aluminum 17 is deposited by sputtering or the like.

Although a metal such as aluminum is directly connected to the N ⁺ type diffusion regions 3 and 4 and the polysilicon gate electrode 10 here, the diffusion regions 3 and 4 and the polysilicon are also described. When a metal such as aluminum is connected to the gate electrode 10, titanium nitride (T) is formed on the diffusion regions 3 and 4 or the polysilicon gate electrode 10.
A barrier metal such as i / TiN) or titanium silicide (TiSi ₂ ) is deposited and then the metal is connected.

Next, as shown in FIG. 23, the lower electrode material is patterned by photolithography to form the lower electrodes 18 and 19, the gate electrode 10 and the source region 3, respectively.
And the drain region 4 are connected.

Next, as shown in FIG. 24, CVD is performed on the entire surface.
A through hole 21 is formed so that the electrode 19 on the drain region 4 is partially exposed in the insulating layer 20 such as SiO ₂ deposited by.

Next, as shown in FIG. 25, through holes
Aluminum including 21 is deposited as an upper electrode material by sputtering or the like, and this is patterned to form an upper electrode 22.

Thus, the gate electrode is formed by the lower electrode 18.
A multilayer wiring structure in which the drain region 4 is taken out by the upper electrode 22 and the lower electrode 19 from the source electrode 3 and the source region 3 is manufactured.

However, in this multilayer wiring structure, the insulating layer 7 has contact holes 13 to 15 for wiring of the first layer.
However, since it is necessary to form through holes 21 for wiring of the second layer in the insulating layer 20, highly accurate patterning and etching are required twice to form each of these holes, resulting in cost increase. , Contributing to an increase in cycle time. In recent years, the number of wiring layers has increased from two layers to three layers and four layers, and this tendency is being spurred.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a multi-layer wiring structure which enables highly accurate connection without reducing the number of steps or increasing the number of steps.
It is to provide the manufacturing method.

[0014]

That is, according to the present invention, the first and second conductive regions are connected to the lower wiring and the upper wiring through the connection holes in the insulating layer provided on these conductive regions, respectively. The present invention relates to a semiconductor device having a connected structure, in which each of the connection holes on the first and second conductive regions is opened from a common insulating layer.

In the semiconductor device of the present invention, the first
And the connection hole on the second conductive region may be filled with a lower wiring material.

The upper wiring and the lower wiring may be electrically connected via the first or second conductive region.

The present invention also provides a first conductive region, a second conductive region formed above the first conductive region via a first insulating layer, and above the second conductive region. A third and a fourth conductive region formed via a second insulating layer,
A first connection hole reaching the first conductive region through the second and first insulating layers, and a second connection hole reaching the second conductive region through the second insulating layer The first conductive region and the third conductive region are connected via the first connection hole, and the second conductive region and the fourth conductive region are the second conductive region. The present invention also relates to a semiconductor device connected through the connection hole.

In this case, the first conductive region may be a conductive region formed on one main surface of the semiconductor substrate, and the second, third and fourth conductive regions may be wiring layers.

The present invention also provides a method for manufacturing a semiconductor device according to the present invention, wherein a first method is provided above the first and second conductive regions.
Forming an insulating layer, forming first and second connection holes reaching the first and second conductive regions through the first insulating layer, respectively, and the first insulating layer A second conductive material, which is connected to the first conductive region via a first connection hole filled with the first conductive material by depositing a first conductive material thereon (this is the first conductive material). And the same may be different from the conductive material of No. 1), and a second connection hole filled with the first conductive material, and Second over the first wiring
And a second conductive material electrically connected to the second conductive region via a second connection hole filled with the first conductive material. And a step of forming wiring on the second insulating layer.

The present invention also includes the step of forming a first insulating layer above the first conductive region, the step of forming a second conductive region on the first insulating layer, and the second step. Forming a second insulating layer above the conductive region, and reaching the first conductive region through the second and first insulating layers.
And a second connection hole reaching the second conductive region via the second insulating layer, and the first connection hole
And a step of filling the second connection hole with a conductive material and forming third and fourth conductive regions connected to the first and second connection holes, respectively. To do.

In this case, a step of forming a third insulating layer above the third and fourth conductive regions, and a step of reaching the second conductive region through the third and second insulating layers. Forming the third connection hole, and filling the third connection hole with a conductive material and forming a fifth conductive region connected to the second conductive region through the third connection hole. And a process.

[0022]

Embodiments of the present invention will be described below.

1 to 8 show a first embodiment in which the present invention is applied to a MOS device.

The device structure according to this embodiment will be described together with its manufacturing process. First, as shown in FIG. 1, in the element region partitioned by the field SiO ₂ film 2,
A polysilicon gate electrode 10 is formed on one main surface of the P ⁻ type silicon substrate 1 through a gate oxide film 5, and N ⁺ type source regions 3 and drain regions 4 are formed on both sides of the gate electrode by impurity diffusion. Further, a side wall 11 of an oxide film (SiO ₂ ) or a nitride film (Si ₃ N ₄ ) is formed on the side surface of the gate electrode 10. The field Si
A gate electrode having a sidewall 11 on the O ₂ film 2
10 is present as part of the wiring.

Then, CVD (Chemical Vapor) is formed on the entire surface.
A mask 32 (for example, photoresist) for forming a contact hole is provided in a predetermined pattern on the insulating layer 7 such as SiO ₂ formed by the deposition, and the insulating layer 7 is etched using the mask 32 as shown in FIG. Each contact hole 3
3, 34, 35, 37, 39 are formed respectively.

Next, as shown in FIG. 3, after removing the mask 32, polysilicon 36 which is a conductive material is deposited on the entire surface including each contact hole.

Then, as shown in FIG. 4, the conductive material on the surface is removed by etching back, and the contact holes 33.about.
The conductive material 36 is filled only (37 and 39) and left (as a plug), and aluminum 38 which is a lower wiring material is further sputtered, and an SiO ₂ insulating layer 60 is sequentially laminated by CVD.

Next, as shown in FIG. 5, a mask 59 (eg, photoresist) is formed in a predetermined pattern to form a lower wiring, and then etching is performed using this mask to form a lower portion having a SiO ₂ layer 60 on the upper portion. The electrode 38 is formed, and the conductive material 36 is left as a contact hole plug also in the contact holes 35 and 37.

Next, as shown in FIG. 6, an interlayer insulating film 40 such as SiO ₂ for separating the lower wiring 38 and the conductive material 36 as a plug is formed, and then, as shown in FIG. The side wall 54 is covered with the sidewall 54, and the through hole 50 without the sidewall 54 is formed.
At, the conductive material 36 in the contact holes 35 and 37 is exposed.

Next, as shown in FIG. 8, aluminum 42 which is an upper wiring material is deposited. After that, the device is completed through the patterning of the upper wiring material and the step of adhering the surface insulating layer.

Thus, the gate electrode 10 and the source region 3
It is possible to fabricate a multi-layer wiring structure in which the lower wiring 38 connected to the above and the upper wiring 42 connected to the drain region 4 are insulated and separated by the insulating layers 60 and 54, but this process has the following remarkable features. are doing.

(1) The connection holes for the lower wiring 38 and the upper wiring 42 are provided in the common insulating layer 7 as contact holes 33, 34 and
When forming each of 39, 35 and 37, they are formed using a common mask 32 (see FIG. 2), and the conductive material 36 for the lower wiring is left as a plug when patterning the lower wiring 38 (see FIG. 5). ) Further, since the upper wiring 42 is deposited on the through hole 50 formed by using the sidewall technique, each contact hole can be formed by one-time masking, patterning, and etching, and the through hole for the upper wiring is also formed. It can be formed without a mask, the number of steps can be reduced by at least two steps, and at the same time, cost reduction and cycle time reduction can be realized.

(2) Since each contact hole and through hole can be formed with high precision without positional displacement, each hole can be formed as small as possible and at a narrow interval, and the chip or element size can be reduced. It is advantageous.

(3) Since the upper wiring (second layer wiring) and the transistor or the like formed on the silicon substrate can be directly connected without passing through the lower wiring (first layer wiring), that much Layout rules for wiring of a semiconductor device are relaxed.

(4) Since the upper wiring (second layer wiring) and the lower wiring (first layer wiring) can be connected to each other by a wiring layer lower than these wirings, conventionally, the wiring has not been formed. The field SiO ₂ film or the interlayer insulating film, which has been left as an empty region, can be used as a wiring formation region, and the layout rule can be relaxed and the chip area can be reduced.

In this embodiment, the field SiO ₂
Although the upper wiring and the lower wiring are connected via the wiring on the film, the bit line in the dynamic DRAM,
The upper wiring and the lower wiring may be connected via a wiring formed in the same layer as the storage node, the plate electrode and the like.

9 and 10 show a second embodiment in which the present invention is applied to a MOS device.

This embodiment is different from the above-mentioned first embodiment in that the wiring material itself is used as the plug material of the contact hole.

That is, as shown in FIG. 9, in the steps corresponding to the steps of FIGS. 3 and 4 in the above-mentioned first embodiment,
Each of the contact holes 33 to 37 formed in the insulating layer 7 is filled with a lower wiring material 38 such as aluminum as a plug when the lower wiring material 38 is deposited.

Therefore, in the finally produced multilayer wiring structure, as shown in FIG. 10, the lower wiring material 38 is left in the contact holes 35 and 37, and the upper wiring 42 such as aluminum is deposited through the contact holes 35 and 37. Will be connected.

As described above, since the lower wiring material itself is used as the plug material, it is possible to additionally obtain an effect that the number of steps required for filling the plug material is further reduced as compared with the first embodiment described above. .

11 to 16 show a third embodiment in which the present invention is applied to a MOS device.

The device structure according to this embodiment will be described together with its manufacturing process. First, as shown in FIG.
^- a polysilicon gate electrode 10 is formed via a gate oxide film 5 on the one main surface of -type silicon substrate 1, the N ⁺ -type source region 3 and drain region 4 are formed respectively by impurity diffusion in both sides of the gate electrode, Further, sidewalls 11 such as an oxide film (SiO ₂ ) or a nitride film (Si ₃ N ₄ ) are formed on the side surfaces of the gate electrode 10.

Then, as shown in FIG. 12, CVD is performed on the entire surface.
SiO ₂ formed by (Chemical Vapor Deposition)
A lower wiring 38 made of aluminum or the like is formed in a predetermined pattern on the insulating layer 57 or the like. This lower wiring can be formed by ordinary photolithography.

Then, as shown in FIG. 13, CVD is performed on the entire surface.
An insulating layer 67 such as SiO ₂ is formed by.

Next, as shown in FIG. 14, a mask 72 for forming contact holes is provided in a predetermined pattern, and using this, the insulating layers 67 and / or 57 are etched to contact holes 73, 74, 75 and Each through hole 76 is formed.

Next, as shown in FIG. 15, after removing the mask 72, a conductive material 86 such as aluminum is deposited on the entire surface including each contact hole, and this is etched back to fill each hole as a plug. Further, aluminum 42 which is an upper wiring material is deposited on the entire surface by sputtering. At this time, the upper wiring material 42 is connected to the conductive region on the substrate 1 and the lower wiring 38 by each plug material 86.

Next, as shown in FIG. 16, the upper wiring material is patterned into the upper wiring 42. As a result, a multi-layer wiring structure in which the gate electrode 10 and the source region 3 are connected to the lower wiring 38 via the plug material 86 and the upper wiring, and the drain region 4 is connected to the upper wiring 42 via the plug material 86 can be manufactured.

According to this example, the contact holes 73 to 75 for the upper and lower wirings are simultaneously formed in the common insulating layers 67 and 57 (the through hole 76 is also formed at the same time). The same effect as described in the first embodiment can be obtained. Then, various structures such as connecting to the lower wiring through the upper wiring are possible.

However, as shown in FIG. 15, since the contact holes 73 to 75 are considerably deep, it is advantageous to adopt a technique such as reflow Al in order to satisfactorily fill the plug material 86 (aluminum). .

That is, it is generally difficult to fill aluminum into a deep contact hole or a through hole, but reflow Al {ETM (Enhanced Transfer Mob
ility)}, deep contact holes or through holes can be completely filled with aluminum. First, deposit aluminum, and in an atmosphere such as argon, 55
Aperture ratio (ratio of hole diameter to depth) of 3 or more, 0.5μm or less (further 0.25 or less, 0.25) by performing treatment under the condition of pressure of ~ 65MPa and temperature of 350 ~ 450 ℃. The contact holes or through holes (μm or smaller) can be completely filled with aluminum.

FIG. 17 shows a fourth embodiment in which the present invention is applied to a MOS device.

According to this embodiment, the steps up to forming the contact holes 33, 34 and 35 in the insulating layer 7 at the same time and filling the contact holes with the conductive material 36 are the same as those described in the first embodiment.
1 to 4 in the embodiment of FIG.

On the insulating layer 7, first, the lower wiring is
38 is formed in a predetermined pattern so as to be connected to the plug material 36, and upper wiring is formed on the insulating layer 67 formed by CVD.
42 is formed in a predetermined pattern. After that, through holes 80, 81, 82 are formed in the insulating layer 77 and / or the insulating layer 67 formed by CVD on the insulating layer 67, and the through holes are filled with a conductive material 96, respectively. 3 on 77
The wiring 83 of the layer is formed in a predetermined pattern.

Thus, the lower wiring 38 or 42 and the upper wiring 42
Alternatively, a multi-layer wiring structure in which the wirings are isolated from each other via an insulating layer can be manufactured, but here, the contact holes 33 to 35 or the through holes 80 to 82 for each wiring are the common insulating layer 7 or
66 and 77 will be formed simultaneously. Therefore, even if the wiring has two or more layers (three layers in this example), the contact can be obtained with high accuracy by reducing the number of steps.

18 and 19 show another embodiment in which the present invention is applied to a MOS device.

In the embodiment shown in FIG. 8, the gate electrode 10 and the source region 3 are connected by the lower wiring 38, and the lower wiring 38 and the upper wiring 42 are connected to the gate electrode 10 on the field SiO ₂ film 2.
The wiring structure is to connect with, but as shown in Fig. 18,
It is also possible to divide the lower wiring 38 for the gate electrode 10 and the lower wiring 38 for the source region 3 and form a wiring structure in which these are separated from each other by a sidewall 54. Further, in the embodiment shown in FIG. 16 also, the wiring structure in which the gate electrode 10 and the source region 3 are connected by the upper wiring 42 is used, but as shown in FIG. 19, they may be separated. .

In the above-mentioned embodiment, it is described that the metal conductive material such as aluminum is directly connected to the diffusion regions 3 and 4 and the polysilicon gate electrode 10 in the silicon substrate. When a metal such as aluminum is connected to the polysilicon gate electrode, a barrier metal such as titanium nitride (Ti / TiN) or titanium silicide (TiSi ₂ ) is deposited on the diffusion region or polysilicon and then the metal is deposited. Connecting will be apparent to those skilled in the art. It will also be apparent to those skilled in the art that the barrier metal as described above may be interposed even when connecting different metals.

Although the embodiments of the present invention have been described above, the above embodiments can be further modified based on the technical idea of the present invention.

For example, the order and combination of the above-mentioned steps may be variously changed, and the materials and patterns to be used can be changed. As long as connection holes (contact holes or through holes) for upper and lower wirings are formed with a common mask, multilayer wirings with various structures and layouts can be manufactured.

In the above-described embodiments, aluminum was used as an example of the material of each wiring, but the material of these wirings may be conductive, such as polysilicon and A.
It may be arbitrarily selected from l, Ti, W and the like. Further, the insulating layer described above is not limited to the oxide film (SiO ₂ ) and may be, for example, a nitride film or the like.

The connection holes for the upper and lower wirings are preferably formed using a common mask, but the connection holes may be formed in any order as long as they are formed in the common insulating layer. . In addition, when connecting the upper and lower wiring,
In addition to the gate electrode, the wirings may be connected through the silicon substrate 1, or may be connected through other conductive layers.

The conductivity type of the semiconductor region described above may be changed, or the present invention may be applied to ICs, LSIs, semiconductor memories and other devices having an element structure other than the MOS device described above.

[0064]

As described above, according to the present invention, the first and second conductive regions are respectively connected to the lower wiring and the upper wiring through the connection holes in the insulating layer provided on these conductive regions. Since each connection hole on the first and second conductive regions is opened from the common insulating layer, each connection hole can be formed by reducing the number of steps, which leads to cost reduction. It is also advantageous in reducing the size in that the connection time can be reduced, the position deviation of each connection hole can be reduced, and the connection hole can be made as small as possible.

[Brief description of drawings]

FIG. 1 is an enlarged cross-sectional view of a process step of a method for manufacturing a MOS device according to an embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 3 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 4 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 5 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 6 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 7 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 8 is an enlarged sectional view of still another process step of the manufacturing method.

FIG. 9 is an enlarged cross-sectional view of a step of a method for manufacturing a MOS device according to another embodiment of the present invention.

FIG. 10 is an enlarged cross-sectional view of another process step of the manufacturing method.

FIG. 11 is an enlarged cross-sectional view of a process step of a method for manufacturing a MOS device according to another embodiment of the present invention.

FIG. 12 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 13 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 14 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 15 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 16 is an enlarged cross-sectional view of still another process step of the manufacturing method.

FIG. 17 is an enlarged cross-sectional view of a MOS device according to another embodiment of the present invention.

FIG. 18 is an enlarged cross-sectional view of a MOS device according to another embodiment of the present invention.

FIG. 19 is an enlarged cross-sectional view of a MOS device according to still another embodiment of the present invention.

FIG. 20 is an enlarged cross-sectional view of one step of a method for manufacturing a MOS device according to a conventional example.

FIG. 21 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 22 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 23 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 24 is an enlarged cross-sectional view of another process step of the same manufacturing method.

FIG. 25 is an enlarged cross-sectional view of still another process step of the manufacturing method.

[Explanation of symbols]

1 ... Silicon substrate 3 ... N ⁺ type drain region 4 ... N ⁺ type source region 7, 40, 57, 60, 67 ... Insulating layer 10 ... Gate electrode 11, 54 ... Side walls 32, 59, 72 ... Masks 33, 34, 35, 36, 37, 39, 73, 74, 75 ... Contact holes 36, 86 ... Conductive material 38 ... Lower wiring 42 ...・ Upper wiring 50, 76 ... through hole

Claims (8)

[Claims] 1. A structure in which a first conductive region and a second conductive region are respectively connected to a lower wiring and an upper wiring through respective connecting holes in an insulating layer provided on these conductive regions,
A semiconductor device in which each of the connection holes on the first and second conductive regions is opened from a common insulating layer. 2. The semiconductor device according to claim 1, wherein a lower wiring material is filled in each of the connection holes on the first and second conductive regions. 3. The semiconductor device according to claim 1, wherein the upper wiring and the lower wiring are electrically connected via the first or second conductive region. 4. A first conductive region, a second conductive region formed above the first conductive region via a first insulating layer, and a second conductive region formed above the second conductive region. Third and fourth conductive regions formed through the first insulating layer and first insulating regions that reach the first conductive region through the second and first insulating layers.
Connection hole and a second connection hole reaching the second conductive region via the second insulating layer, and the first conductive region and the third conductive region have the first conductive region and the second conductive region. A semiconductor device, which is connected through a connection hole, wherein the second conductive region and the fourth conductive region are connected through the second connection hole. 5. The method according to claim 4, wherein the first conductive region is a conductive region formed on one main surface of the semiconductor substrate, and the second, third and fourth conductive regions are wiring layers. Semiconductor device. 6. A step of forming a first insulating layer above the first and second conductive regions, and a first step of reaching the first and second conductive regions through the first insulating layer, respectively. And forming a second connection hole, and depositing the first conductive material on the first insulating layer to form the first connection material through the first connection hole filled with the first conductive material. Forming a first wiring made of a second conductive material and a second connection hole filled with the first conductive material, which is connected to the first conductive region; A step of forming a second insulating layer and a third step of electrically connecting to the second conductive region via a second connection hole filled with the first conductive material.
Forming a second wiring made of a conductive material on the second insulating layer. 7. A step of forming a first insulating layer above the first conductive area, a step of forming a second conductive area on the first insulating layer, and a step of forming the second conductive area. A step of forming a second insulating layer above, a first connecting hole reaching the first conductive region through the second and first insulating layers, and the first connecting hole through the second insulating layer Second reaching the second conductive area
And connecting the first and second connection holes with a conductive material and forming third and fourth conductive regions connected to the first and second connection holes, respectively. A method of manufacturing a semiconductor device, comprising: 8. A step of forming a third insulating layer above the third and fourth conductive regions, and a third step of reaching the second conductive region through the third and second insulating layers. And a step of filling the third connection hole with a conductive material and forming a fifth conductive region connected to the second conductive region through the third connection hole. The method for manufacturing a semiconductor device according to claim 7, further comprising: