JP2001110893A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device wherein the metal wiring of two or more layers are connected through two or more via-holes having mask alignment tolerance. SOLUTION: In this device, a first interlayer insulating film 4, first wiring 6, second interlayer insulating film 8, second wiring 10, third interlayer insulating film 12, third wiring 14, and cover film 16 are sequentially provided on a semiconductor substrate 2. The semiconductor substrate 2 is connected to the first wiring 8 through a first via hole 18 in the first interlayer insulating film 4. The first wiring 6 and the third wiring 14 are within the second interlayer insulating film 8, and are connected together through a second via-hole 20 having a mask alignment tolerance Dm and a third via-hole 22 within the third interlayer insulating film 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a multilayer wiring structure for connecting two or more layers of metal wiring through via holes and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, there is a tendency for a circuit configuration to be a multilayer wiring structure in response to recent demands for higher density and higher integration. In the multi-layer wiring structure, a connection technology between layers, that is, an embedding technology such as a contact hole as a connection portion between a lower layer device and an upper layer wiring and a via hole as a connection portion between a lower layer wiring and an upper layer wiring is important.

FIG. 12 shows a conventional example of a semiconductor integrated circuit device for connecting a lower wiring and an upper wiring. The semiconductor integrated circuit device has a three-layer wiring structure of a first wiring 106 as a lower wiring, a second wiring 110 as an intermediate wiring, and a third wiring 114 as an upper wiring.
It has a first interlayer insulating film 104, a second interlayer insulating film 108, a third interlayer insulating film 112, a cover film 116, a first via hole 118, a second via hole 120, and a third via hole 122.

A second wiring 110 as an intermediate wiring is formed between via holes 120 and 122 directly above via hole 120, and via hole 122 is formed directly above second wiring 110.
Is formed to electrically connect the third wiring 114 as the upper wiring and the first wiring 106 as the lower wiring (hereinafter, the second wiring 110 between the via holes 120 and 122 is formed). This is called dot wiring). The dot wiring is formed as follows.

First, a photoresist is applied to a thickness of about 1 μm after the formation of the second wiring, and a pattern is formed by lithography. Next, dry etching is performed using the photoresist as a mask to form dot wiring. However, it is difficult to stably form a photoresist in a shape required as the via hole diameter is reduced due to an improvement in the degree of integration of a semiconductor integrated circuit. This is because a photoresist having a required shape has a columnar shape, and the photoresist having this shape is extremely unstable and falls down during the development of the photoresist. In recent LSIs in which millions of transistors are integrated, if there is only a small possibility that such a columnar resist falls in one product chip, the yield is reduced.

As a means for solving the problem of the yield described above, for example, there is a method described in Japanese Patent Application Laid-Open No. 9-232429. The manufacturing method according to the prior art described in this publication will be described with reference to the drawings.

FIG. 13 is a plan view of a wiring structure of a conventional semiconductor integrated circuit device, and FIGS. 14 to 17 are lines B of FIG.
FIG. 4 is a cross-sectional view taken along the line -B ′, showing a method for forming a conventional multilayer wiring structure in a semiconductor integrated circuit device.

As shown in FIG. 13, the structure of a conventional semiconductor integrated circuit device is such that tungsten plugs 60, 70,
72, and wirings 62, 74, 76, 78.

First, as shown in FIG. 14, a first interlayer insulating film 52 such as a BPSG film is formed on a silicon substrate 50. Next, via hole 5 reaching silicon substrate 50
4, 56 are formed respectively. The via hole is formed by the following method. Using the photoresist film as a mask,
This is performed by reactive ion etching using a mixed gas of CF ₄ gas: CF ₃ gas = 1: 3. As the etching proceeds, the fluorocarbon-based polymer deposits formed on the side walls are removed by an organic solvent, and 0.6 μm × 0.6 μm on the surface of the first interlayer insulating film 52 and on the surface of the silicon substrate 50. Via holes (tapered via holes) 54 and 56 having a size of 0.4 μm × 0.4 μm and gradually narrowing in the depth direction are formed. Next, a tungsten film is formed on the entire surface by a blanket tungsten method, and the via holes 54 and 56 are filled with tungsten. First
The tungsten film is removed from the surface of the interlayer insulating film 52, and tungsten plugs 58 and 60 are formed.

Next, as shown in FIG. 15, an aluminum alloy film 62 is formed. In order to form a first wiring (reference numeral 62 in FIG. 16) connected to the tungsten plug 60, a photoresist 65 is formed, and using this as a mask, the aluminum-based alloy film 62 is etched.
The aluminum alloy film 62 does not remain on the tungsten plug 58. Next, the photoresist 65 is removed.

Next, as shown in FIG. 16, a second interlayer insulating film 64 such as a silicon oxide film is formed, and the via holes 66 and 68 reaching the tungsten plug 58 and the first wiring 62, respectively, are formed as described above. It is formed by taper etching. At this time, the taper etching using the mixed gas etches the silicon oxide-based interlayer insulating film at a high selectivity with respect to the aluminum-based alloy. Is hardly etched. Next, via holes 66 and 72
Is filled with tungsten, and tungsten plug 7
0,72 are formed.

As shown in FIG. 17, finally, wirings 74, 7
6, 78 are formed, and a protective film 80 is formed.

[0013]

In the conventional semiconductor integrated circuit device having the above-mentioned wiring structure, since a tapered via hole is used, the margin for mask alignment is strict and it is not suitable for mass production.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device which solves the above-mentioned problems, can be easily mask-aligned, is suitable for mass production, and a method of manufacturing the same.

It is another object of the present invention to provide a semiconductor integrated circuit device in which the opening diameter of a via hole can be changed by designing a circuit layout, and a method of manufacturing the same.

[0016]

A semiconductor integrated circuit device according to the present invention has a lower wiring, a first via hole, a first insulating layer formed on the lower wiring, and a second via hole. And a second insulating layer formed on the first insulating layer; and an upper wiring formed on the second insulating layer, wherein the lower wiring comprises the first wiring. A via hole and a second via hole are connected to the upper wiring, the second via hole is directly connected to the first via hole, and a cross section of one of the first via hole and the second via hole The shape is characterized in that it fits within the cross-sectional shape of the other via hole.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a step of forming a lower wiring, a step of forming a first insulating layer on the lower wiring having a first via hole, The step of forming a second insulating layer on the first insulating layer, and the step of forming an upper layer wiring on the second insulating layer, wherein the lower layer wiring comprises:
The first via hole and the second via hole are connected to the upper wiring via the first via hole and the second via hole, and the second via hole is directly connected to the first via hole. It is characterized in that one of the cross-sectional shapes falls within the cross-sectional shape of the other via hole.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a configuration of an embodiment of a semiconductor integrated circuit device of the present invention. This semiconductor integrated circuit device has a three-layer wiring structure including a first wiring 6 as a lower wiring, a second wiring 10 as an intermediate wiring, and a third wiring 14 as an upper wiring, and has a first via hole 1.
8, a second via hole 20, and a third via hole 22. In addition, in this embodiment, in order to make the description clear, the opening shape of the via hole is defined as a square, and one side of the square is defined as the opening diameter, but the opening shape is not limited to the square.

FIG. 2 is a sectional view taken along the line AA 'of FIG. As shown in FIG. 2, the semiconductor integrated circuit device includes a first interlayer insulating film 4, a first wiring 6, a second interlayer insulating film 8, a second wiring 10, The semiconductor substrate 2 and the first wiring 6 have a third interlayer insulating film 12, a third wiring 14, and a cover film 16, and are connected via a first via hole 18 in the first interlayer insulating film 4. The first wiring 6 and the third wiring 14 are electrically connected to each other by the second via hole 20 and the third via hole 20 in the second interlayer insulating film 8.
Are electrically connected via a third via hole 22 in the interlayer insulating film 12. At this time, the third via hole 22 is formed directly above the second via hole 20.

FIG. 3 shows a second example of the semiconductor integrated circuit device of FIG.
FIG. 4 is an enlarged view of a connection portion between a via hole 20 and a third via hole 22 of FIG. As shown in FIG. 3, the opening diameter D ₂ of the second via hole 20 is equal to the opening diameter D 3 of the third via hole 22.
Greater than _3, is formed to have a mask alignment margin D _m. Conversely, the third via hole 22 may be formed such that the opening diameter D ₃ is larger than the opening diameter D ₂ of the second via hole 20 and has a mask alignment margin D _m .

[0022]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a sectional view of a first embodiment of the semiconductor integrated circuit device. As shown in FIG. 4, the semiconductor integrated circuit device has a three-layer wiring structure, in which a first wiring 6 as a lower wiring, a second wiring 10 as an intermediate wiring,
A third wiring 14 is provided as an upper wiring. First wiring 6
Are Ti film 24, TiN film 26, aluminum alloy film 3
0, the TiN film 32, and the second wiring 10 includes the Ti film 34, the TiN film 36, the aluminum-based alloy film 40, the TiN
The third wiring 14 includes a Ti film 44, a Ti film
An N film 46, an aluminum alloy film 47, and a TiN film 49 are provided. Also in this example, as in the example, the opening shape of the via hole is a square, and one side of the square is the opening diameter.

More specifically, in this semiconductor integrated circuit device, a first interlayer insulating film 4, a first wiring 6, a second interlayer insulating film 8, and a second wiring 1
0, a third interlayer insulating film 12, a third wiring 14, and a cover film 16. The semiconductor substrate 2 and the first wiring 6 are
The first wiring 6 and the third wiring 14 are electrically connected to each other via a second via hole 20 and a third via hole 22. The first via hole 18 is in the first interlayer insulating film 4,
It is filled with a Ti film 24, a TiN film 26, and tungsten 28. The second via hole 20 is in the second interlayer insulating film 8 and is filled with a Ti film 34, a TiN film 36, and tungsten 38. The third via hole 22 has a third shape.
, The Ti film 44 and the TiN film 4
6, filled with tungsten 48. At this time, the third
Is formed directly above the second via hole. Further, the opening diameter D ₂ of the second via hole, as shown in FIG. 3 is greater than the opening diameter D ₃ of the third via holes 22 are formed to have a mask alignment margin D _m.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

As shown in FIG. 5, the field oxide film, M
Silicon substrate 2 on which OS transistors, capacitors, etc. are formed
Then, a first interlayer insulating film 4 such as a BPSG film is formed.
Next, a patterned photoresist 5 is formed,
Using this as a mask, a first via hole 18 is opened in the first interlayer insulating film 4 by an etching method, and the photoresist 5 is removed. Thus, the first via hole 18 connected to the silicon substrate 2 is formed.

Next, as shown in FIG.
The iN film 26 is formed by a sputtering method. Next, a tungsten film 28 is formed by a CVD method, and the first via hole 1 is formed.
8 is filled with tungsten. At this time, tungsten is formed on the first interlayer insulating film 4 to a thickness of about 0.2 μm to 0.3 μm. Next, the tungsten on the first interlayer insulating film 4 is removed by etching to expose the TiN film 26. Next, an aluminum alloy film 30 and a TiN film 32 are formed by a sputtering method. Next, in order to form a first wiring, a patterned photoresist 1 is formed.
Then, the TiN film 32, the aluminum-based alloy film 30, the TiN film 26, and the Ti film 24 are etched using the mask as a mask to remove the photoresist.

Next, as shown in FIG. 7, a second interlayer insulating film 8 is formed. Next, a patterned photoresist 25 is formed on the second interlayer insulating film 8, and using this as a mask, the second interlayer insulating film 8 is etched to form a second via hole 20 connected to the first wiring. And the photoresist 25 is removed. At this time, as shown in FIG. 3, the opening diameter of the second via hole 20, the circuit layout designed to have a mask alignment margin D _m. Therefore, when opening the second via hole 20, the shape of the patterned photoresist 25 is formed on the second insulating film 8 also, to have a mask alignment margin D _m.

Next, as shown in FIG.
An iN film 36 is formed by sputtering, and a tungsten film 38 is formed.
Is formed by a CVD method, and the via hole 20 is filled with tungsten. At this time, tungsten is formed on the second interlayer insulating film 8 to a thickness of about 0.2 μm to 0.3 μm. Next, etching is performed to remove tungsten on the second interlayer insulating film 8, exposing the TiN film 36. Next, the aluminum alloy film 40, Ti
An N film 42 is formed. Next, in order to form a second wiring, the TiN film 42, the aluminum-based alloy film 40, the TiN film 36, and the Ti film 34 are etched using a patterned photoresist (not shown) as a mask. Is removed.

Next, a third interlayer insulating film 12 is formed, a patterned photoresist 35 is formed on the third interlayer insulating film 12, and the third interlayer insulating film 12 is etched using this as a mask. Then, the third via hole 22 is opened, and the photoresist 35 is removed.

Next, as shown in FIG. 9, a third via hole 22 is formed in the Ti film 44, the TiN film 46, and the tungsten 48.
And tungsten on the third interlayer insulating film is removed by etching. An aluminum alloy film 47 and a TiN film 49 are formed by a sputtering method. Next, in order to form the third wiring 14, a patterned photoresist (not shown) is formed, and using this as a mask, the TiN film 49, the aluminum-based alloy film 47, the TiN
The film 46 and the Ti film 44 are etched to remove the photoresist. Finally, to protect the third wiring 14,
The cover film 16 is formed.

Returning now to FIG. 3, FIG.
An enlarged view of a connection portion between the second via hole 20 and the third via hole 22 formed in the above-described process is shown. Opening diameter D _{2 of second} via hole 20 connected to first wiring 6
And by a third magnitude plus mask alignment margin D _m in opening diameter D ₃ of the via hole 22 to be formed directly above, the third via holes 22 directly above the second via holes 20 formed In this case, there is a margin in the manufacturing process, and poor connection can be prevented. As a result, the occurrence of abnormal circuit formation due to poor connection can be suppressed.

FIG. 10 shows the first wiring 6 and the second wiring of this embodiment.
2 via hole 20, third wiring 14 and third via
FIG. 9 is a diagram when the layout of the hole 22 is synthesized,
Misalignment between second via hole 20 and third via hole 22
Is the mask alignment margin D in FIG. _m It is.

Next, a second embodiment of the present invention will be described.

As shown in FIG. 11, in the second embodiment,
Mask alignment margin D (shown in FIG. 3) _m The third beer
Opening diameter D_Three And the third via hole opening diameter is D_Three 
With the second via hole opening diameter D_Two The point of forming larger
However, this is different from the first embodiment. In the second embodiment, the upper wiring
Third via hole 22 connected to third wiring 14
Opening diameter D_Three , The degree of integration is improved.

Next, a third embodiment of the present invention will be described.

In the third embodiment, the first wiring 6 is replaced by the semiconductor substrate 2, the second wiring 10 is replaced by the first wiring 6, and the third wiring 14 is replaced by the second wiring of the first and second embodiments. Of the first via hole 1 connected to the semiconductor substrate 2
8, the second via hole 20 is directly connected, and the semiconductor substrate 2 and the second wiring 10 are connected.

Next, a fourth embodiment of the present invention will be described.

In the fourth embodiment, the third via hole 22 shown in FIG. 2 is regarded as the second via hole 20, and the connection described above with reference to FIGS. In this case, by combining the first and second embodiments, the combined mask alignment margin D _m in layout design, formed in addition to the opening diameter of the top or bottom hole stacking. Therefore, the aspect ratio does not increase each time a layer is stacked (conversely, the aspect ratio of the via hole in the lower layer does not increase). Therefore, the circuit layout can be freely designed without making the filling of tungsten difficult.

[0040]

As described above, according to the present invention, two or more layers of metal wiring can be connected via two or more via holes having a margin for mask alignment. In addition, conventionally, since connection was made using a tapered via hole,
The opening diameters of the via holes were all the same, and the mask alignment margin was strict, which was not suitable for mass production. However, according to the present invention, since there is sufficient mask alignment allowance and the via holes are directly connected to each other, the degree of integration of the semiconductor integrated circuit device can be improved, and the chip area can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of an embodiment of a semiconductor integrated circuit device of the present invention.

2 is a cross-sectional view of the semiconductor integrated circuit device of FIG. 1 taken along the line AA ';

FIG. 3 is an enlarged view of a connection portion between a second via hole and a third via hole of the semiconductor integrated circuit device of FIG. 1;

FIG. 4 is a sectional view showing a configuration of an embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 5 is a diagram showing a manufacturing process of the embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 6 is a diagram showing a manufacturing process of the embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 7 is a diagram showing a manufacturing process of the embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 8 is a diagram showing a manufacturing process of the embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 9 is a diagram showing a manufacturing process of the embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 10 is a diagram showing a layout obtained by synthesizing the layout of each layer in the embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 11 is a diagram showing a configuration of another embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 12 is a diagram showing a configuration of a semiconductor integrated circuit device according to a conventional technique.

FIG. 13 is a plan view of another conventional semiconductor integrated circuit device.

14 is a cross-sectional view of the manufacturing process of the semiconductor integrated circuit device of FIG. 13 along line BB ';

FIG. 15 is a cross-sectional view of the semiconductor integrated circuit device of FIG. 13 in a manufacturing step along the line BB ';

16 is a cross-sectional view of the semiconductor integrated circuit device of FIG. 13 in a manufacturing step along the line BB ';

17 is a cross-sectional view of the manufacturing process of the semiconductor integrated circuit device of FIG. 13 along line BB ';

[Explanation of symbols]

2,102 semiconductor substrate 4,52,104 first interlayer insulating film 5,15,25,35,65 photoresist 6,106 first wiring 8,64,108 second interlayer insulating film 10,110 second Wiring 12, 112 Third interlayer insulating film 14, 114 Third wiring 16, 116 Cover film 18, 118 First via hole 20, 120 Second via hole 22, 122 Third via hole 24, 34, 44 Ti Films 26, 32, 36, 42, 46, 49 TiN film 28, 38, 48 Tungsten 30, 40, 47 Aluminum-based alloy film 50 Silicon substrate 54, 56, 66, 68 Via hole 58, 60, 70, 72 Tungsten plug 62 the opening diameter D ₃ of 74, 76, 78 wiring 120, 122 via hole 80 protective layer D ₂ the second via hole third via Hole opening diameter D _m Allowance for mask alignment

Claims (7)

[Claims] A first insulating layer formed on the lower wiring and having a first via hole; and a second insulating layer formed on the lower wiring and a second via hole formed on the first insulating layer. A second insulating layer formed; and an upper wiring formed on the second insulating layer, wherein the lower wiring is connected to the upper wiring via the first via hole and the second via hole. Connected to the second
Wherein the via hole is directly connected to the first via hole, and a sectional shape of one of the first via hole and the second via hole falls within a sectional shape of the other via hole. Circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein said upper wiring and said lower wiring are made of an aluminum alloy. 3. The semiconductor integrated circuit device according to claim 1, wherein said first and second via holes are filled with a metal. 4. The semiconductor integrated circuit device according to claim 3, wherein said metal is tungsten. 5. The semiconductor device according to claim 1, wherein said first and second via holes have a circular cross section.
5. The semiconductor integrated circuit device according to 3 or 4. 6. A cross section of the first and second via holes having a rectangular cross section.
5. The semiconductor integrated circuit device according to 3 or 4. 7. A step of forming a lower wiring, a step of forming a first insulating layer on the lower wiring having a first via hole, and a step of forming a first via hole on the lower wiring. Second on insulating layer
Forming an upper layer wiring on the second insulating layer; and forming the upper layer wiring through the first via hole and the second via hole. Connected to the second
Is directly connected to the first via hole, and the sectional shape of one of the first via hole and the second via hole falls within the sectional shape of the other via hole. Of manufacturing a semiconductor integrated circuit device.