JPH08316310A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: To provide a method for manufacturing a semiconductor device which forms a contact hole reaching each layer without forming an isolated pattern in an intermediate layer. CONSTITUTION: The first interlayer insulation film 13 is formed on a substrate 11 on which the first conductive pattern 12a is formed. After the second conductive pattern 15a consisting of a metal group material and a protection pattern 16a consisting of a silicon nitride system film material, on the top face of the pattern 15a, are formed on the first interlayer insulation film 13, the second interlayer insulation film 17 is so formed on the first interlayer insulation film 13 as to cover the second conductive pattern 15a and the protection pattern 16a. A resist pattern 18 is formed on the second interlayer insulation film 17, and then, by etching the first interlayer insulation film 13 and the second interlayer insulation film 17 with the pattern 18 as a mask, the first contact hole 17a reaching the protection pattern 16a and the second contact hole 17b reaching the first conductive pattern 12a are formed. The protection pattern 16a on the bottom of the first contact hole 17a is removed by etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art In a manufacturing process of a semiconductor device having a multilayer wiring structure, a contact hole connected to a lower layer wiring and a contact hole connected to an intermediate layer wiring are formed as follows.

First, as shown in FIG. 4A, a substrate 31
A contact hole 33 a connecting to the lower layer wiring 32 is formed in the first interlayer insulating film 33 covering the upper lower layer wiring 32, and the inside thereof is filled with a plug 34. Next, as shown in FIG. 4B, the wiring layer formed on the first interlayer insulating film 33 is etched to form the intermediate layer wiring 35a and the isolated pattern 35b connected only to the plug 34. . afterwards,
A second interlayer insulating film 36 is formed on the first interlayer insulating film 33 in a state of covering the intermediate layer wiring 35a and the isolated pattern 35b. Then, the second using the resist pattern 37 as a mask
The first contact hole 36a reaching the intermediate wiring 35a and the isolated pattern 35b by etching the interlayer insulating film.
And a second contact hole 36b connected to.
Then, as shown in FIG. 4C, the plug 3 is formed in the first contact hole 36a and the second contact hole 36b.
8, the upper wiring 39 connected to each plug 38 is formed on the second interlayer insulating film 36.

In the method of manufacturing a semiconductor device, the second contact hole 36b connected to the lower layer wiring 32 via the isolated pattern 35b and the plug 34 is formed, so that the first contact hole 36a and the second contact hole 36a are formed. The etching depth when forming the holes 36b becomes constant. Therefore, excessive over-etching of the intermediate layer wiring 35a is prevented, and an insulating etching product composed of the constituents of the intermediate layer wiring 35a and the resist pattern 37 adheres to the etching sidewall to cause contact failure. Can be prevented.

[0005]

However, the above-mentioned method of manufacturing a semiconductor device has the following problems. That is, as the degree of integration and functionality of semiconductor devices increases, the miniaturization of each pattern forming the semiconductor device is progressing. Then, as the miniaturization of the isolated pattern that is independently formed without connecting to the intermediate layer wiring progresses, the bottom area of the resist pattern that serves as an etching mask for forming the isolated pattern also decreases, and the resist pattern becomes It easily falls.

Further, when the number of isolated patterns arranged in each intermediate layer increases as the number of intermediate layers increases when the number of layers increases as the integration of the semiconductor device increases. However, it is necessary to form the isolated pattern with a pattern width that considers misalignment of the isolated pattern itself with respect to the formation position of the plug and misalignment of the second contact hole with the isolated pattern. Also needs to be formed with a large pattern width. Therefore, as shown in FIG. 4C, it is necessary to widen the pitch W ₃ of the intermediate wiring 35a formed on the first interlayer insulating film 33 in the same manner as the isolated pattern 35b, and the integration degree of the semiconductor device is increased. Has become a factor that hinders the improvement of.

Further, the resist pattern formed in a state of being isolated from the surroundings tends to be formed smaller than the design due to problems of exposure property and developability. However, with the progress of high integration, the interval between each pattern is set to the minimum, and it is difficult to increase the design value in consideration of the reduction of the resist pattern due to the exposure property and the developability. Is coming. In such a case, as shown in FIG. 4B, the isolated pattern 35b is also made smaller than the design pattern width w ₃ , and the isolated pattern 35b is displaced from the formation position of the plug 34 or the second contact hole. 36
It becomes impossible to absorb misalignment when forming b. This causes a contact failure.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device in which a contact hole reaching each layer can be formed without forming an isolated pattern in the intermediate layer.

[0009]

A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises a method of forming a metal-based material sandwiched between a first interlayer insulating film and a second interlayer insulating film above the first interlayer insulating film. A protective pattern made of a silicon nitride film material is formed on the second conductive pattern. A first contact hole reaching the protection pattern is formed by etching the second interlayer insulating film, and a second contact hole reaching the first conductive pattern is formed by etching the second interlayer insulating film and the first interlayer insulating film. Form. Then, the protective pattern on the bottom surface of the first contact hole is removed by etching to expose the second conductive pattern.

[0010]

According to the method of manufacturing a semiconductor device described above, a protective pattern made of a silicon nitride based film material is formed on the second conductive pattern, so that the first contact hole and the second contact hole are formed. In the etching of the first interlayer insulating film and the second interlayer insulating film, the protective pattern serves as an etching mask for the second conductive pattern. Therefore, the etching proceeds to the first conductive pattern on the bottom surface of the second contact hole without etching the second conductive pattern on the bottom surface of the first contact hole. afterwards,
By removing the protective pattern on the bottom surface of the first contact hole by etching, a first contact hole reaching the second conductive pattern and a second contact hole reaching the first conductive pattern are formed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. In the first step shown in FIG. 1A, for example, the substrate 1 whose surface is covered with a silicon oxide film is used.
An aluminum-based material layer as a metal-based material layer 12 forming the first conductive pattern 12a and a titanium nitride layer thereabove are sputter-deposited on the first layer. For the aluminum-based material layer, for example, aluminum, aluminum-silicon, aluminum-copper, or the like is used and is formed to a film thickness of 500 to 1000 nm. Further, the titanium nitride layer is formed to have a film thickness of 100 nm. This titanium nitride layer becomes an antireflection film when a resist pattern is formed on the aluminum-based material layer by the lithography method. As the metal-based material layer 12, other than the above, tungsten (W), copper (Cu), or the like may be used.

Next, a resist pattern (not shown here) is formed on the metal-based material layer 12 by a lithography method, and the metal-based material is subjected to reactive ion etching (Reactive Ion Etching: hereinafter referred to as RIE) using the resist pattern as a mask. The layer 12 is patterned.
Here, for example, RIE is performed using BCl ₃ / Cl ₂ as a reaction gas. As a result, the first conductive pattern 12a made of the metal-based material layer 12 is formed on the substrate 11. The first conductive pattern 12a includes a wiring portion and a contact portion formed by widening the area of this portion.

Next, for example, TEOS (tetraetoxysilan)
e: (C ₂ H ₅ O) ₄ Si) by a chemical vapor deposition (Chemical Vapor Deposition: hereinafter referred to as CVD) method using silicon oxide on the substrate 11 with the first conductive pattern 12a embedded therein. A first interlayer insulating film 13 is formed. The first interlayer insulating film 13 is formed to have a film thickness of 0.5 to 1.0 μm on the first conductive pattern 12a, for example.

Thereafter, by RIE using a resist pattern (not shown) as a mask, a contact hole 13a for connecting the first conductive pattern 12a and the second conductive pattern formed on the first interlayer insulating film 13 in the next step.
Are formed on the first interlayer insulating film 13. Then, the contact hole 13a is filled with a plug 14 made of, for example, tungsten (W).

Next, in the second step shown in FIG. 1B, the metal-based material layer 15 forming the second conductive pattern 15a is formed on the first interlayer insulating film 13. This metallic material layer 15
Has a laminated structure of an aluminum-based material layer and an upper titanium nitride layer, similar to the first conductive pattern 12a. Then, the protective pattern 16a is formed on the metal-based material layer 15.
The silicon nitride-based material layer 16 constituting the is formed. The silicon nitride-based material layer 16 is made of, for example, plasma silicon nitride having a film thickness of 200 nm formed by a plasma CVD method. The above silicon nitride-based material layer 1
6 may be silicon oxynitride. In addition, the film thickness of the silicon nitride-based material layer 16 will be changed in the next step to the second interlayer insulating film 1
7 and the first interlayer insulating film 13 are etched, the protective pattern 16a made of the silicon nitride material layer 16 is formed.
Is not removed.

After that, a resist pattern (not shown here) is formed on the silicon nitride material layer 16, and the silicon nitride material layer 16 and the metal material layer 15 are patterned by RIE using the resist pattern as a mask. The RIE of the silicon nitride layer-based material layer 16 is performed by using CHF ₃ / CF ₄ / Ar as a reaction gas, for example. For the subsequent RIE of the metal-based material layer 15, the same reaction gas as in the first step is used. By this, the first
A second conductive pattern 15a made of the metal-based material layer 15 is formed on the interlayer insulating film 13, and the second conductive pattern 15a is formed.
Protective pattern 1 made of silicon nitride-based material layer 16 on top
6a is formed.

The second conductive pattern 15a is composed of a wiring portion and a contact portion formed by widening the area of this portion. One of the contact portions is the plug 14 formed in the first interlayer insulating film 13. Is formed to connect to. It should be noted that the second conductive pattern 15a is not formed with an isolated pattern of only the contact portion.

Next, a second interlayer insulating film 17 made of silicon oxide is formed on the first interlayer insulating film 13 by the TEOS-CVD method, for example, with the second conductive pattern 15a and the protective pattern 16a being embedded. The first interlayer insulating film 13 is, for example, 0.5 on the second conductive pattern 15a.
The film is formed to a film thickness of ˜1.0 μm.

Thereafter, in the third step shown in FIG. 1 (3),
A resist pattern 18 is formed on the second interlayer insulating film 17 by the lithography method. Then, only the second interlayer insulating film 17 is etched by RIE using the resist pattern 18 as a mask to remove the second conductive pattern 15a.
The first contact hole 17a reaching the upper protective pattern 16a is formed, and the second interlayer insulating film 17 and the first contact hole 17a are formed.
The interlayer insulating film 13 is etched to etch the first conductive pattern 12
A second contact hole 17b reaching a is formed.

In the above RIE, the first interlayer insulating film 13 and
Etching between the second interlayer insulating film 17 and the protective pattern 16a
The reaction gas has C
_FourF ₈/ CO / Ar is used. As a result,
The protective pattern 16a is exposed at the bottom of the tact hole 17a.
After the etching progresses until the
Etch 16a is the bottom of the first contact hole 17a
Become a gumask. On the other hand, the second contact hole 17b
At the bottom, the second interlayer insulating film 17 and the first interlayer insulating film 13
Etching progresses to expose the first conductive pattern 12a
It

Next, CHF ₃ / CF ₄ / Ar is added to the reaction gas.
By RIE using the first contact hole 17a
The portion of the protection pattern 16a made of silicon nitride exposed at the bottom of the first contact hole 17a is removed, and the second conductive pattern 15a is exposed at the bottom of the first contact hole 17a. Here, the first conductive pattern 12a at the bottom of the second contact hole 17b is etched, but the protective pattern 16a
The first conductive pattern 12 with respect to the silicon nitride constituting the
The etching rate of titanium nitride on the surface a is low. Therefore, this titanium nitride layer serves as an etching mask for the first conductive pattern 12a. After that, the resist pattern (18) on the second interlayer insulating film 17 is removed.

As described above, the second conductive pattern 15a
After forming the first contact hole 17a reaching the first contact pattern 17a and the second contact hole 17b reaching the first conductive pattern 12a, as shown in FIG.
The plug 19 made of tungsten (W) fills the inside of the a and the second contact hole 17b. Then, the third conductive pattern 20 having a laminated structure of an aluminum-based material layer and a titanium nitride layer similar to the first conductive pattern 12a and the second conductive pattern 15a is formed on the second interlayer insulating film 17. The third conductive pattern 20 is composed of a wiring portion and a contact portion formed by widening the area of this portion, and each contact portion is formed so as to be connected to the plug 19 formed in the second interlayer insulating film 17. To be done. As a result, a semiconductor device having a three-layer wiring structure is formed.

In the method of manufacturing a semiconductor device described above, the protective pattern 16a serves as an etching mask for the second conductive pattern 15a during etching using the resist pattern 18 as a mask, and thus the second conductive pattern 15a is not overetched before being etched. The etching can proceed to the one conductive pattern 12a. Therefore, the first contact hole 17a and the first contact hole 17a can be formed without forming an etching compound of a metal-based material forming the second conductive pattern 15a.
The second contact hole 17b, which is deeper than the contact hole 17a, can be formed by one etching.

Therefore, the upper and lower layers are formed on the first interlayer insulating film 13.
Need to form isolated patterns that connect only to layer plugs
There is no. This allows the mask to be used when forming an isolated pattern.
It is necessary to form an isolated resist pattern
It is possible to prevent collapse of the resist pattern
become. In addition, the isolated pattern may shift from the design value.
It is possible to prevent contact failure due to Further
Between the first interlayer insulating film 13 and the second interlayer insulating film 17
Compared to the case of forming an isolated pattern, it is shown in FIG.
The pitch W between the second conductive patterns 15a ₁Narrowing down
And become possible.

In the above embodiment, the metal-based material layer 12 is etched to form the first conductive pattern 12a. However, the first conductive pattern 12a may be a diffusion layer formed by introducing impurities into the surface side of the substrate 11 made of a semiconductor material. Further, in the above-described embodiment, the conductive pattern of the intermediate layer sandwiched between the interlayer insulating films is a single layer including only the second conductive pattern. However, even if the conductive pattern of the intermediate layer is a plurality of layers of two or more layers, the same effect as in the above embodiment can be obtained.

[0026]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the first interlayer insulating film and the second upper layer is formed.
A first contact reaching the protection pattern without etching the second conductive pattern by forming a protection pattern made of a silicon nitride-based film material serving as an etching mask on the second conductive pattern sandwiched by the interlayer insulating film. It becomes possible to form a hole and a second contact hole reaching the first conductive pattern below the first interlayer insulating film. Then, by removing the protective pattern on the second conductive pattern after the etching, the first contact hole reaching the second conductive pattern and the second contact can be formed without forming an isolated pattern on the first interlayer insulating film. Holes can be formed. Therefore, the layout area of the second conductive pattern in the first interlayer insulating film can be increased to improve the degree of integration of the semiconductor device. Further, it is possible to prevent the collapse of an isolated resist pattern that serves as a mask for forming an isolated pattern and to prevent an increase in contact resistance due to the deviation of the formation of the isolated pattern from the design value, thus improving the reliability of the semiconductor device. It becomes possible to plan.

[Brief description of drawings]

FIG. 1 is a first diagram illustrating an embodiment.

FIG. 2 is a second diagram illustrating an example.

FIG. 3 is a diagram illustrating an effect of the embodiment.

FIG. 4 is a diagram illustrating a conventional example.

[Explanation of symbols]

Reference Signs List 11 substrate 12a first conductive pattern 13 first interlayer insulating film 15a second conductive pattern 16a protective pattern 17 second interlayer insulating film 17a first contact hole 17b second contact hole

Claims (1)

[Claims] 1. A first step of forming a first interlayer insulating film on a substrate on which a first conductive pattern is formed, a second conductive pattern made of a metal-based material on the first interlayer insulating film, and the first step. After forming a protective pattern made of a silicon nitride-based film material on the second conductive pattern, a second interlayer insulating film is formed on the first interlayer insulating film in a state of covering the second conductive pattern and the protective pattern. And a first contact hole reaching the protection pattern by etching the second interlayer insulating film, and
A third step of forming a second contact hole reaching the first conductive pattern by etching the second interlayer insulating film and the first interlayer insulating film; and etching the protective pattern exposed on the bottom surface of the first contact hole. And a fourth step of removing by means of a method of manufacturing a semiconductor device.