JPH07153756A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide reliable connection between upper and lower conductive parts through a through hole formed in an interlayer insulating film. CONSTITUTION:A dummy pattern 15 is used as a buffer for a step part. The dummy pattern 15 is formed just under a through hole 10 located in a region, where a semiconductor device is not formed, so that an interlayer insulating film 9 has almost equal thicknesses between upper regions, where the semiconductor device is formed and where the semiconductor device is not formed, above a first-layer aluminum wiring 8. Then, an etching condition is set easily when a through hole is opened in an interlayer insulating film 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to improve connection reliability between upper and lower wirings in a semiconductor integrated circuit device having a multilayer wiring structure. .

[0002]

2. Description of the Related Art In recent years, wiring has become more and more multi-layered along with the progress of high integration of LSI devices. For example, in a high-speed memory LSI using bipolar transistors,
A multilayer wiring structure such as layer Al wiring + three layer polysilicon has been realized.

In an LSI device having such a multilayer wiring structure, flattening of the interlayer insulating film is an essential technique in order to prevent a decrease in connection reliability between upper and lower wirings due to a step difference in the underlying layer. There is.

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In a bipolar memory LSI having a 1-wiring + three-layer polysilicon structure, a base extraction electrode of a bipolar transistor forming a memory cell is a first-layer polysilicon, an emitter extraction electrode is a second-layer polysilicon, and a resistance element is a third-layer. Each is made of polysilicon.

For this reason, as shown in FIG. 3, a step (corresponding to the film thickness of the above three layers of polysilicon) is formed between the element forming region (A) and the non-forming region (B) on the semiconductor substrate. S) occurs, and as a result, the first-layer Al wirings 20a and 20b are formed on the memory cells, and then the interlayer insulating film 21 is deposited on the first-layer Al wirings 20a and 20b to cover the surface thereof. When planarized, the film thickness of the interlayer insulating film 21 is different between the upper part of the first layer Al wiring 20a formed in the element forming region (A) and the upper part of the first layer Al wiring 20b formed in the non-forming region (B). Come on.

Therefore, if an attempt is made to form a through hole for connecting the first-layer Al wirings 20a, 20b and the second-layer Al wiring by opening the interlayer insulating film 21, the same etching step is performed to obtain a depth. Different through holes 22a, 2
Since 2b must be formed, it becomes extremely difficult to set etching conditions.

Therefore, an object of the present invention is to provide a technique capable of improving the connection reliability of upper and lower layer wirings electrically connected through through holes formed in the interlayer insulating film.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

In the semiconductor integrated circuit device of the present invention, among a plurality of through holes formed in the interlayer insulating film above the semiconductor element formed on the semiconductor substrate, the semiconductor element is directly below the through hole in a region where the semiconductor element is not formed. A dummy pattern for arranging steps is arranged in the.

[0011]

According to the above-mentioned means, the semiconductor element is formed by arranging the dummy pattern for buffering the step just below the through hole opened in the interlayer insulating film in the area where the semiconductor element is not formed. Since the film thickness of the interlayer insulating film can be made substantially the same on the Al wiring formed in the region and the Al wiring formed in the region where the semiconductor element is not formed, the through hole is formed. In this case, it becomes easy to set etching conditions.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is an enlarged view of the non-formed region (region where no semiconductor element is formed) shown in FIG.
A field insulating film 2 made of silicon oxide for element isolation is formed on a semiconductor substrate 1 made of silicon single crystal, and insulating films 3, 4, 5 made of silicon oxide are formed on the field insulating film 2. 6 and a BPSG film 7 are formed.

A first layer Al wiring 8 is formed on the BPSG film 7, and a film thickness of silicon oxide whose surface is flattened by, for example, a quartz sputtering method is formed on the first layer Al wiring 8. An interlayer insulating film 9 having a thickness of about 2.5 μm is formed. The first-layer Al wiring 8 is electrically connected to the second-layer Al wiring 11 on the interlayer insulating film 9 through the through hole 10 formed in the interlayer insulating film 9.

Immediately below the through hole 10 formed in the interlayer insulating film 9, a first layer polysilicon 12, a second layer polysilicon 13 and a third layer polysilicon 14 are sequentially deposited to form a step buffer. Dummy pattern 15 is arranged. The film thickness of each of the first-layer polysilicon 12, the second-layer polysilicon 13, and the third-layer polysilicon 14 is about 2000 Å.

On the other hand, although not shown, a bipolar transistor and a resistance element are formed in a region (element formation region shown in FIG. 3) adjacent to FIG. 1 on the semiconductor substrate 1. In the bipolar transistor, the base extraction electrode is formed of the first layer polysilicon 12, the emitter extraction electrode is formed of the second layer polysilicon 13, and the resistance element is formed of the third layer polysilicon 14. Has been formed.

That is, the dummy pattern 15 is simultaneously formed in the step of forming the first layer polysilicon 12 which constitutes a part of the dummy pattern 15 in the step of forming the base lead electrode of the bipolar transistor, and the second layer polysilicon 13 forms the emitter lead electrode. Are simultaneously formed in the step of forming the resistance element, and the third-layer polysilicon is formed simultaneously in the step of forming the resistance element.

As described above, according to the present embodiment in which the dummy pattern 15 for buffering the step is arranged immediately below the through hole 10 in the region where the semiconductor element is not formed, the semiconductor pattern is formed in the region where the semiconductor element is formed. Since it is possible to make the film thickness of the interlayer insulating film 9 substantially the same on the upper part of the first-layer Al wiring and the upper part of the first-layer Al wiring 8 opened in the region where the semiconductor element is not formed, It becomes easy to set the etching conditions when the through hole 10 is formed by opening the insulating film 9, and the first layer Al wiring 8 and the second layer Al wiring 11 electrically connected through the through hole 10 are formed. The connection reliability can be improved.

Further, according to this embodiment, since the dummy pattern is simultaneously formed in the step of forming the semiconductor element, the number of manufacturing steps does not increase.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the embodiments and can be variously modified without departing from the scope of the invention. Needless to say.

In the above-described embodiment, the step-difference dummy pattern is formed by using the first to third layer polysilicon, but the present invention is not limited to this. For example, as shown in FIG. , 17, 18 may be used to form the dummy pattern 15. However, in this case, the insulating film 1
A step of forming 6, 17, 18 is required.

In the above embodiment, the dummy pattern is formed immediately below the through hole connecting the first-layer Al wiring and the second-layer Al wiring, but the present invention is not limited to this, and the dummy pattern is not limited to the second-layer Al wiring. The dummy pattern can be formed immediately below the through hole connecting to the third layer Al wiring, or directly below the through hole connecting between the wirings in the upper layer.

In the above description, the case where the invention is applied to an LSI having a bipolar transistor has been described, but the invention is not limited to this. For example, in a DRAM having a stack-structured capacitor, the film thickness of the interlayer insulating film is formed as an element. It can be widely applied to LSIs having different regions and non-formation regions.

[0024]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the present invention, it is easy to set etching conditions when a through hole is formed by opening an interlayer insulating film. Therefore, a connection between upper and lower wirings electrically connected through this through hole is formed. The reliability can be improved.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 3 is a main-portion cross-sectional view showing a step on a semiconductor substrate.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Field Insulating Film 3 Insulating Film 4 Insulating Film 5 Insulating Film 6 Insulating Film 7 BPSG Film 8 First Layer Al Wiring 9 Interlayer Insulating Film 10 Through Hole 11 Second Layer Al Wiring 12 First Layer Polysilicon 13 Second Layer Polysilicon 14 Third Layer Polysilicon 15 Dummy Pattern 16 Insulating Film 17 Insulating Film 18 Insulating Film 20a First Layer Al Wiring 20b First Layer Al Wiring 21 Interlayer Insulating Film 22a Through Hole 22b Through Hole

Claims (4)

[Claims] 1. A semiconductor integrated device in which an interlayer insulating film is deposited on a semiconductor element formed on a semiconductor substrate, and a lower layer wiring and an upper layer wiring are electrically connected through a through hole formed in the interlayer insulating film. In the circuit device, a dummy pattern for buffering a step is formed directly under a through hole formed in a region where the semiconductor element is not formed among a plurality of through holes formed in the interlayer insulating film. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the surface of the interlayer insulating film is flattened. 3. The semiconductor integrated circuit device according to claim 1, wherein the dummy pattern is made of a conductive film formed in the same step as a conductive film forming a part of the semiconductor element. 4. The semiconductor integrated circuit device according to claim 1, wherein the dummy pattern is made of an insulating film.