JP2596848B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] First mask layer (Si ₃ N ₄ film, etc.) and second mask layer (SiO ₂ film, etc.) serving as mask layers for etching and conductive film growth
The method of forming the electrode contact windows having different depths in a self-alignment manner, easily embedding the selective chemical vapor deposition conductive film into the electrode contact windows having different depths, and preventing the interlayer insulating film from slipping easily can be easily achieved. Can be realized in
The connection between the upper-layer wiring body made of the same layer and the plurality of conductive regions formed at the lower portion and having the electrode contact windows with different depths is made via conductive films in which the electrode contact windows with different depths are respectively buried flat. Therefore, since each conductive region can be directly connected to an upper wiring body composed of the same layer, high integration by increasing the degree of freedom of wiring can be achieved. It is possible to manufacture a semiconductor device suitable for mass production that enables high reliability by enabling easy connection from a thick upper wiring body capable of increasing the density, thereby increasing the life of the wiring body. it can.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MIS and a bipolar semiconductor device, and more particularly, to a MIS and a bipolar semiconductor device having a plurality of conductive regions having electrode contact windows having different depths and capable of simultaneously connecting an upper wiring body of the same layer. The present invention relates to a method for manufacturing an integrated and highly reliable semiconductor device.

Conventionally, for the connection between the upper wiring body and the lower conductive region of the same layer, a technique for embedding a conductive film evenly in electrode contact windows of different depths has not been developed. For example, when connecting from an upper wiring body to an impurity region formed in a semiconductor substrate below a lower wiring body, the connection exists only below a plurality of conductive regions having the upper wiring body. However, since it is necessary to connect all the wiring bodies to be interposed as wiring bodies of the intermediate layer, the degree of freedom of wiring is restricted, and the problem of hindering high integration has become significant. Therefore, there is a demand for a method of manufacturing a semiconductor device capable of burying a conductive film evenly in electrode contact windows of different depths and simultaneously connecting to an upper wiring body of the same layer.

[Prior Art] FIG. 5 is a schematic side sectional view of a semiconductor device obtained by a conventional manufacturing method, where 51 is a p-type silicon (Si) substrate, and 52 is
Is a p-type channel stopper region, 53a is an n + type impurity region through which a relatively small current flows, 53b is an n + type impurity region through which a relatively large current flows, 54 is a field oxide film, 55
Is an oxide film for impurity blocking, 56 is a first phosphosilicate glass (PSG) film, 57 is a first electrode contact window, 58 is a first electrode contact window buried conductive film, 59a, 59b, and 59c are first-layer conductive films. Al wiring, 60 is a second phosphosilicate glass (PSG) film, 61
Denotes a second electrode contact window, 62 denotes a conductive film embedded in the second electrode contact window, and 63 denotes a second layer Al wiring.

In the figure, an n + type impurity region 53a through which a relatively small current flows through a p- type silicon (Si) substrate 51 separated by a field oxide film 54 and an n through which a relatively large current flows
+ -Type impurity regions 53b are formed, and
A first electrode contact window 57 is formed by opening a phosphor silicate glass (PSG) film 56 and an impurity blocking oxide film 55,
The first electrode contact windows 57 are connected to separate first-layer Al wirings (59b, 59c) via conductive films 58 embedded therein. Another layer of Al wiring 59a is formed on the first phosphosilicate glass (PSG) film 56 on the field oxide film 54. The first Al wiring 59c and the field oxide film 54 on the n + type impurity region 53b through which a relatively large current flows.
A second electrode contact window 6 in which a second phosphosilicate glass (PSG) film 60 is formed on the upper first Al wiring 59a, respectively.
1 is formed, and is connected to a second-layer Al wiring 63 via a conductive film 62 embedded in the second electrode contact window 61. Here, a direct connection cannot be formed between the thick second-layer Al wiring 63 and the n + -type impurity region 53b through which a relatively large current flows (in other places, the second-layer Al wiring 63 is not used).
The electrode contact windows of different depths could not be buried flat with the conductive film because of the necessity of establishing a connection with the first Al wiring 59). The first Al wiring 59c is interposed as an intermediate layer. Therefore, the first layer of Al that is connected to the adjacent n + type impurity region 53a through which a relatively small current flows.
There is a problem that high integration is difficult due to the necessity of providing an interval with the wiring 59b.

[Problem to be Solved by the Invention] The problem to be solved by the present invention is to form a highly integrated and highly reliable semiconductor device with an improved degree of freedom in wiring as shown in the conventional example. Another object of the present invention is to provide a method of manufacturing a semiconductor device suitable for mass production, which enables direct connection with good step coverage by a wiring body of the same layer to a plurality of conductive regions having electrode contact windows having different depths.

[Means for Solving the Problem] The above problem is caused by selectively forming a first conductive region on a semiconductor substrate or on a semiconductor substrate via an insulating film, and laminating a first interlayer insulating film. Performing a step of selectively forming a second conductive region on the first interlayer insulating film, laminating a second interlayer insulating film, and forming a first conductive region on the second interlayer insulating film. And (a) selectively opening the first mask layer and the second interlayer insulating film on the first and second conductive regions; and
A step of burying an electrode contact window opened on the second conductive region with a first selective chemical vapor deposition conductive film, a step of stacking an insulating film, a step of stacking an insulating film, By selectively etching away the insulating film using the photoresist layer formed on the second conductive region as a mask layer, a second conductive film is selectively formed on the first selective chemical vapor deposition conductive film on the second conductive region. Forming a mask layer, and opening the first interlayer insulating film in which the second interlayer insulating film on the first conductive region is opened, and removing the photoresist layer And a step of burying a second selective chemical vapor deposition conductive film in an electrode contact window on the first conductive region using the second mask layer, or (b) the first and second conductive layers. The first mask layer over the region, the first and Selectively opening the second interlayer insulating film, and filling the electrode contact window opened on the second conductive region with a first selective chemical vapor deposition conductive film to be flat, and Partially embedding an electrode contact window opened on the conductive region of step (a), laminating an insulating film, and insulating the first mask layer and the selectively formed photoresist layer as a mask layer. By selectively etching away the film, a second layer is selectively formed on the first selective chemical vapor deposition conductive film on the second conductive region.
Forming a mask layer, removing the photoresist layer, and forming a second selective chemical vapor in an electrode contact window buried halfway over the first conductive region by the second mask layer. (A) or (b) after any one of the steps of: (a) and (b), etching and removing the second mask layer by the first mask layer; and (b) the first mask. The problem is solved by a method of manufacturing a semiconductor device according to the present invention, which includes a step of removing a layer by etching and a step of selectively forming an upper wiring body.

[Operation] That is, in the method of manufacturing a semiconductor device according to the present invention, a first mask layer (such as a Si ₃ N ₄ film) and a second mask layer (such as a SiO ₂ film) serving as mask layers for etching and conductive film growth are provided. ), The electrode contact windows of different depths are formed in a self-aligned manner, the selective chemical vapor deposition conductive film is buried flat in the electrode contact windows of different depths, and the interlayer insulating film is prevented from being slipped. Since it can be easily realized, the connection between the upper layer wiring body formed of the same layer and the plurality of conductive regions having the electrode contact windows having different depths formed in the lower portion bury the electrode contact windows having different depths flat. It is possible to easily form a structure that is simultaneously formed via the conductive film. Therefore, there is no need for a wiring body interposed in order to adjust the depth of the electrode contact window, and the conductive layer is formed of the same layer as each conductive region via a conductive film in which electrode contact windows of different depths are respectively buried flat. High integration by increasing the degree of freedom of wiring because it can be directly connected to the upper layer wiring body.The upper layer wiring body with good step coverage is formed on a conductive film in which electrode contact windows of different depths are buried flat. The high reliability can be realized because the life of the wiring body can be increased by easily and freely connecting the upper wiring body that can be formed and having a large film thickness capable of obtaining a large current density. That is, it is possible to manufacture a semiconductor device suitable for mass production that enables formation of a highly integrated and highly reliable semiconductor integrated circuit.

EXAMPLES Hereinafter, the present invention will be described specifically with reference to illustrated examples.

FIG. 1 is a schematic side sectional view of a semiconductor device obtained by the manufacturing method of the first embodiment of the present invention, and FIG. 2 is a schematic side sectional view of the semiconductor device obtained by the manufacturing method of the second embodiment of the present invention. FIGS. 3 (a) to 3 (f) {including partially modified steps (g) to (i)} are cross-sectional views of steps in the first embodiment of the method for manufacturing a semiconductor device of the present invention, and FIGS. Figures (a) to (d)
FIG. 6 is a process sectional view of a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

The same objects are denoted by the same reference numerals throughout the drawings. The terms in [] are broader terms used in the claims, and indicate the correspondence with more specific terms used in the examples.

FIG. 1 shows a first embodiment of the present invention using a p-type silicon substrate.
1 is a schematic side sectional view of a semiconductor device obtained by the manufacturing method according to the embodiment of the present invention, wherein 1 is a p-type silicon substrate [semiconductor substrate] of about 10 ¹⁵ cm ^-3 and 2 is a p-type channel stopper of about 10 ¹⁷ cm ^-3. The region 3a is an n + type impurity region of about 10 ²⁰ cm ^-3 where a relatively small current flows, and the region 3b is a relatively large current flows
N + -type impurity region of about 10 ²⁰ cm ^-3 [first conductive region],
4 is a field oxide film of about 600 nm, 5 is an oxide film for impurity blocking of about 35 nm, 6 is a first phosphor silicate glass (PSG) film of about 600 nm [first interlayer insulating film], and 7 is 0.8 μm in diameter.
About the first electrode contact window, 8 is the first electrode contact window embedded conductive film, 9a [the second conductive region], 9b is 0.1.
The first layer of Al wiring of about 5 μm, 10 is a second phosphosilicate glass (PSG) film of about 600 nm [second interlayer insulating film], and 11a is 0.2 mm in diameter.
8 μm shallow second electrode contact window [electrode contact window opened on second conductive region], 11b has a diameter of 0.8 μm
m, a second electrode contact window [electrode contact window opened on the first conductive region], and 12a a shallow second electrode contact window buried conductive film (selective chemical vapor deposition tungsten silicide film) [ First selective chemical vapor deposition conductive film], 12b is a deep second electrode contact window filling conductive film (selective chemical vapor deposition tungsten silicide film)
[Second Selective Chemical Vapor Deposition Conductive Film], 13 denotes a second layer Al wiring (upper wiring body) of about 1 μm.

In FIG. 1, an n + -type impurity region 3 a through which a relatively small current flows and an n + -type impurity region 3 b through which a relatively large current flows are formed on a p − -type silicon substrate 1 separated by a field oxide film 4. In the n + -type impurity region 3a through which a very small current flows, a first electrode contact window 7 in which a first phosphosilicate glass (PSG) film 6 and an impurity blocking oxide film 5 are opened is formed. It is connected to a first-layer Al wiring 9b via a conductive film 8 in which a contact window 7 is embedded. On the first phosphosilicate glass (PSG) film 6 on the field oxide film 4, another Al wiring 9a is formed, and the second Al wiring 9a is formed with a second phosphor silicate. A shallow second electrode contact window 11a formed by opening a glass (PSG) film 10 is formed, and a second layer Al wiring 13 is formed via a conductive film 12a embedded in the shallow second electrode contact window 11a.
It is connected to the. On the other hand, a relatively large current n
In the + type impurity region 3b, a second phosphosilicate glass (PSG) film 1 is formed.
0, a deep second electrode contact window 11b in which the first phosphosilicate glass (PSG) film 6 and the impurity blocking oxide film 5 are opened
Is formed, and is connected to the second-layer Al wiring 13 via a conductive film 12b buried in the deep second electrode contact window 11b. Therefore, there is no need for a wiring body interposed in the middle to adjust the depth of the electrode contact window as seen in the conventional example, and each of the electrode contact windows of different depths is formed via a conductive film that is buried flat. Since the upper wiring body composed of the same layer as the conductive region can be connected, high integration by increasing the degree of freedom in wiring can be achieved by increasing the step coverage on the conductive film in which electrode contact windows of different depths are respectively buried flat. It is possible to form a good upper wiring body and to easily and freely connect from a thick upper wiring body that can provide a large current density, thereby increasing the life of the wiring body and enabling high reliability. can do.

In the above embodiment, the case where the impurity region and the wiring body are used as the conductive regions having the electrode contact windows having different depths is described. However, the present invention can be applied to the case where the wiring bodies have different layers.

FIG. 2 is a schematic side sectional view of a semiconductor device obtained by the manufacturing method according to the second embodiment of the present invention, wherein 1 is a p-type silicon substrate [first conductive region], 2, 4, and 5 are first The same thing as the figure, 6 is a phosphosilicate glass (PSG) film [second interlayer insulating film], 7a is a shallow first electrode contact window [electrode contact window opened on the second conductive region], 7b is a deep first electrode contact window [electrode contact window opened on the first conductive region], 8a is a shallow first electrode contact window buried conductive film (selective chemical vapor deposition tungsten silicide film) [ 1 selective chemical vapor deposition conductive film], 8b is a deep second
Electrode contact window embedded conductive film (selective chemical vapor deposition tungsten silicide film) [second selective chemical vapor deposition conductive film], 9 is first-layer Al wiring [upper wiring], 14a is p-type silicon substrate An n + type impurity region [second conductive region] to which a voltage different from that applied is applied, and 14b denotes an n + type impurity region to which the same voltage as that of the p− type silicon substrate is applied.

In the figure, n + type impurity regions 14a and p− to which a voltage different from that of the p− type silicon substrate 1 insulated and separated by the field oxide film 4 is applied to the p− type silicon substrate 1 are applied.
An n + -type impurity region 14 b to which the same voltage as that of the p-type silicon substrate 1 is applied is formed, and a first phosphosilicate glass (PSG) is formed in the n + -type impurity region 14 a to which a voltage different from that of the p − -type silicon substrate 1 is applied. ) Film 6 and oxide film 5 for impurity block
A shallow first electrode contact window 7a is formed,
The first electrode contact window 7a is connected to the first-layer Al wiring 9 via a conductive film 8a embedded therein. On the other hand, p-
In the n + -type impurity region 14 b to which the same voltage as that of the n-type silicon substrate 1 is applied, the first phosphosilicate glass (PSG) film 6, the impurity blocking oxide film 5, the n + -type impurity region 14 b and the p − -type silicon substrate 1 A deep first electrode contact window 7b partially opened is formed, and is connected to the first-layer Al wiring 9 via a conductive film 8b embedded in the deep first electrode contact window 7b. In this embodiment, in addition to the effects of the first embodiment, high integration in which two conductive regions are simultaneously connected to a wiring body with one deep electrode contact window can be achieved.

Next, a method for manufacturing a semiconductor device of the present invention will be described in detail. Here, only the manufacturing method relating to the formation of the semiconductor device in FIGS. 1 and 2 will be described, and the manufacturing method relating to the formation of various elements (transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit will be described. Description is omitted.

3 (a) to 3 (f) and FIG. 1 are sectional views showing the steps of the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 (a) By applying a conventional technique, a p-type channel stopper region 2, an n + -type impurity region 3a in which a relatively small current flows, and an n + -type impurity in which a relatively large current flows in a p- type silicon substrate 1. The region 3b and the field oxide film 4 are formed.

FIG. 3 (b) Next, an impurity blocking oxide film 5 of about 35 nm, 600 nm
A first degree of first phosphosilicate glass (PSG) film 6 is sequentially grown. Then, using normal photolithography technology,
Using a resist (not shown) as a mask layer, the first phosphosilicate glass (PSG) film 6 and the impurity blocking oxide film 5 are selectively etched to form a second layer on the n + type impurity region 3a through which a relatively small current flows. One electrode contact window 7 is formed. Next, the resist is removed. Next, a first selective chemical vapor deposition tungsten silicide film 8 is grown,
Is buried flat.

Next, a first Al film having a thickness of about 0.5 μm is grown by sputtering. Next, the first Al film is selectively etched using a resist (not shown) as a mask layer using a normal photolithography technique, and the first Al film is etched.
The wirings 9a and 9b are formed. Next, the resist is removed. Next, a second phosphosilicate glass (PSG) film 10, 30 of about 0.6 μm
A nitride film 15 (first mask layer) of about nm is sequentially grown.

FIG. 3 (d) Then, using a normal photolithography technique and using a resist (not shown) as a mask layer, the nitride film 15 and the second phosphosilicate glass (PSG) film 10 are selectively etched, Second electrode contact window shallow on Al wiring 9a
11a and n + type impurity region 3 through which a relatively large current flows
A shallow second electrode contact window 11a in which a first phosphosilicate glass (PSG) film 6 is somewhat left is formed on b. Next, the resist is removed. Next, a second selective chemical vapor deposition tungsten silicide film 12a is grown, and the shallow second electrode contact window 11a on the first layer Al wiring 9a is buried almost flat. (Since some of the first phosphosilicate glass (PSG) film 6 is left in the shallow second electrode contact window 11a on the n + type impurity region 3b through which a relatively large current flows,
The selective chemical vapor deposition tungsten silicide film does not grow. 3 (e) Next, a chemical vapor deposition oxide film 16 of about 30 nm is grown. Then, using normal photolithography technology,
Using the resist (not shown) as a mask layer, the chemical vapor deposition oxide film 16 is selectively etched, and the chemical vapor deposition oxide film 16 (the second Mask layer). Next, using the same resist (not shown) and the nitride film 15 as a mask layer, the remaining first phosphosilicate glass (PSG) film 6 is etched to form a shallow second n + type impurity region 3b on which a relatively large current flows. 2
Second electrode contact window 1
1b. Next, the resist is removed.

Next, a third selective chemical vapor deposition tungsten silicide film 12b is grown, and the deep second electrode contact window 11b is buried almost flat.

FIG. 1 Next, the remaining chemical vapor deposition oxide film 16 (second mask layer) is removed by etching. Next, the nitride film 15 (first mask layer) is removed by etching. Next, a second Al film of about 1 μm is grown by a sputtering method. Next, using a normal photolithography technique and using a resist (not shown) as a mask layer, the second layer Al film is selectively etched to form a second layer Al wiring 13 to complete the semiconductor device. .

In FIG. 3 (d), when a shallow second electrode contact window 11a is opened on the first layer Al wiring 9a, the first electrode contact window 3a on the n + type impurity region 3b through which a relatively large current flows. Shallow second layer with some phosphosilicate glass (PSG) film 6 left
Although the first electrode contact window 11a is formed, even if the first phosphosilicate glass (PSG) film 6 is completely etched by etching over, the step shown in FIG. By performing the steps g) to (i) and the steps of FIG. 1, the semiconductor device of FIG. 1 can be manufactured.

FIG. 3 (g) Then, using a normal photolithography technique, using a resist (not shown) as a mask layer, the nitride film 15 (first
Mask layer), the second phosphosilicate glass (PSG) film 10, the first
The phosphor silicate glass (PSG) film 6 and the impurity blocking oxide film 5 are selectively etched to form a shallow second electrode contact window 11a on the first Al wiring 9a and an n + type impurity through which a relatively large current flows. The deep second electrode contact windows 11b are simultaneously formed on the region 3b. Next, the resist is removed.

FIG. 3 (h) Next, a second selective chemical vapor deposition tungsten silicide film 12a is grown, and a relatively large current flows through the shallow second electrode contact window 11a on the first layer Al wiring 9a almost flat. Part of the deep second electrode contact window 11b on the n + -type impurity region 3b is buried.

FIG. 3 (i) Next, a chemical vapor deposition oxide film 16 of about 30 nm is grown. Then, using normal photolithography technology,
Using the resist (not shown) as a mask layer, the chemical vapor deposition oxide film 16 is selectively etched to form a second selective chemical vapor deposition tungsten silicide film 12 on the first Al wiring 9a.
The chemical vapor deposition oxide film 16 (second mask layer) is left on a. Next, the resist is removed. Next, a third selective chemical vapor deposition tungsten silicide film 12b is grown, and a part of the third selective chemical vapor deposition tungsten silicide film is formed.
The deep second electrode contact window 11b on the n + type impurity region 3b through which a relatively large current flows, buried in 12a, is buried almost flat.

Next, the steps of FIG. 1 are performed to complete a semiconductor device according to the manufacturing method of the first embodiment of the present invention.

4 (a) to 4 (d) and FIG. 2 are sectional views showing the steps of a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 (a) By applying a normal technique, a p-type silicon substrate 1 has a p-type channel stopper region 2 and an n + -type impurity region 14 to which a voltage different from that of the p- type silicon substrate 1 is applied.
a, An n + type impurity region 14b and a field oxide film 4 to which the same voltage as that of the p− type silicon substrate 1 is applied are formed.

FIG. 4 (b) Next, an oxide film 5 for impurity blocking of about 35 nm, 600 nm
About a first phosphosilicate glass (PSG) film 6 and a nitride film 15 (first mask layer) are sequentially grown. Then, using a normal photolithography technique, a resist (not shown) is used as a mask layer, and the nitride film 15 and the first phosphosilicate glass (PSG) are used.
The film 6 and the impurity blocking oxide film 5 are selectively etched to form a shallow first electrode contact window 7a on the n + -type impurity regions (14a, 14b). Next, the resist is removed. Next, a first selective chemical vapor deposition tungsten silicide film 8a is grown, and the shallow first electrode contact window 7a is buried almost flat.

FIG. 4 (c) Next, a chemical vapor deposition oxide film 16 of about 30 nm is grown. Then, using normal photolithography technology,
Using the resist (not shown) as a mask layer, the chemical vapor deposition oxide film 16 is selectively etched, and the first selective chemistry on the n + -type impurity region 14 a to which a voltage different from that of the p − -type silicon substrate 1 is applied. The chemical vapor deposition oxide film 16 (second mask layer) is left on the vapor deposition tungsten silicide film 8a. Next, using the same resist (not shown) and the nitride film 15 (first mask layer) as a mask layer, the first selective chemical vapor deposition on the n + -type impurity region 14 b to which the same voltage as that of the p − -type silicon substrate 1 is applied. The phase-grown tungsten silicide film 8a and then n
The + -type impurity region 14b and part of the p--type silicon substrate 1 are removed by etching, and the shallow first electrode contact window 7a is changed to the deep first electrode contact window 7b. Next, the resist is removed.

Next, a second selective chemical vapor deposition tungsten silicide film 8b is grown to bury the deep first electrode contact window 7b almost flat.

FIG. 2 Next, the remaining chemical vapor deposition oxide film 16 (second mask layer) is removed by etching. Next, the nitride film 15 (first mask layer) is removed by etching. Next, an Al film of about 1 μm is grown by a sputtering method. Then, using a normal photolithography technique, the Al film is selectively etched using a resist (not shown) as a mask layer,
An Al wiring 9 is formed. Next, the resist is removed to complete the semiconductor device according to the manufacturing method of the embodiment shown in FIG.

In the above manufacturing method, the shallow electrode contact window and the deep electrode contact window are formed by the same mask process (the deep electrode contact window requires a two-step process for its formation. And the deep electrode contact windows are formed in a self-aligned manner with each other.) These may be formed by different mask processes. In short, after the selective chemical vapor deposition conductive film is embedded in one electrode contact window, the selective chemical vapor deposition conductive film embedded with the chemical vapor deposition oxide film is masked, and only the other electrode contact window opened is opened. Nitriding on the underlying phosphosilicate glass (PSG) film as a point to embed the selective chemical vapor deposition conductive film and as an etching stopper film when selectively providing the chemical vapor deposition oxide film for the mask The point of the manufacturing method is to provide a film.

As described in the above embodiments, according to the method of manufacturing a semiconductor device of the present invention, it is not necessary to provide a wiring body interposed in order to adjust the depth of the electrode contact windows, and to form electrode contact windows of different depths. Since it is possible to easily manufacture a semiconductor device capable of directly connecting an upper wiring body made of the same layer as each conductive region via a conductive film buried flatly,
Higher integration by increasing the degree of freedom of wiring is required. An upper layer wiring body with good step coverage can be formed on a conductive film in which electrode contact windows of different depths are buried flat, and a film thickness with a large current density can be obtained. A semiconductor device suitable for mass production that enables high reliability by extending the life of the wiring body by easily and freely connecting from the thick upper wiring body can be manufactured.

[Effects of the Invention] As described above, according to the present invention, in a method for manufacturing a MIS and a bipolar semiconductor device, a first mask layer (such as a Si ₃ N ₄ film) serving as a mask layer for etching and growing a conductive film.
And a manufacturing method using a _second mask layer (such as a SiO ₂ film) to form electrode contact windows of different depths in a self-aligned manner and to form a selective chemical vapor deposition conductive film on the electrode contact windows of different depths. Since the flat burying and the prevention of film slippage of the interlayer insulating film can be easily realized, the connection between the upper wiring body made of the same layer and the plurality of conductive regions formed at the bottom and having electrode contact windows having different depths is different. Since the structure in which the electrode contact windows of different depths are simultaneously formed through the conductive film buried flat respectively can be easily formed, the respective electrode contact windows of different depths can be easily formed through the conductive film buried flat respectively. Since the conductive region can be directly connected to the upper layer wiring body formed of the same layer, the degree of freedom of wiring can be increased, and higher integration can be achieved. By take a connection from it to form a body and the current density is increased take large thickness upper wiring body easily it can allow reliable by being able to increase the life of the wire body. That is, it is possible to manufacture a semiconductor device suitable for mass production that enables formation of a highly integrated and highly reliable semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a schematic side sectional view of a semiconductor device obtained by the manufacturing method according to the first embodiment of the present invention, and FIG.
FIGS. 3 (a) to 3 (f) (including partially modified steps (g) to (i)) of a semiconductor device obtained by the manufacturing method of the embodiment of FIG. 4 (a) to 4 (d) are process cross-sectional views of the first embodiment of the manufacturing method.
Is a process sectional view of a semiconductor device manufacturing method according to a second embodiment of the present invention, and FIG. 5 is a schematic side sectional view of a semiconductor device obtained by a conventional manufacturing method. In the figure, 1 is a p- type silicon substrate, 2 is a p-type channel stopper region, 3a is an n + type impurity region through which a relatively small current flows, 3b is an n + type impurity region through which a relatively large current flows, 4 is a field oxide film Reference numeral 5 denotes an oxide film for blocking impurities, 6 denotes a first phosphosilicate glass (PSG) film, 7 denotes a first electrode contact window, 7a denotes a shallow first electrode contact window, and 7b denotes a shallow first electrode contact window. Reference numeral 8 denotes a first electrode contact window burying conductive film, 8a denotes a shallow first electrode contact window burying conductive film (selective chemical vapor deposition tungsten silicide film), and 8b denotes a deep first electrode contact window burying conductive film (selection). 9, 9a, 9b, 9c are first-layer Al wirings, 10 is a second phosphosilicate glass (PSG) film, 11a is a shallow second electrode contact window, 11b is a deep 12a is a shallow second electrode contact window buried conductive film (selective chemical vapor deposition tungsten silicide film), 12b is a deep second electrode contact window buried conductive film (selective chemical vapor deposition tungsten silicide film) Reference numeral 13 denotes a second-layer Al wiring, and 14a denotes an n to which a voltage different from that of the p-type silicon substrate is applied
A + -type impurity region 14b is an n + -type impurity region to which the same voltage as that of the p- type silicon substrate is applied.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication H01L 29/73

Claims (2)

(57) [Claims] A step of selectively forming a first conductive region on a semiconductor substrate or on a semiconductor substrate via an insulating film;
A step of stacking a first interlayer insulating film, a step of selectively forming a second conductive region on the first interlayer insulating film, a step of stacking a second interlayer insulating film, Laminating a first mask layer on the interlayer insulating film, and (a) selectively forming the first mask layer and the second interlayer insulating film on the first and second conductive regions. Opening a hole in the
A step of burying an electrode contact window opened on the second conductive region with a first selective chemical vapor deposition conductive film, a step of stacking an insulating film, a step of stacking an insulating film, By selectively etching away the insulating film using the photoresist layer formed on the second conductive region as a mask layer, a second conductive film is selectively formed on the first selective chemical vapor deposition conductive film on the second conductive region. Forming a mask layer, and opening the first interlayer insulating film in which the second interlayer insulating film on the first conductive region is opened, and removing the photoresist layer And a step of burying a second selective chemical vapor deposition conductive film in an electrode contact window on the first conductive region using the second mask layer, or (b) the first and second conductive layers. The first mask layer over the region, the first and Selectively opening the second interlayer insulating film, and filling the electrode contact window opened on the second conductive region with a first selective chemical vapor deposition conductive film to be flat, and Partially embedding an electrode contact window opened on the conductive region of step (a), laminating an insulating film, and insulating the first mask layer and the selectively formed photoresist layer as a mask layer. By selectively etching away the film, a second layer is selectively formed on the first selective chemical vapor deposition conductive film on the second conductive region.
Forming a mask layer, removing the photoresist layer, and forming a second selective chemical vapor in an electrode contact window buried halfway over the first conductive region by the second mask layer. After the step (a) or (b) of embedding the grown conductive film flatly, the step of etching and removing the second mask layer by the first mask layer; A method for manufacturing a semiconductor device, comprising: a step of etching and removing a mask layer; and a step of selectively forming an upper wiring body. 2. The method according to claim 1, wherein the first conductive region is formed of a semiconductor substrate, and the electrode contact windows formed at different depths are formed by partially opening the conductive layer in addition to the interlayer insulating film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein: