JPS6092623A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6092623A JPS6092623A JP58200383A JP20038383A JPS6092623A JP S6092623 A JPS6092623 A JP S6092623A JP 58200383 A JP58200383 A JP 58200383A JP 20038383 A JP20038383 A JP 20038383A JP S6092623 A JPS6092623 A JP S6092623A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- film containing
- phosphorus
- containing boron
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052796 boron Inorganic materials 0.000 claims abstract description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 9
- 239000011574 phosphorus Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000001947 vapour-phase growth Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 12
- 229920005591 polysilicon Polymers 0.000 abstract description 12
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000002950 deficient Effects 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 10
- 239000002184 metal Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 101000651178 Homo sapiens Striated muscle preferentially expressed protein kinase Proteins 0.000 description 1
- 102100027659 Striated muscle preferentially expressed protein kinase Human genes 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法に係シ、特に半導体素
子表面にＣＶＤ法によｊ５１ＪＰ８Ｇ膜を始めとする層
間絶縁膜を形成せしめる場合に、よシ平滑な構造を有し
、かつ耐湿性に優れた絶縁膜を形成させる方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly when forming an interlayer insulating film such as a j51JP8G film on the surface of a semiconductor element by CVD method, it is possible to obtain a smoother structure. The present invention relates to a method for forming an insulating film having the same characteristics as above and having excellent moisture resistance.
一般に半導体素子の層間絶縁膜としては、形成された素
子と金属配線とを電気的に分離させるために、 ＣＶＤ
（Ｃｈｅｍｉｃａｌ Ｖａｐｏｕｒ Ｄｅｐｏｓｉｔ
ｉｏｎ）法によシ形成された各種酸化膜が用いられてい
る。Generally, CVD is used as an interlayer insulating film for semiconductor devices to electrically isolate the formed device and metal wiring.
(Chemical Vapor Deposit
Various oxide films formed by the ion method are used.
特にＢＰＳＧ膜（ボロンと燐を含む酸化膜）は、電気的
なパッシベーション効果を有し、素子表面を平滑化させ
るためのりフロー効果も犬でアシ、耐湿性の点でも問題
がない等の長所を有していることによ多層間絶縁膜とし
て非常に有望である。In particular, the BPSG film (oxide film containing boron and phosphorus) has advantages such as having an electrical passivation effect, a glue flow effect to smooth the element surface, and no problems in terms of moisture resistance. This makes it very promising as a multilayer insulating film.
ところが、素子表面を滑らかな形状とするためにはりフ
ロー用のＢＰ８Ｇ膜を比較的厚く成長させる必要がアシ
、この時にヒロックと称する突起物が発生し易い。その
ため塗布したレジストがヒロックのところで薄くなった
シ、マスクの損傷によシマスフ欠陥が発生して不必要な
開孔が生じ易く、しかもヒロックとＢＰ８Ｇ膜との界面
はエツチング液が浸透し易いので、その開孔はＢＰＳＧ
膜の下層の深い所まで及び場合によってはゲートとなる
ポリシリコン（以下ポリシリと称す）層、又は、ソース
（またはドレイン）となる拡散層に達する。However, in order to make the element surface smooth, it is necessary to grow the BP8G film for beam flow relatively thickly, and at this time protrusions called hillocks are likely to occur. As a result, the applied resist becomes thinner at the hillocks, mask defects occur due to damage to the mask, and unnecessary openings are likely to occur.Moreover, the etching solution easily penetrates into the interface between the hillocks and the BP8G film. The opening is BPSG
It reaches deep into the lower layer of the film, and in some cases reaches a polysilicon (hereinafter referred to as polysilicon) layer that becomes a gate or a diffusion layer that becomes a source (or drain).
それ故、上述したＢＰＳＧ膜成長時に発生するヒロック
に起因した欠陥孔によシ配線ショ＝トを生じ製造歩留り
の低下を招く。Therefore, defective holes caused by hillocks generated during the growth of the BPSG film described above cause wiring shorts, resulting in a decrease in manufacturing yield.
、本発明はかかる難点に鑑みなされたもので、その特徴
とするところは、形成された素子と金属配線との間の層
間絶縁膜をＰＳＧ膜（燐を含む酸化膜）、Ｂｉ２Ｏ膜（
ボロンを含、む酸化膜）、及びＢＰＥＧ膜の三層構造と
することによシ、ＢａＯ膜のエツチング速度が遅いこと
を利用して、ＢＰＳＧ膜にヒロックが存在しても不必要
な欠陥孔が下層まで到達しないようにし、金属配線層に
よるポリシリ層と半導体領域層との電気的接触が生ずる
のを防止する点、及びバターニング後の熱処理工程によ
って、ＢａＯ膜からボロンがポリシリ層へ拡散するのを
ＰＳＧ膜によシ防止する点、そしてＰＳＧ膜が界面のパ
ッシベーション効果を有している点にある。The present invention has been developed in view of these difficulties, and is characterized by the fact that the interlayer insulating film between the formed element and the metal wiring is a PSG film (an oxide film containing phosphorus), a Bi2O film (
By using a three-layer structure consisting of an oxide film containing boron (oxide film containing boron) and a BPEG film, unnecessary defect holes can be eliminated even if hillocks exist in the BPSG film by taking advantage of the slow etching rate of the BaO film. In addition, boron is diffused from the BaO film into the polysilicon layer by the heat treatment process after buttering. The PSG film prevents this from occurring, and the PSG film has an interface passivation effect.
以下本発明を図面に基づいて、実施例につき、従来方法
と比較して、詳細に説明する。Hereinafter, the present invention will be described in detail based on the drawings, using examples and comparing with a conventional method.
第１図（ａ）Ｉ′５至第１図（Ｃ）は、ＢＰｉ９Ｇ膜の
みを用いた層間絶縁膜形成のための一実施例でめシ、Ｍ
ＯＳ）ランジスタへ適用した場合の工程断面図である。FIG. 1(a) I'5 to FIG. 1(C) show an example of forming an interlayer insulating film using only a BPi9G film.
FIG. 3 is a cross-sectional view of the process when applied to a transistor (OS).
第１図（ａ）において、１０はｐ型シリコン基板、２０
は基板に埋設せる酸化膜、３０はゲート酸化膜、４０は
ポリシリコン等のゲート電極、５０はソース、ドレイン
形成のためのイオンビームを各々示す。この方法では、
上記構造の素子に第１図（ｂ）で示した如（、ＢＰＳＧ
膜８０全８０させ箋パターニングを行ってコンタクト穴
の開孔をした後、９００〜１０００℃付近の熱処理を施
してＢＰ８Ｇ膜の平滑化を行う。しかしながら、ＢＰＳ
Ｇ膜８０全８０に伴りてヒロックが発生し、コンタクト
穴の開孔に使用するエツチング液によってヒロックの部
分から不要な欠陥孔９０が形成される。これに起因して
第１図（Ｃ）に示した如（ＢＰＳＧ膜８０全８０に形成
された金属配＃ｉ！１００により、ポリシリ電極と半導
体領域の電気的接触が生じ製造歩留シが低下する。本発
明は平滑な構造を有し、かつ耐湿性に優れた絶縁膜を形
成する方法において、上記方法の欠点を除去するために
なされたもので、Ｐ２Ｏ膜、Ｂ１０膜、ＢＰＳＧ膜の三
層構造を有することを特徴とするものである。In FIG. 1(a), 10 is a p-type silicon substrate, 20
Reference numeral 30 indicates an oxide film buried in the substrate, 30 indicates a gate oxide film, 40 indicates a gate electrode such as polysilicon, and 50 indicates an ion beam for forming a source and a drain. in this way,
As shown in FIG. 1(b), the element with the above structure is
After patterning the entire film 80 and forming contact holes, the BP8G film is smoothed by heat treatment at around 900 to 1000°C. However, B.P.S.
Hillocks occur along with the entire G film 80, and unnecessary defective holes 90 are formed from the hillock portions by the etching solution used to open the contact holes. Due to this, as shown in FIG. 1(C), the metal interconnection #i!100 formed on the entire BPSG film 80 causes electrical contact between the polysilicon electrode and the semiconductor region, resulting in a decrease in manufacturing yield. The present invention was made in order to eliminate the drawbacks of the above methods in a method of forming an insulating film having a smooth structure and excellent moisture resistance. It is characterized by having a layered structure.
次に本発明の一実施例を図面を参照しつつ詳細に説明す
る。Next, one embodiment of the present invention will be described in detail with reference to the drawings.
第２図（ａ）乃至第２図（Ｃ）は本発明の一実施例でめ
シ、ＭＯＳトランジスタへ適用した場合の工程断面図で
ある。第２図（ａ）において、１１０はｐ型シリコン基
板、１２０は基板に埋設せる酸化膜、１３０はゲート酸
化膜、１４０はポリシリコンのゲート電極、１５０はソ
ース・ドレイン形成のためのイオン・ビームを各々示す
。FIGS. 2(a) to 2(C) are process sectional views of one embodiment of the present invention when applied to a MOS transistor. In FIG. 2(a), 110 is a p-type silicon substrate, 120 is an oxide film buried in the substrate, 130 is a gate oxide film, 140 is a polysilicon gate electrode, and 150 is an ion beam for forming the source and drain. are shown respectively.
上記構造の素子に第２図（ｂ）に示した如（、Ｐ８Ｇ膜
１８０を成長させ、次いで該ＰＳＧ膜上に、ＢａＯ膜（
ボロンを含む酸化膜）１９０を成長させ、さらに２層の
Ｐ８Ｇ膜上にＢＰＳＧ膜（ボロンと燐を含む酸化膜）２
００を成長せしめる。この工程によシ第２図（ｂ）に示
されたヒロックによるコンタクト開孔の際の不要な欠陥
孔２１０はエツチング速度の遅いＢ８Ｇ膜上で喰い止め
られ、第２図（Ｃ）に示した如く金属配線２２０による
ポリシリ電極と半導体領域の電気的接触は皆無に近くな
る。As shown in FIG. 2(b), a P8G film 180 is grown on the device having the above structure, and then a BaO film (
A BPSG film (oxide film containing boron and phosphorus) 2 is grown on the two-layer P8G film.
Let 00 grow. Through this process, unnecessary defective holes 210 caused by hillocks during contact opening shown in FIG. 2(b) are blocked on the B8G film, which has a slow etching rate, and are removed as shown in FIG. 2(c). As a result, electrical contact between the polysilicon electrode and the semiconductor region by the metal wiring 220 becomes almost non-existent.
以上の説明ではＳｉ基板上にポリシリの電極が形成され
たＭＯＳトランジスタについて述べたが、本発明はこれ
に限られるものではなく、ポリシリの代シに高温に耐え
得る電極材料であるモリブデン等の金属、あるいはシリ
サイド等を用いた場合にも適用できる。In the above explanation, a MOS transistor in which a polysilicon electrode is formed on a Si substrate has been described, but the present invention is not limited to this. It can also be applied to cases where silicide or the like is used.
以上説明したように本発明によれば、半導体素子表面に
ＣＶＤ法によシ順次ＰＳＧ膜、ＢａＯ膜を形成している
ので、ＢＰＳＧ膜成長時にヒロックが発生しても不必要
な欠陥孔が深く開孔されることを防止でき、それ故その
後の金属配線により半導体領域とポリシリ層との電気的
接触が生ずることを防げる。そしてさらにパターニング
後の熱処理によるボロンのポリシリ層への拡散を防止で
きる。序た、ＢＰＳＧ膜を最上層に用いていることによ
シ、耐湿性に優れ、金属配線層の断切れも発生しない半
導体装置が得られる。As explained above, according to the present invention, the PSG film and the BaO film are sequentially formed on the surface of the semiconductor element by the CVD method, so even if hillocks occur during the growth of the BPSG film, unnecessary defect holes will be deep. Opening can be prevented, and therefore electrical contact between the semiconductor region and the polysilicon layer by subsequent metal wiring can be prevented. Further, it is possible to prevent boron from diffusing into the polysilicon layer due to heat treatment after patterning. First, by using the BPSG film as the top layer, a semiconductor device with excellent moisture resistance and no breakage of the metal wiring layer can be obtained.
以上、本発明の特徴をＭＯＳデバイスを例に挙げて説明
したが、本発明による方法が他のデバイスにも有効なの
は首うまでもない。Although the features of the present invention have been described above using MOS devices as an example, it goes without saying that the method according to the present invention is also effective for other devices.
第１図および第２図はそれぞれ従来技術および本発明の
一実施例を説明するための半導体装置の工程断面図であ
る。
尚、図において、１０，１１０・・・・・・シリコン基
板、２０，１２０・・・・・・酸化膜、３０，１３０・
・・・・・ゲート酸化膜、４０，１４０・・・・・・ゲ
ート電極、５０．１５０・・・・・・イオン・ビーム、
６０，１６０・・・・・・ソース領域、７０，１７０・
・・・・・ドレイン領域、８０．２００・・・・・・Ｂ
Ｐ８Ｇ膜、１９０・・・・・・Ｂ１０膜、１８０・・・
・・・Ｐ２Ｏ膜、１００，２００・・・・・・金属配線
。
（ｂ）
（Ｃ）
８７ 図FIG. 1 and FIG. 2 are process cross-sectional views of a semiconductor device for explaining a conventional technique and an embodiment of the present invention, respectively. In the figure, 10, 110... silicon substrate, 20, 120... oxide film, 30, 130...
...Gate oxide film, 40,140...Gate electrode, 50.150...Ion beam,
60,160...source area, 70,170...
...Drain region, 80.200...B
P8G film, 190...B10 film, 180...
...P2O film, 100,200...metal wiring. (b) (C) 87 Figure
Claims (1)
体装置の製造方法において、前記絶縁膜を１気相成長法
によシ、燐を含む酸化膜、ボロンを含む酸化膜、さらに
ボロンと燐とを含む酸化膜を１１＠次成長させて形成す
ることを特徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device in which an insulating film is formed on a substrate on which a semiconductor element is formed, the insulating film is formed by one vapor phase growth method, an oxide film containing phosphorus, an oxide film containing boron, and further an oxide film containing boron and phosphorus are formed. A method for manufacturing a semiconductor device, characterized in that an oxide film containing the following is formed by 11th order growth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58200383A JPS6092623A (en) | 1983-10-26 | 1983-10-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58200383A JPS6092623A (en) | 1983-10-26 | 1983-10-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6092623A true JPS6092623A (en) | 1985-05-24 |
Family
ID=16423403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58200383A Pending JPS6092623A (en) | 1983-10-26 | 1983-10-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6092623A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62160743A (en) * | 1986-01-09 | 1987-07-16 | インテル・コーポレーシヨン | Formation of insulated contact aperture on semiconductor article |
| KR100950469B1 (en) | 2007-03-26 | 2010-03-31 | 주식회사 하이닉스반도체 | Method for manufacturing inter layer dielectric in semiconductor device |
-
1983
- 1983-10-26 JP JP58200383A patent/JPS6092623A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62160743A (en) * | 1986-01-09 | 1987-07-16 | インテル・コーポレーシヨン | Formation of insulated contact aperture on semiconductor article |
| KR100950469B1 (en) | 2007-03-26 | 2010-03-31 | 주식회사 하이닉스반도체 | Method for manufacturing inter layer dielectric in semiconductor device |
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