JPS5921044A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a wiring pattern flatly, and to prevent disconnection at a position where wirings cross by filling a groove having insulating property and forming a conductor film, the surface thereof is formed on approximately the same plane as the surface of a semiconductor layer and a conductor film pattern disposed on the surface of the semiconductor layer. CONSTITUTION:An SiO2 film 2 and a GaAs semiconductor layer 1 are etched selectively while using a resist 3 as a mask to form the grooves 4 of a pattern to the semiconductor layer 1. A protective film is removed, the surface of the GaAs semiconductor layer 1 is coated, and a conductor film 6 is formed in thickness through which the grooves 4 are filled completely. An SiO2 film 8, films 7 and the conductor film 6 are etched in succession according to a resist pattern 9. An SiO2 film 12 is formed to the whole surface on the semi-insulating GaAs semiconductor layer, and a region using a resist 13 as a source and a drain and the SiO2 film 12 on a gate electrode 11 are removed selectively. Each electrode and an opening corresponding to the required position of the wiring pattern 10 of a first layer are disposed to an SiO2 film 19, a film such as a titanium-gold film is formed, and the wiring pattern 20 of a second layer is formed through patterning.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing intersecting wiring patterns.

(b) Prior art and problems Semiconductor layer surface ζIn this integrated circuit device, if the electrodes of transistors, diodes, etc. However, in this case, the wiring pattern is usually formed using two or more layers of conductive films.

That is, normally, the first layer of the conductor layer provided through the insulating film is subjected to the required patterning to form the first layer of the wiring pattern. After forming the interlayer insulating film (this is the required opening []), the entire second layer conductor film is covered, and this second layer conductor film is patterned as required. A second layer of wiring patterns is formed.

According to the method described in No. 611, when the wiring patterns are crossed, the first layer wiring pattern 1 is interrupted and the interlayer insulating film F formed thereon causes step noise, and the second layer wiring pattern is generally It has a shape that traverses the entire step. The interlayer insulating film is formed using chemical vapor deposition method (hereinafter abbreviated as CVD method).
Therefore, in the case of a fully deposited film such as silicon dioxide (Sing), the insulating film is deposited thicker on the first layer wiring, especially on the edge portions than on a flat surface. This tends to cause disconnections in the second layer wiring pattern, and short circuits between the second layer wirings may occur due to unintended conductor film remaining during patterning due to etching of the second layer wiring. may occur.

As a countermeasure for these problems, for example, a method of coating a silsesquioxane prepolymer or the like and curing it with heat to make the entire surface of the insulating film flat, or a method of forming the interlayer insulating film into a phosphorus silicide containing germanium oxide (GeOt) k. However, these manufacturing methods that require high-temperature heat treatment are often not appropriate for compound semiconductors.

In addition, as another countermeasure against the above-mentioned problems, the shape of the cross section of the first layer wiring pattern can be made so that the level difference is reduced, for example, by making all the grooves at the edges smooth or by reducing the slope of the side edges. However, if the cross-sectional shape of such a wiring pattern is
1.I got stuck and used this as a mask for impurity ion implantation 7
In addition, the effect of shaping the cross section of the first layer wiring pattern is not necessarily sufficient.

In order to promote the miniaturization of patterns of semiconductor integrated circuit devices, a method of manufacturing cross wiring that replaces or complements the above-mentioned conventional technology ζ is required.

(c) Object of the Invention The entire purpose of the present invention is to provide a highly reliable method of manufacturing a cross wiring that can be easily applied to semiconductor devices, particularly compound semiconductor integrated circuit devices.

(d) Structure of the Invention The main feature of the present invention is to provide a semiconductor layer with a predetermined shape of insulation [
7. Filling the groove to form a conductor film covering the entire surface of the semiconductor layer, and then forming a hindlimb membrane with a flat surface in contact with the conductor film, and the conductor film fully selective 1
a conductive film 11 disposed on the surface of the semiconductor layer;
□1 1゛ This is achieved by having a conductive film pattern and a complete forming process.

(e) Embodiments of the Invention The present invention will be specifically explained below with reference to all the drawings.

FIGS. 1 to 9 are cross-sectional views showing an embodiment of a gallium-arsenide (GaAs) compound semiconductor integrated circuit device using a blank barrier type FET element.

Refer to FIG. 1. A silicon dioxide (S i Ox )N2 film is selectively formed on the semiconducting GaAs semiconductor layer 1.
As a mask, for example, silicon y (St) ions are placed in the part that forms the active region of the FET, 59 (: K e V
) at a dose of 1 to 2XIO"(cm")
] Inject to the extent of t.

See FIG. 2 the semi-insulating GaAs semiconductor layer 1 and S10°1111
The first layer wiring is buttered on the resist (for example, product number AZ13507) 3 that has been formed over the 5-lot film 2 using the resist 3 as a mask.
And the entire GaAs semiconductor layer 1 is selectively etched to form a GaAs semiconductor layer 1.
In the As semiconductor layer II, all the grooves 4 of the pattern described above are formed. However, in this embodiment J, the depth of the groove 4 is approximately equal to the thickness l of the gate electrode, for example, about 0.
．． 4 [μm].

Refer to Fig. 3. CVD method after removing the resist 3 and 510 gM2? Therefore, the thickness is about 0.1 (μm: 1).

A protective film (not shown) consisting of, for example, hydrogen
: Temperature 8 in nitrogen (N2) atmosphere containing (H6)
Heat treatment is performed for about 20 minutes (50 1C). As a result of this heat treatment, the previously implanted St ions are activated and the n-type region 5 is formed.

Next, the conductive layer 6 is removed to cover the entire surface of the GaAs semiconductor layer and to a thickness that completely fills the groove 4 provided previously. In this embodiment, (iii) the conductor film 6 is made of titanium tungsten silicide ('I'1WSi)', which is a suitable material for the gate electrode of a s-metal barrier type FET! <, ri method, etc. (form from this.

Since the conductive film 6 in FIG. 4 will have dents as shown in FIG. A film 7 with a flat surface is provided, and an 810° 11#1l film with a thickness of about 0.5 (μm) is provided.
After Hr formation, ζ resist 9? ! :Used as a mask for patterning of the ingot electrode.

Refer to Figure 5. Reactive ion etching method etc. (Thus, the above-mentioned
The Stow film 8, film 7, and conductor film 6 are sequentially etched according to the cyst pattern 9. However, when etching the conductor film 6, the etching speed of the conductor film 6 and the film 7 is the same, and the recessed portion of the conductor M6 in the groove 40 is
Also in this case, all conditions such as gas pressure are selected so that the ethosangular plane becomes a plane parallel to the surface of the semiconductor layer 10.

When the surface 1111 of the semiconductor layer I is exposed (the etching is completely stopped and the masked SiOx M 8 and film 7 are peeled off and removed E), the state shown in FIG. 6 is obtained.

Refer to Fig. 6 1) After the process 11-1 is completed, the wiring pattern 10 of the first layer is buried with the surface of the semiconductor M 1 t as a plane, and then buried. The above-mentioned もtype region 5-1=l
After the gate electrode 1 is formed, a photo resist (131C) is used as a mask.
S10 of the region and gate electrode 11 to be made into source and T'1 twin by etching process! The membrane 12 is selectively (
Remove this. ? For example, S 1k175[Kev
``Ji %p 1.7 x 10'' (c
tn') Ion implantation is performed using the gate electrode 11, the Sin film 12, and the entire mask U2.

Figure 8: We S 102 film 12 gold removed (after removal, S was applied again to the entire surface)
The preservation film consisting of iO film etc. is completely formed and the temperature is 750 [℃]
Heat treatment is performed for about 15 minutes. By this heat treatment, the St ions are activated and n-type regions 14 and 15, which serve as source and drain regions, are formed.

Next, the entire surface of the semi-insulating GaAs semiconductor layer (this SiO
The area where the source and drain electrodes are placed in the moon
Open [1] For example, gold/gel manila A (A
u G e )--Gold (Au) 7 &: Vapor deposited. After the lift-off treatment, the GaAs semiconductor layer is alloyed by heat treatment at a temperature of about 450 (°C), and the source electrode 17 is in ohmic contact with the n-type regions 14 and 15, respectively.
and do/in electrode 18 is completely formed.

Refer to Fig. 9. Furthermore, CVT) method ζ Therefore, S i 02 'c'<(
For example, its i Ox VI416k is 0
．． The film 19 is 5 in 2 with a thickness of about 6 [μm]. Then such sio.

Membrane 191, @electrode and wiring pattern of the first layer -71
For example, a titanium (Ti)-gold (Au) film with a thickness of 0.6 (μm) is placed on all openings corresponding to the required positions of
'.

When the wiring pattern 20 of the second layer is completely formed, the second layer wiring pattern 20 is completely formed by butter-ning.

The wiring formed by the manufacturing method described above
8- is also a flat line where the first layer and second layer intersect, and there is a possibility that a disconnection as explained above will occur. 1./) There is no possibility that the short circuit sound will occur.

In Example I, (J first layer wiring pattern 10 and conductor 11!・The same conductor as the drain electrode
It is also possible to form them in sequence.

In this example, the semi-insulating semiconductor layer element and the first layer wiring pattern are not formed, but the 217 conductor layer (this After the formation of the exposed surface of the formed groove (this method is to remove the insulating film or the conductive semiconductor layer f), the high resistance area is placed in the area of the lever ( This method of arranging the grooves is also possible.

In addition, in the above-mentioned implementation [HJl], the depth of the groove is made to match the total thickness of the gate electrode, but it is possible to select the entire resistance value of the first layer wiring pattern depending on the depth of the groove.
Product GbT f=R-+-sing,-A Compilation: l m +
[4 壬 い 1K 類栖 ↓ Te - ・ can be done.

Furthermore, since the wiring pattern of the first layer is buried inside the conductor, the wiring pattern of the second layer can also be routed directly above the first layer via the diastolic membrane, and the gate The WJ product required for gluing the electrodes and wiring is reduced compared to the conventional structure, making it possible to achieve the same integration density.

(f) Effects of the Invention As explained in the present invention, the intersecting wiring patterns of a semiconductor device are formed flat, thereby preventing disconnections at the positions where the wiring intersects, which has been a major cause of trouble in the past. It is possible to exclude it.

Furthermore, the first layer wiring pattern is formed from the same conductor layer as the electrodes, and can be manufactured in a number of steps equal to or less than that of a conventional semiconductor device having a cross-over pattern S. It can be easily carried out industrially.

[Brief explanation of drawings]

1 to 9 are cross-sectional views showing embodiments of the present invention. In the figure, 1 is a semi-insulating semiconductor layer, 4 is a groove, 5 is an n-type region, 6 is a conductor film, 7 is a film, 10 is a first layer wiring pattern, 11 is a gate electrode, 14 and 15 are n+ type area,
17 is a source electrode, 18 is a drain electrode, 19 is S i
O indicates the film, and 2o indicates the wiring pattern of the second layer. 11- Adventure 1 Brilliant 2 Mouth 5 Mouth smart S Country 0 − =12- Year old 4 Illustration Y day

Claims (1)

[Claims] A conductor film covering the surface of the semiconductor layer is formed by disposing the semiconductor layer in a desired shape having insulating properties at least in the vicinity of its exposed surface, and filling the semiconductor layer with the conductor film to cover the surface of the semiconductor layer. 1. Selectively remove all of the hindlimb membrane and the conductive film,
A semiconductor characterized by comprising the steps of forming a conductor film whose surface is substantially coplanar with the surface of the semiconductor layer by filling the semiconductor layer, and a conductor film pattern disposed on the surface of the semiconductor layer. Method of manufacturing the device.